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1.1 root 1: ;;- Machine description the Hitachi SH
2: ;; Copyright (C) 1993 Free Software Foundation, Inc.
3: ;; Contributed by Steve Chamberlain ([email protected])
4:
5: ;; This file is part of GNU CC.
6:
7: ;; GNU CC is free software; you can redistribute it and/or modify
8: ;; it under the terms of the GNU General Public License as published by
9: ;; the Free Software Foundation; either version 2, or (at your option)
10: ;; any later version.
11:
12: ;; GNU CC is distributed in the hope that it will be useful,
13: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: ;; GNU General Public License for more details.
16:
17: ;; You should have received a copy of the GNU General Public License
18: ;; along with GNU CC; see the file COPYING. If not, write to
19: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20:
21: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
22:
23:
24:
25: ;; -------------------------------------------------------------------------
26: ;; Attributes
27: ;; -------------------------------------------------------------------------
28:
29: ; Target CPU.
30:
31: (define_attr "cpu" "sh0,sh1,sh2,sh3"
32: (const (symbol_ref "sh_cpu")))
33:
34: (define_attr "type" "cbranch,ctable,jump,arith,other,load,store,move,smpy,dmpy,return,pload"
35: (const_string "other"))
36:
37: ; If a conditional branch destination is within -100..100 bytes away
38: ; from the instruction it can be 2 bytes long. Something in the
39: ; range -4000..4000 bytes can be 6 bytes long, all other conditional
40: ; branches are 8 bytes long.
41:
42: ; An unconditional jump which can reach forward or back 4k can be
43: ; 6 bytes long (including the delay slot). If it is too big, it
44: ; must be 8 bytes long.
45:
46: ; All other instructions are two bytes long by default.
47:
48: (define_attr "length" ""
49: (cond [(eq_attr "type" "cbranch")
50: (if_then_else (and (ge (minus (pc) (match_dup 0))
51: (const_int -100))
52: (le (minus (pc) (match_dup 0))
53: (const_int 100)))
54: (const_int 2)
55: (if_then_else (and (ge (minus (pc) (match_dup 0))
56: (const_int -4000))
57: (le (minus (pc) (match_dup 0))
58: (const_int 4000)))
59: (const_int 6)
60: (const_int 8)))
61:
62: (eq_attr "type" "jump")
63: (if_then_else (and (ge (minus (pc) (match_dup 0))
64: (const_int -4000))
65: (le (minus (pc) (match_dup 0))
66: (const_int 4000)))
67: (const_int 4)
68: (const_int 6))
69: ] (const_int 2)))
70:
71: ;; (define_function_unit {name} {num-units} {n-users} {test}
72: ;; {ready-delay} {issue-delay} [{conflict-list}])
73:
74: (define_function_unit "memory" 1 1 (eq_attr "type" "load") 1 0)
75: (define_function_unit "mpy" 1 1 (eq_attr "type" "smpy") 3 0)
76: (define_function_unit "mpy" 1 1 (eq_attr "type" "dmpy") 5 0)
77:
78: (define_attr "needs_delay_slot" "yes,no"
79: (cond [(eq_attr "type" "jump") (const_string "yes")
80: (eq_attr "type" "return") (const_string "yes")]
81: (const_string "no")))
82:
83: (define_delay
84: (eq_attr "needs_delay_slot" "yes")
85: [(eq_attr "in_delay_slot" "yes") (nil) (nil)])
86:
87:
88: (define_attr "dump" "yes,no,must" (const_string "no"))
89: (define_attr "constneed" "yes,no" (const_string "no"))
90: (define_attr "smallestsize" "" (const_int 2))
91: (define_attr "largestsize" "" (const_int 8))
92: (define_attr "constantsize" "" (const_int 4))
93:
94: (define_attr "in_delay_slot" "maybe,yes,no"
95: (cond [(eq_attr "type" "cbranch") (const_string "no")
96: (eq_attr "type" "jump") (const_string "no")
97: (eq_attr "type" "pload") (const_string "no")
98: (eq_attr "type" "return") (const_string "no")
99: (eq_attr "length" "2") (const_string "yes")
100: (eq_attr "length" "4,6,8,10,12") (const_string "no")
101: ] (const_string "yes")))
102:
103:
104:
105: ;; -------------------------------------------------------------------------
106: ;; SImode signed integer comparisons
107: ;; -------------------------------------------------------------------------
108:
109: (define_insn ""
110: [(set (match_operand:SI 0 "arith_reg_operand" "=r")
111: (eq:SI (reg:SI 18)
112: (const_int 1)))]
113: ""
114: "movt %0 !movt1")
115:
116: (define_insn ""
117: [(set (reg:SI 18) (gt (match_operand:SI 0 "arith_reg_operand" "r")
118: (const_int 0)))]
119: ""
120: "cmp/pl %0")
121:
122: (define_insn ""
123: [(set (reg:SI 18) (ge (match_operand:SI 0 "arith_reg_operand" "r")
124: (const_int 0)))]
125: ""
126: "cmp/pz %0")
127:
128: (define_insn "cmpeqsi_t"
129: [(set (reg:SI 18) (eq (match_operand:SI 0 "arith_reg_operand" "r,z")
130: (match_operand:SI 1 "arith_operand" "r,I")))]
131: ""
132: "cmp/eq %1,%0")
133:
134:
135: (define_insn "cmpgtsi_t"
136: [(set (reg:SI 18) (gt (match_operand:SI 0 "arith_reg_operand" "r")
137: (match_operand:SI 1 "arith_reg_operand" "r")))]
138: ""
139: "cmp/gt %1,%0")
140:
141: (define_insn "cmpgesi_t"
142: [(set (reg:SI 18) (ge (match_operand:SI 0 "arith_reg_operand" "r")
143: (match_operand:SI 1 "arith_reg_operand" "r")))]
144: ""
145: "cmp/ge %1,%0")
146:
147: (define_insn "cmpltsi_t"
148: [(set (reg:SI 18) (lt (match_operand:SI 0 "arith_reg_operand" "r")
149: (match_operand:SI 1 "arith_reg_operand" "r")))]
150: ""
151: "cmp/gt %0,%1")
152:
153: (define_insn "cmplesi_t"
154: [(set (reg:SI 18) (le (match_operand:SI 0 "arith_reg_operand" "r")
155: (match_operand:SI 1 "arith_reg_operand" "r")))]
156: ""
157: "cmp/ge %0,%1")
158:
159:
160: ;; -------------------------------------------------------------------------
161: ;; SImode unsigned integer comparisons
162: ;; -------------------------------------------------------------------------
163:
164: (define_insn "cmpgeusi_t"
165: [(set (reg:SI 18) (geu (match_operand:SI 0 "arith_reg_operand" "r")
166: (match_operand:SI 1 "arith_reg_operand" "r")))]
167: ""
168: "cmp/hs %1,%0")
169:
170: (define_insn "cmpgtusi_t"
171: [(set (reg:SI 18) (gtu (match_operand:SI 0 "arith_reg_operand" "r")
172: (match_operand:SI 1 "arith_reg_operand" "r")))]
173: ""
174: "cmp/hi %1,%0")
175:
176: (define_insn "cmpleusi_t"
177: [(set (reg:SI 18) (leu (match_operand:SI 0 "arith_reg_operand" "r")
178: (match_operand:SI 1 "arith_reg_operand" "r")))]
179: ""
180: "cmp/hs %0,%1")
181:
182: (define_insn "cmpltusi_t"
183: [(set (reg:SI 18) (ltu (match_operand:SI 0 "arith_reg_operand" "r")
184: (match_operand:SI 1 "arith_reg_operand" "r")))]
185: ""
186: "cmp/hi %0,%1")
187:
188: ;; We save the compare operands in the cmpxx patterns and use them when
189: ;; we generate the branch.
190:
191: (define_expand "cmpsi"
192: [(set (reg:SI 18) (compare (match_operand:SI 0 "arith_reg_operand" "")
193: (match_operand:SI 1 "arith_reg_operand" "")))]
194: ""
195: "
196: { sh_compare_op0 = operands[0];
197: sh_compare_op1 = operands[1];
198: DONE;
199: }")
200:
201:
202: ;; -------------------------------------------------------------------------
203: ;; Addition instructions
204: ;; -------------------------------------------------------------------------
205:
206: (define_insn "adddi3"
207: [(set (match_operand:DI 0 "arith_reg_operand" "=&r")
208: (plus:DI (match_operand:DI 1 "arith_reg_operand" "%0")
209: (match_operand:DI 2 "arith_reg_operand" "r")))
210: (clobber (reg:SI 18))]
211: ""
212: "clrt\;addc %R2,%R0\;addc %2,%0"
213: [(set_attr "length" "6")
214: (set_attr "in_delay_slot" "no")
215: (set_attr "type" "arith")])
216:
217:
218: (define_insn "addsi3_i"
219: [(set (match_operand:SI 0 "arith_reg_operand" "=r")
220: (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0")
221: (match_operand:SI 2 "arith_operand" "rI")))]
222: ""
223: "add %2,%0"
224: [(set_attr "length" "2")
225: (set_attr "type" "arith")])
226:
227: (define_expand "addsi3"
228: [(set (match_operand:SI 0 "arith_reg_operand" "=r")
229: (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0")
230: (match_operand:SI 2 "arith_operand" "rI")))]
231: ""
232: "")
233:
234:
235: ;; -------------------------------------------------------------------------
236: ;; Subtraction instructions
237: ;; -------------------------------------------------------------------------
238:
239: (define_insn "subdi3"
240: [(set (match_operand:DI 0 "arith_reg_operand" "=&r")
241: (minus:DI (match_operand:DI 1 "arith_reg_operand" "0")
242: (match_operand:DI 2 "arith_reg_operand" "r")))
243: (clobber (reg:SI 18))]
244: ""
245: "clrt\;subc %R2,%R0\;subc %2,%0"
246: [(set_attr "length" "6")
247: (set_attr "in_delay_slot" "no")
248: (set_attr "type" "arith")])
249:
250: (define_insn "subsi3"
251: [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
252: (minus:SI (match_operand:SI 1 "arith_reg_operand" "0,0")
253: (match_operand:SI 2 "arith_operand" "r,I")))]
254: ""
255: "@
256: sub %2,%0
257: add %M2,%0"
258: [(set_attr "type" "arith")])
259:
260:
261: ;; -------------------------------------------------------------------------
262: ;; Multiplication instructions
263: ;; -------------------------------------------------------------------------
264:
265:
266: (define_insn ""
267: [(set (reg:SI 21)
268: (mult:SI (zero_extend:SI
269: (match_operand:HI 1 "arith_reg_operand" "r"))
270: (zero_extend:SI
271: (match_operand:HI 2 "arith_reg_operand" "r"))))]
272: ""
273: "mulu %2,%1"
274: [(set_attr "type" "smpy")])
275:
276: (define_insn ""
277: [(set (reg:SI 21)
278: (mult:SI (sign_extend:SI
279: (match_operand:HI 1 "arith_reg_operand" "r"))
280: (sign_extend:SI
281: (match_operand:HI 2 "arith_reg_operand" "r"))))]
282: ""
283: "muls %2,%1"
284: [(set_attr "type" "smpy")])
285:
286: (define_expand "mulhisi3"
287: [(set (reg:SI 21)
288: (mult:SI (sign_extend:SI
289: (match_operand:HI 1 "arith_reg_operand" "r"))
290: (sign_extend:SI
291: (match_operand:HI 2 "arith_reg_operand" "r"))))
292: (set (match_operand:SI 0 "arith_reg_operand" "=r")
293: (reg:SI 21))]
294: ""
295: "")
296:
297: (define_expand "umulhisi3"
298: [(set (reg:SI 21)
299: (mult:SI (zero_extend:SI
300: (match_operand:HI 1 "arith_reg_operand" "r"))
301: (zero_extend:SI
302: (match_operand:HI 2 "arith_reg_operand" "r"))))
303: (set (match_operand:SI 0 "arith_reg_operand" "=r")
304: (reg:SI 21))]
305: ""
306: "")
307:
308:
309: ;; -------------------------------------------------------------------------
310: ;; Logical operations
311: ;; -------------------------------------------------------------------------
312:
313: (define_insn "andsi3"
314: [(set (match_operand:SI 0 "arith_reg_operand" "=r,z")
315: (and:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
316: (match_operand:SI 2 "logical_operand" "r,L")))]
317: ""
318: "and %2,%0"
319: [(set_attr "type" "arith")])
320:
321: (define_insn "iorsi3"
322: [(set (match_operand:SI 0 "arith_reg_operand" "=r,z")
323: (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
324: (match_operand:SI 2 "logical_operand" "r,L")))]
325: ""
326: "or %2,%0")
327:
328: (define_insn "xorsi3"
329: [(set (match_operand:SI 0 "arith_reg_operand" "=r,z")
330: (xor:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
331: (match_operand:SI 2 "logical_operand" "r,L")))]
332: ""
333: "xor %2,%0"
334: [(set_attr "type" "arith")])
335:
336:
337: ;; -------------------------------------------------------------------------
338: ;; Shifts and rotates
339: ;; -------------------------------------------------------------------------
340:
341: (define_insn "rotlsi3_k"
342: [(set (match_operand:SI 0 "arith_reg_operand" "=r")
343: (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
344: (const_int 1)))
345: (clobber (reg:SI 18))]
346: ""
347: "rotl %0")
348:
349: (define_expand "rotlsi3"
350: [(parallel[(set (match_operand:SI 0 "arith_reg_operand" "")
351: (rotate:SI (match_operand:SI 1 "arith_reg_operand" "")
352: (match_operand:SI 2 "immediate_operand" "")))
353: (clobber (reg:SI 18))])]
354: ""
355: "{ if (GET_CODE(operands[2]) != CONST_INT || INTVAL(operands[2]) != 1) FAIL;}")
356:
357: (define_insn "rotrsi3_k"
358: [(set (match_operand:SI 0 "arith_reg_operand" "=r")
359: (rotatert:SI (match_operand:SI 1 "arith_reg_operand" "0")
360: (const_int 1)))
361: (clobber (reg:SI 18))]
362: ""
363: "rotr %0")
364:
365: (define_expand "rotrsi3"
366: [(parallel[(set (match_operand:SI 0 "arith_reg_operand" "")
367: (rotatert:SI (match_operand:SI 1 "arith_reg_operand" "")
368: (match_operand:SI 2 "immediate_operand" "")))
369: (clobber (reg:SI 18))])]
370: ""
371: "{ if (GET_CODE(operands[2]) != CONST_INT || INTVAL(operands[2]) != 1) FAIL;}")
372:
373: (define_insn "ashlsi3_k"
374: [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
375: (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0")
376: (match_operand:SI 2 "immediate_operand" "K,n")))
377: (clobber (reg:SI 18))]
378: ""
379: "*return output_shift(\"shll\", operands[0], operands[2], ASHIFT);"
380: [(set_attr "length" "2,12")
381: (set_attr "in_delay_slot" "yes,no")
382: (set_attr "type" "arith")])
383:
384: (define_expand "ashlsi3"
385: [(parallel[(set (match_operand:SI 0 "arith_reg_operand" "")
386: (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
387: (match_operand:SI 2 "immediate_operand" "")))
388: (clobber (reg:SI 18))])]
389: ""
390: "if (!ok_shift_value(operands[2], ASHIFT)) FAIL;")
391:
392: (define_insn "ashrsi3_k"
393: [(set (match_operand:SI 0 "arith_reg_operand" "=r")
394: (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
395: (const_int 1)))
396: (clobber (reg:SI 18))]
397: ""
398: "shar %0"
399: [(set_attr "type" "arith")])
400:
401: (define_expand "ashrsi3"
402: [(parallel[(set (match_operand:SI 0 "arith_reg_operand" "=r")
403: (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
404: (match_operand:SI 2 "nonmemory_operand" "M")))
405: (clobber (reg:SI 18))])]
406: ""
407: "
408: {
409: if (GET_CODE (operands[2]) != CONST_INT ||
410: INTVAL (operands[2]) != 1) FAIL;
411: }
412: ")
413:
414: (define_insn "lshrsi3_k"
415: [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
416: (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0,0")
417: (match_operand:SI 2 "immediate_operand" "K,n")))
418: (clobber (reg:SI 18))]
419: ""
420: "* return output_shift (\"shlr\", operands[0], operands[2], LSHIFTRT);"
421: [(set_attr "length" "2,12")
422: (set_attr "in_delay_slot" "yes,no")
423: (set_attr "type" "arith")])
424:
425: (define_expand "lshrsi3"
426: [(parallel[(set (match_operand:SI 0 "arith_reg_operand" "")
427: (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
428: (match_operand:SI 2 "nonmemory_operand" "")))
429: (clobber (reg:SI 18))])]
430: ""
431: "if (!ok_shift_value (operands[2])) FAIL; ")
432:
433: (define_insn "ashldi3_k"
434: [(set (match_operand:DI 0 "arith_reg_operand" "=r")
435: (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
436: (match_operand:DI 2 "immediate_operand" "I")))
437: (clobber (reg:SI 18))]
438: ""
439: "shll %R0\;rotcl %0"
440: [(set_attr "length" "4")])
441:
442: (define_expand "ashldi3"
443: [(parallel[(set (match_operand:DI 0 "arith_reg_operand" "")
444: (ashift:DI (match_operand:DI 1 "arith_reg_operand" "")
445: (match_operand:DI 2 "immediate_operand" "")))
446: (clobber (reg:SI 18))])]
447:
448: ""
449: "{ if (GET_CODE (operands[2]) != CONST_INT
450: || INTVAL (operands[2]) != 1) FAIL;} ")
451:
452: (define_insn "lshrdi3_k"
453: [(set (match_operand:DI 0 "arith_reg_operand" "=r")
454: (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
455: (match_operand:DI 2 "immediate_operand" "I")))
456: (clobber (reg:SI 18))]
457: ""
458: "shlr %0\;rotcr %R0"
459: [(set_attr "length" "4")])
460:
461: (define_expand "lshrdi3"
462: [(parallel[(set (match_operand:DI 0 "arith_reg_operand" "")
463: (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
464: (match_operand:DI 2 "immediate_operand" "")))
465: (clobber (reg:SI 18))])]
466: ""
467: "{ if (GET_CODE (operands[2]) != CONST_INT
468: || INTVAL (operands[2]) != 1) FAIL;} ")
469:
470: (define_insn "ashrdi3_k"
471: [(set (match_operand:DI 0 "arith_reg_operand" "=r")
472: (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
473: (match_operand:DI 2 "immediate_operand" "")))
474: (clobber (reg:SI 18))]
475: ""
476: "shar %0\;rotcr %R0"
477: [(set_attr "length" "4")])
478:
479: (define_expand "ashrdi3"
480: [(parallel[(set (match_operand:DI 0 "arith_reg_operand" "")
481: (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
482: (match_operand:DI 2 "immediate_operand" "")))
483: (clobber (reg:SI 18))])]
484: ""
485: "{ if (GET_CODE (operands[2]) != CONST_INT
486: || INTVAL (operands[2]) != 1) FAIL; } ")
487:
488:
489:
490: ;; -------------------------------------------------------------------------
491: ;; Unary arithmetic
492: ;; -------------------------------------------------------------------------
493:
494: (define_insn "negdi2"
495: [(set (match_operand:DI 0 "arith_reg_operand" "=&r")
496: (neg:DI (match_operand:DI 1 "arith_reg_operand" "0")))
497: (clobber (reg:SI 18))]
498: ""
499: "clrt\;negc %R1,%R0\;negc %1,%0"
500: [(set_attr "length" "6")
501: (set_attr "type" "arith")])
502:
503: (define_insn "negsi2"
504: [(set (match_operand:SI 0 "arith_reg_operand" "=r")
505: (neg:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
506: ""
507: "neg %1,%0"
508: [(set_attr "type" "arith")])
509:
510: (define_insn "one_cmplsi2"
511: [(set (match_operand:SI 0 "arith_reg_operand" "=r")
512: (not:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
513: ""
514: "not %1,%0"
515: [ (set_attr "type" "arith")])
516:
517:
518: ;; -------------------------------------------------------------------------
519: ;; Zero extension instructions
520: ;; -------------------------------------------------------------------------
521:
522: (define_insn "zero_extendhisi2"
523: [(set (match_operand:SI 0 "arith_reg_operand" "=r")
524: (zero_extend:SI (match_operand:HI 1 "arith_reg_operand" "r")))]
525: ""
526: "extu.w %1,%0"
527: [(set_attr "type" "arith")])
528:
529: (define_insn "zero_extendqisi2"
530: [(set (match_operand:SI 0 "arith_reg_operand" "=r")
531: (zero_extend:SI (match_operand:QI 1 "arith_reg_operand" "r")))]
532: ""
533: "extu.b %1,%0"
534: [(set_attr "type" "arith")])
535:
536: (define_insn "zero_extendqihi2"
537: [(set (match_operand:HI 0 "arith_reg_operand" "=r")
538: (zero_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
539: ""
540: "extu.b %1,%0"
541: [(set_attr "type" "arith")])
542:
543:
544: ;; -------------------------------------------------------------------------
545: ;; Sign extension instructions
546: ;; -------------------------------------------------------------------------
547:
548: (define_insn "extendsidi2"
549: [(set (match_operand:DI 0 "arith_reg_operand" "=r")
550: (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "0")))]
551: ""
552: "mov %1,%0\;shll %0\;subc %0,%0"
553: [(set_attr "length" "6")])
554:
555: (define_insn "extendhisi2"
556: [(set (match_operand:SI 0 "arith_reg_operand" "=r")
557: (sign_extend:SI (match_operand:HI 1 "arith_reg_operand" "r")))]
558: ""
559: "exts.w %1,%0")
560:
561: (define_insn "extendqisi2"
562: [(set (match_operand:SI 0 "arith_reg_operand" "=r")
563: (sign_extend:SI (match_operand:QI 1 "arith_reg_operand" "r")))]
564: ""
565: "exts.b %1,%0")
566:
567: (define_insn "extendqihi2"
568: [(set (match_operand:HI 0 "arith_reg_operand" "=r")
569: (sign_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
570: ""
571: "exts.b %1,%0")
572:
573:
574: ;; -------------------------------------------------------------------------
575: ;; Move instructions
576: ;; -------------------------------------------------------------------------
577:
578: (define_insn ""
579: [(set (match_operand:SI 0 "push_operand" "=<,<")
580: (match_operand:SI 1 "arith_reg_operand" "r,l"))]
581: ""
582: "@
583: mov.l %1,%0
584: sts.l pr,%0"
585: [(set_attr "type" "store")])
586:
587: (define_insn ""
588: [(set (match_operand:SI 0 "arith_reg_operand" "=r,l")
589: (match_operand:SI 1 "pop_operand" "=>,>"))]
590: ""
591: "@
592: mov.l %1,%0
593: lds.l %1,pr"
594: [(set_attr "type" "load,pload")])
595:
596: (define_insn "push"
597: [(set (mem:SI (pre_dec:SI (reg:SI 15)))
598: (match_operand:SI 0 "register_operand" "r,l"))]
599: ""
600: "@
601: mov.l %0,@-r15
602: sts.l pr,@-r15")
603:
604: (define_insn "pop"
605: [(set (match_operand:SI 0 "register_operand" "=r,l")
606: (mem:SI (post_inc:SI (reg:SI 15))))]
607: ""
608: "@
609: mov.l @r15+,%0
610: lds.l @r15+,pr"
611: [(set_attr "type" "load,pload")])
612:
613: ; some constants are easier to generate with alu operations
614: ; rather than loading from memory
615:
616: (define_split
617: [(set (match_operand:SI 0 "register_operand" "=r")
618: (match_operand:SI 1 "painful_immediate_operand" "i"))]
619: ""
620: [(set (match_dup 0) (const_int 127))
621: (set (match_dup 0) (plus:SI (match_dup 0)
622: (match_dup 2)))]
623: "operands[2] = GEN_INT (INTVAL(operands[1]) - 127);" )
624:
625: (define_insn "movsi_i"
626: [(set (match_operand:SI 0 "general_operand" "=r,r,r,m,l,r,r,r,t,x")
627: (match_operand:SI 1 "general_movsrc_operand" "r,I,m,r,r,l,t,x,r,r"))]
628: ""
629: "@
630: mov %1,%0
631: mov %1,%0
632: mov.l %1,%0
633: mov.l %1,%0
634: lds %1,%0
635: sts %1,%0
636: movt %0
637: sts %1,%0
638: tst %1,%1\;bt T%*\;bra F%*\;sett\;T%*:clrt\;F%*:%^
639: lds %1,%0"
640: [(set_attr "length" "2,2,2,2,2,2,2,2,10,2")
641: (set_attr "type" "move,move,load,pload,move,move,move,move,move,move")])
642:
643: (define_insn "movsi_pcrel"
644: [(set (match_operand:SI 0 "arith_reg_operand" "=r")
645: (match_operand:SI 1 "hard_immediate_operand" "i"))]
646: ""
647: "* return output_movepcrel (insn, operands, SImode);"
648: [(set_attr "length" "2")
649: (set_attr "in_delay_slot" "no")
650: (set_attr "constneed" "yes")
651: (set_attr "smallestsize" "2")
652: (set_attr "largestsize" "8")
653: (set_attr "type" "load")])
654:
655: (define_expand "movsi"
656: [(set (match_operand:SI 0 "general_operand" "")
657: (match_operand:SI 1 "general_operand" ""))]
658: ""
659: "{ if(prepare_move_operands(operands, SImode)) DONE; } ")
660:
661: (define_insn "movqi_i"
662: [(set (match_operand:QI 0 "general_operand" "=r,r,r,m,r,m,r,r")
663: (match_operand:QI 1 "general_operand" "r,n,m,r,m,r,x,t"))]
664: ""
665: "@
666: mov %1,%0
667: mov %1,%0
668: mov.b %1,%0
669: mov.b %1,%0
670: mov.b %1,%0
671: mov.b %1,%0
672: sts %1,%0
673: movt %0")
674:
675: (define_expand "movqi"
676: [(set (match_operand:QI 0 "general_operand" "")
677: (match_operand:QI 1 "general_operand" ""))]
678: ""
679: "prepare_move_operands(operands, QImode);")
680:
681: (define_insn "movhi_pcrel"
682: [(set (match_operand:HI 0 "arith_reg_operand" "=r")
683: (match_operand:HI 1 "hard_immediate_operand" "i"))]
684: ""
685: "* return output_movepcrel (insn, operands, SImode);"
686: [(set_attr "length" "2")
687: (set_attr "in_delay_slot" "no")
688: (set_attr "constneed" "yes")
689: (set_attr "smallestsize" "2")
690: (set_attr "largestsize" "8")
691: (set_attr "type" "load")])
692:
693: (define_insn "movhi_i"
694: [(set (match_operand:HI 0 "general_operand" "=r,r,m,z,m,r,r")
695: (match_operand:HI 1 "general_operand" "rI,m,r,m,z,x,t"))]
696: ""
697: "@
698: mov %1,%0
699: mov.w %1,%0
700: mov.w %1,%0
701: mov.w %1,%0
702: mov.w %1,%0
703: sts %1,%0
704: movt %0"
705: [(set_attr "type" "move,load,store,load,store,move,move")])
706:
707: (define_expand "movhi"
708: [(set (match_operand:HI 0 "general_operand" "")
709: (match_operand:HI 1 "general_operand" ""))]
710: ""
711: "prepare_move_operands (operands, HImode);")
712:
713: (define_insn ""
714: [(set (match_operand:DI 0 "push_operand" "=<")
715: (match_operand:DI 1 "arith_reg_operand" "r"))]
716: ""
717: "mov.l %R1,%0\;mov.l %1,%0"
718: [(set_attr "length" "4")
719: (set_attr "type" "store")])
720:
721: (define_insn "movdi_pcrel"
722: [(set (match_operand:DI 0 "arith_reg_operand" "=r")
723: (match_operand:DI 1 "hard_immediate_operand" "i"))]
724: ""
725: "* return output_movepcrel (insn, operands, DImode);"
726: [(set_attr "length" "4")
727: (set_attr "in_delay_slot" "no")
728: (set_attr "constneed" "yes")
729: (set_attr "smallestsize" "4")
730: (set_attr "constantsize" "8")
731: (set_attr "largestsize" "18")
732: (set_attr "type" "load")])
733:
734: (define_insn "movdi_k"
735: [(set (match_operand:DI 0 "general_operand" "=r,r,m,r,r,m,r")
736: (match_operand:DI 1 "general_operand" "r,m,r,I,m,r,x"))]
737: ""
738: "* return output_movedouble(operands, DImode);"
739: [(set_attr "length" "4")
740: (set_attr "type" "move,load,store,move,load,store,load")])
741:
742:
743: (define_expand "movdi"
744: [(set (match_operand:DI 0 "general_operand" "")
745: (match_operand:DI 1 "general_operand" ""))]
746: ""
747: "prepare_move_operands (operands, DImode);")
748:
749: (define_insn ""
750: [(set (match_operand:DF 0 "push_operand" "=<")
751: (match_operand:DF 1 "arith_reg_operand" "r"))]
752: ""
753: "mov.l %R1,%0\;mov.l %1,%0"
754: [(set_attr "length" "4")
755: (set_attr "type" "store")])
756:
757: (define_insn "movdf_pcrel"
758: [(set (match_operand:DF 0 "arith_reg_operand" "=r")
759: (match_operand:DF 1 "hard_immediate_operand" "i"))]
760: ""
761: "* return output_movepcrel (insn, operands, DFmode);"
762: [(set_attr "length" "4")
763: (set_attr "in_delay_slot" "no")
764: (set_attr "constneed" "yes")
765: (set_attr "smallestsize" "4")
766: (set_attr "constantsize" "8")
767: (set_attr "largestsize" "18")
768: (set_attr "type" "load")])
769:
770: (define_insn "movdf_k"
771: [(set (match_operand:DF 0 "general_operand" "=r,r,m")
772: (match_operand:DF 1 "general_operand" "r,m,r"))]
773: ""
774: "* return output_movedouble(operands, DFmode);"
775: [(set_attr "length" "4")
776: (set_attr "type" "move,load,store")])
777:
778: (define_expand "movdf"
779: [(set (match_operand:DF 0 "general_operand" "")
780: (match_operand:DF 1 "general_operand" ""))]
781: ""
782: "prepare_move_operands(operands, DFmode);")
783:
784: (define_insn ""
785: [(set (match_operand:SF 0 "push_operand" "=<")
786: (match_operand:SF 1 "arith_reg_operand" "r"))]
787: ""
788: "mov.l %1,%0"
789: [(set_attr "type" "store")])
790:
791: (define_insn "movsf_pcrel"
792: [(set (match_operand:SF 0 "arith_reg_operand" "=r")
793: (match_operand:SF 1 "hard_immediate_operand" "i"))]
794: ""
795: "* return output_movepcrel (insn, operands, SFmode);"
796: [(set_attr "length" "2")
797: (set_attr "in_delay_slot" "no")
798: (set_attr "constneed" "yes")
799: (set_attr "smallestsize" "2")
800: (set_attr "largestsize" "8")
801: (set_attr "type" "load")])
802:
803: (define_insn "movsf_i"
804: [(set (match_operand:SF 0 "general_operand" "=r,r,r,m,l,r,m,r")
805: (match_operand:SF 1 "general_operand" "r,I,m,r,r,l,r,m"))]
806: ""
807: "@
808: mov %1,%0
809: mov %1,%0
810: mov.l %1,%0
811: mov.l %1,%0
812: lds %1,%0
813: sts %1,%0
814: mov %1,%0
815: mov %1,%0"
816: [(set_attr "type" "move,move,load,store,move,move,move,move")])
817:
818: (define_expand "movsf"
819: [(set (match_operand:SF 0 "general_operand" "")
820: (match_operand:SF 1 "general_operand" ""))]
821: ""
822: "prepare_move_operands(operands, SFmode);")
823:
824:
825: ;; ------------------------------------------------------------------------
826: ;; Define the real conditional branch instructions.
827: ;; ------------------------------------------------------------------------
828:
829: (define_insn "branch_true"
830: [(set (pc) (if_then_else (eq (reg:SI 18) (const_int 1))
831: (label_ref (match_operand 0 "" ""))
832: (pc)))]
833: ""
834: "* return output_branch (1, insn);"
835: [(set_attr "type" "cbranch")])
836:
837: (define_insn "branch_false"
838: [(set (pc) (if_then_else (ne (reg:SI 18) (const_int 1))
839: (label_ref (match_operand 0 "" ""))
840: (pc)))]
841: ""
842: "* return output_branch (0, insn);"
843: [(set_attr "type" "cbranch")])
844:
845: (define_insn "inverse_branch_true"
846: [(set (pc) (if_then_else (eq (reg:SI 18) (const_int 1))
847: (pc)
848: (label_ref (match_operand 0 "" ""))))]
849: ""
850: "* return output_branch (0, insn);"
851: [(set_attr "type" "cbranch")])
852:
853: (define_insn "inverse_branch_false"
854: [(set (pc) (if_then_else (ne (reg:SI 18) (const_int 1))
855: (pc)
856: (label_ref (match_operand 0 "" ""))))]
857: ""
858: "* return output_branch (1, insn);"
859: [(set_attr "type" "cbranch")])
860:
861:
862: ;; Conditional branch insns
863:
864: (define_expand "beq"
865: [(set (reg:SI 18) (eq:SI (match_dup 1) (match_dup 2)))
866: (set (pc)
867: (if_then_else (eq (reg:SI 18)
868: (const_int 1))
869: (label_ref (match_operand 0 "" ""))
870: (pc)))]
871: ""
872: "
873: {
874: operands[1] = sh_compare_op0;
875: operands[2] = sh_compare_op1;
876: }")
877:
878:
879: ; There is no bne compare, so we reverse the branch arms.
880:
881: (define_expand "bne"
882: [(set (reg:SI 18) (eq:SI (match_dup 1) (match_dup 2)))
883: (set (pc)
884: (if_then_else (eq (reg:SI 18)
885: (const_int 1))
886: (pc)
887: (label_ref (match_operand 0 "" ""))))]
888: ""
889: "
890: {
891: operands[1] = sh_compare_op0;
892: operands[2] = sh_compare_op1;
893: }")
894:
895: (define_expand "bgt"
896: [(set (reg:SI 18) (gt:SI (match_dup 1) (match_dup 2)))
897: (set (pc)
898: (if_then_else (eq (reg:SI 18)
899: (const_int 1))
900: (label_ref (match_operand 0 "" ""))
901: (pc)))]
902: ""
903: "
904: {
905: operands[1] = sh_compare_op0;
906: operands[2] = sh_compare_op1;
907: }")
908:
909: (define_expand "blt"
910: [(set (reg:SI 18) (lt:SI (match_dup 1) (match_dup 2)))
911: (set (pc)
912: (if_then_else (eq (reg:SI 18)
913: (const_int 1))
914: (label_ref (match_operand 0 "" ""))
915: (pc)))]
916: ""
917: "
918: {
919: operands[1] = sh_compare_op0;
920: operands[2] = sh_compare_op1;
921: }")
922:
923: (define_expand "ble"
924: [(set (reg:SI 18) (le:SI (match_dup 1) (match_dup 2)))
925: (set (pc)
926: (if_then_else (eq (reg:SI 18)
927: (const_int 1))
928: (label_ref (match_operand 0 "" ""))
929: (pc)))]
930: ""
931: "
932: {
933: operands[1] = sh_compare_op0;
934: operands[2] = sh_compare_op1;
935: }")
936:
937: (define_expand "bge"
938: [(set (reg:SI 18) (ge:SI (match_dup 1) (match_dup 2)))
939: (set (pc)
940: (if_then_else (eq (reg:SI 18)
941: (const_int 1))
942: (label_ref (match_operand 0 "" ""))
943: (pc)))]
944: ""
945: "
946: {
947: operands[1] = sh_compare_op0;
948: operands[2] = sh_compare_op1;
949: }")
950:
951: (define_expand "bgtu"
952: [(set (reg:SI 18) (gtu:SI (match_dup 1) (match_dup 2)))
953: (set (pc)
954: (if_then_else (eq (reg:SI 18)
955: (const_int 1))
956: (label_ref (match_operand 0 "" ""))
957: (pc)))]
958: ""
959: "
960: {
961: operands[1] = sh_compare_op0;
962: operands[2] = sh_compare_op1;
963: }")
964:
965: (define_expand "bltu"
966: [(set (reg:SI 18) (ltu:SI (match_dup 1) (match_dup 2)))
967: (set (pc)
968: (if_then_else (eq (reg:SI 18)
969: (const_int 1))
970: (label_ref (match_operand 0 "" ""))
971: (pc)))]
972: ""
973: "
974: {
975: operands[1] = sh_compare_op0;
976: operands[2] = sh_compare_op1;
977: }")
978:
979: (define_expand "bgeu"
980: [(set (reg:SI 18) (geu:SI (match_dup 1) (match_dup 2)))
981: (set (pc)
982: (if_then_else (eq (reg:SI 18)
983: (const_int 1))
984: (label_ref (match_operand 0 "" ""))
985: (pc)))]
986: ""
987: "
988: {
989: operands[1] = sh_compare_op0;
990: operands[2] = sh_compare_op1;
991: }")
992:
993: (define_expand "bleu"
994: [(set (reg:SI 18) (leu:SI (match_dup 1) (match_dup 2)))
995: (set (pc)
996: (if_then_else (eq (reg:SI 18)
997: (const_int 1))
998: (label_ref (match_operand 0 "" ""))
999: (pc)))]
1000: ""
1001: "
1002: {
1003: operands[1] = sh_compare_op0;
1004: operands[2] = sh_compare_op1;
1005: }")
1006:
1007:
1008: ;; ------------------------------------------------------------------------
1009: ;; Jump and linkage insns
1010: ;; ------------------------------------------------------------------------
1011:
1012: (define_insn "jump_real"
1013: [(set (pc)
1014: (label_ref (match_operand 0 "" "")))]
1015: ""
1016: "*
1017: {
1018: if (get_attr_length(insn) == 6)
1019: {
1020: return \"mov.l %I0,r13\;jmp @r13%#\";
1021: }
1022: else
1023: {
1024: return \"bra %l0%#\";
1025: }
1026: }"
1027: [(set_attr "type" "jump")
1028: (set_attr "needs_delay_slot" "yes")])
1029:
1030: (define_expand "jump"
1031: [(set (pc) (label_ref (match_operand 0 "" "")))]
1032: ""
1033: "
1034: {
1035: emit_insn(gen_jump_real(operand0));
1036: DONE;
1037: }
1038: ")
1039:
1040: (define_insn "calli"
1041: [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
1042: (match_operand 1 "" ""))
1043: (clobber (reg:SI 17))]
1044: ""
1045: "jsr @%0%#"
1046: [(set_attr "needs_delay_slot" "yes")
1047: (set_attr "in_delay_slot" "no")
1048: (set_attr "length" "4")])
1049:
1050: (define_insn "call_valuei"
1051: [(set (match_operand 0 "" "=rf")
1052: (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
1053: (match_operand 2 "" "")))
1054: (clobber (reg:SI 17))]
1055: ""
1056: "jsr @%1%#"
1057: [(set_attr "needs_delay_slot" "yes")
1058: (set_attr "in_delay_slot" "no")
1059: (set_attr "length" "4")])
1060:
1061: (define_expand "call"
1062: [(parallel[(call (match_operand 0 "arith_reg_operand" "o")
1063: (match_operand 1 "" ""))
1064: (clobber (reg:SI 17))])]
1065: ""
1066: "
1067: {
1068: if (GET_CODE (operands[0]) == MEM)
1069: {
1070: operands[0]
1071: = gen_rtx(MEM,GET_MODE (operands[0]),
1072: force_reg (Pmode,
1073: XEXP (operands[0], 0)));
1074: }
1075: }")
1076:
1077: (define_expand "call_value"
1078: [(parallel[(set (match_operand 0 "" "=rf")
1079: (call (match_operand 1 "arith_reg_operand" "o")
1080: (match_operand 2 "" "")))
1081: (clobber (reg:SI 17))])]
1082: ""
1083: "
1084: {
1085: if (GET_CODE (operands[1]) == MEM)
1086: {
1087: operands[1]
1088: = gen_rtx (MEM, GET_MODE (operands[1]),
1089: force_reg (Pmode,
1090: XEXP (operands[1], 0)));
1091: }
1092: }")
1093:
1094: (define_insn "indirect_jump"
1095: [(set (pc)
1096: (match_operand:SI 0 "arith_reg_operand" "r"))]
1097: ""
1098: "jmp @%0%#"
1099: [(set_attr "needs_delay_slot" "yes")
1100: (set_attr "in_delay_slot" "no")
1101: (set_attr "length" "4")])
1102:
1103:
1104:
1105: ;; ------------------------------------------------------------------------
1106: ;; Misc insns
1107: ;; ------------------------------------------------------------------------
1108:
1109:
1110: (define_insn "nop"
1111: [(const_int 0)]
1112: ""
1113: "or r0,r0")
1114:
1115: (define_insn "tablejump"
1116: [(set (pc)
1117: (match_operand:SI 0 "arith_reg_operand" "r"))
1118: (use (label_ref (match_operand 1 "" "")))]
1119: ""
1120: "!table jump\;jmp @%0\;or r0,r0\;%!"
1121: [(set_attr "needs_delay_slot" "no")
1122: (set_attr "in_delay_slot" "no")
1123: (set_attr "type" "jump")
1124: (set_attr "dump" "no")])
1125:
1126: (define_insn "return"
1127: [(return)]
1128: "reload_completed"
1129: "rts %#"
1130: [(set_attr "type" "return")
1131: (set_attr "needs_delay_slot" "yes")
1132: (set_attr "dump" "yes")])
1133:
1134: (define_expand "prologue"
1135: [(const_int 0)]
1136: ""
1137: "sh_expand_prologue (); DONE;")
1138:
1139: (define_expand "epilogue"
1140: [(return)]
1141: ""
1142: "sh_expand_epilogue ();")
1143:
1144: (define_insn "blockage"
1145: [(unspec_volatile [(const_int 0)] 0)]
1146: ""
1147: ""
1148: [(set_attr "length" "0")])
1149:
1150:
1151: ;; ------------------------------------------------------------------------
1152: ;; Scc instructions
1153: ;; ------------------------------------------------------------------------
1154:
1155: (define_insn ""
1156: [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1157: (eq (reg:SI 18) (const_int 1)))]
1158: ""
1159: "movt %0 ! ")
1160:
1161: (define_expand "seq"
1162: [(set (match_operand:SI 0 "arith_reg_operand" "")
1163: (match_dup 1))]
1164: ""
1165: "operands[1] = prepare_scc_operands (EQ);")
1166:
1167: (define_expand "slt"
1168: [(set (match_operand:SI 0 "arith_reg_operand" "")
1169: (match_dup 1))]
1170: ""
1171: "operands[1] = prepare_scc_operands (LT);")
1172:
1173: (define_expand "sle"
1174: [(set (match_operand:SI 0 "arith_reg_operand" "")
1175: (match_dup 1))]
1176: ""
1177: "operands[1] = prepare_scc_operands (LE);")
1178:
1179: (define_expand "sgt"
1180: [(set (match_operand:SI 0 "arith_reg_operand" "")
1181: (match_dup 1))]
1182: ""
1183: "operands[1] = prepare_scc_operands (GT);")
1184:
1185: (define_expand "sge"
1186: [(set (match_operand:SI 0 "arith_reg_operand" "")
1187: (match_dup 1))]
1188: ""
1189: "operands[1] = prepare_scc_operands (GE);")
1190:
1191: (define_expand "sgtu"
1192: [(set (match_operand:SI 0 "arith_reg_operand" "")
1193: (match_dup 1))]
1194: ""
1195: "operands[1] = prepare_scc_operands (GTU);")
1196:
1197: (define_expand "sltu"
1198: [(set (match_operand:SI 0 "arith_reg_operand" "")
1199: (match_dup 1))]
1200: ""
1201: "operands[1] = prepare_scc_operands (LTU);")
1202:
1203: (define_expand "sleu"
1204: [(set (match_operand:SI 0 "arith_reg_operand" "")
1205: (match_dup 1))]
1206: ""
1207: "operands[1] = prepare_scc_operands (LEU);")
1208:
1209: (define_expand "sgeu"
1210: [(set (match_operand:SI 0 "arith_reg_operand" "")
1211: (match_dup 1))]
1212: ""
1213: "operands[1] = prepare_scc_operands (GEU);")
1214:
1215: (define_expand "sne"
1216: [(set (match_operand:SI 0 "arith_reg_operand" "")
1217: (match_dup 1))
1218: (set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))]
1219: ""
1220: "operands[1] = prepare_scc_operands (EQ);")
1221:
1222: ; these patterns give better code then gcc invents if
1223: ; left to its own devices
1224:
1225: (define_insn "anddi3"
1226: [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1227: (and:DI (match_operand:DI 1 "arith_reg_operand" "%0")
1228: (match_operand:DI 2 "arith_reg_operand" "r")))]
1229: ""
1230: "and %2,%0\;and %R2,%R0"
1231: [(set_attr "length" "4")])
1232:
1233: (define_insn "iordi3"
1234: [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1235: (ior:DI (match_operand:DI 1 "arith_reg_operand" "%0")
1236: (match_operand:DI 2 "arith_reg_operand" "r")))]
1237: ""
1238: "or %2,%0\;or %R2,%R0"
1239: [(set_attr "length" "4")])
1240:
1241: (define_insn "xordi3"
1242: [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1243: (xor:DI (match_operand:DI 1 "arith_reg_operand" "%0")
1244: (match_operand:DI 2 "arith_reg_operand" "r")))]
1245: ""
1246: "xor %2,%0\;xor %R2,%R0"
1247: [(set_attr "length" "4")])
1248:
1249:
1250: ;; ------------------------------------------------------------------------
1251: ;; Block move
1252: ;; ------------------------------------------------------------------------
1253:
1254: (define_expand "movstrsi"
1255: [(parallel [(set (mem:BLK (match_operand:BLK 0 "general_operand" ""))
1256: (mem:BLK (match_operand:BLK 1 "general_operand" "")))
1257: (use (match_operand:SI 2 "general_operand" ""))
1258: (use (match_operand:SI 3 "immediate_operand" ""))
1259: ])]
1260: ""
1261: "
1262: {
1263: rtx dest_mem = operands[0];
1264: rtx src_mem = operands[1];
1265: operands[0] = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
1266: operands[1] = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
1267: expand_block_move (dest_mem, src_mem, operands);
1268: DONE;
1269: }")
1270:
1271:
1272:
1273:
1274:
1275: ;; -------------------------------------------------------------------------
1276: ;; Peepholes
1277: ;; -------------------------------------------------------------------------
1278:
1279:
1280: (define_peephole
1281: [(set (match_operand:QI 0 "arith_reg_operand" "")
1282: (mem:QI (match_operand:SI 1 "arith_reg_operand" "")))
1283: (set (match_dup 1) (plus:SI (match_dup 1) (const_int 1)))]
1284: "REGNO(operands[1]) != REGNO(operands[0])"
1285: "mov.b @%1+,%0")
1286:
1287: (define_peephole
1288: [(set (match_operand:HI 0 "arith_reg_operand" "")
1289: (mem:HI (match_operand:SI 1 "arith_reg_operand" "")))
1290: (set (match_dup 1) (plus:SI (match_dup 1) (const_int 2)))]
1291: "REGNO(operands[1]) != REGNO(operands[0])"
1292: "mov.w @%1+,%0")
1293:
1294: (define_peephole
1295: [(set (match_operand:SI 0 "arith_reg_operand" "")
1296: (mem:SI (match_operand:SI 1 "arith_reg_operand" "")))
1297: (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
1298: "REGNO(operands[1]) != REGNO(operands[0])"
1299: "mov.l @%1+,%0")
1300:
1301: (define_peephole
1302: [(set (match_operand:QI 0 "register_operand" "=r")
1303: (match_operand:QI 1 "general_operand" "g"))
1304: (set (match_operand:SI 2 "register_operand" "=r")
1305: (sign_extend:SI (match_dup 0)))]
1306: "REGNO(operands[0]) == REGNO(operands[2])"
1307: "mov.b %1,%0")
1308:
1309: (define_peephole
1310: [(set (match_operand:QI 0 "register_operand" "=r")
1311: (match_operand:QI 1 "general_operand" "g"))
1312: (set (match_operand:SI 2 "register_operand" "=r")
1313: (sign_extend:SI (match_dup 0)))]
1314: "REGNO(operands[0]) != REGNO(operands[2])
1315: && dead_or_set_p (insn, operands[0])"
1316: "mov.b %1,%2")
1317:
1318: ; notice when a mov.b could be done with a displacement
1319:
1320: (define_peephole
1321: [(set (match_operand:SI 0 "register_operand" "=r")
1322: (plus:SI (match_dup 0)
1323: (match_operand:SI 1 "byte_index_operand" "i")))
1324: (set (mem:QI (match_dup 0)) (reg:QI 0))]
1325: "dead_or_set_p(insn, operands[0])"
1326: "mov.b r0,@(%O1,%0)")
1327:
1328: (define_peephole
1329: [(set (match_operand:SI 0 "register_operand" "=r")
1330: (plus:SI (match_dup 0)
1331: (match_operand:SI 1 "byte_index_operand" "i")))
1332: (set (reg:QI 0) (mem:QI (match_dup 0)))]
1333: "dead_or_set_p(insn, operands[0])"
1334: "mov.b @(%O1,%0),r0")
1335:
1336:
1337:
1338:
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