![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to sparc.h CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Apple XNU] / GNUtools / cc / config / sparc|
Return to sparc.h CVS log | Up to [Apple XNU] / GNUtools / cc / config / sparc |
1.1 root 1: /* Definitions of target machine for GNU compiler, for Sun SPARC.
2: Copyright (C) 1987, 1988, 1989, 1992 Free Software Foundation, Inc.
3: Contributed by Michael Tiemann ([email protected]).
4:
5: This file is part of GNU CC.
6:
7: GNU CC is free software; you can redistribute it and/or modify
8: it under the terms of the GNU General Public License as published by
9: the Free Software Foundation; either version 2, or (at your option)
10: any later version.
11:
12: GNU CC is distributed in the hope that it will be useful,
13: but WITHOUT ANY WARRANTY; without even the implied warranty of
14: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: GNU General Public License for more details.
16:
17: You should have received a copy of the GNU General Public License
18: along with GNU CC; see the file COPYING. If not, write to
19: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
20:
21: /* Note that some other tm.h files include this one and then override
22: many of the definitions that relate to assembler syntax. */
23:
24: #define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg} \
25: %{a:/usr/lib/bb_link.o}"
26:
27: /* Provide required defaults for linker -e and -d switches. */
28:
29: #define LINK_SPEC \
30: "%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp %{static:-Bstatic} %{assert*}"
31:
32: /* Special flags to the Sun-4 assembler when using pipe for input. */
33:
34: #define ASM_SPEC " %| %{fpic:-k} %{fPIC:-k}"
35:
36: /* Define macros to distinguish architectures. */
37: #define CPP_SPEC "%{msparclite:-D__sparclite__} %{mf930:-D__sparclite__} \
38: %{mf934:-D__sparclite__} %{mv8:-D__sparc_v8__}"
39:
40: /* Prevent error on `-sun4' and `-target sun4' options. */
41: /* This used to translate -dalign to -malign, but that is no good
42: because it can't turn off the usual meaning of making debugging dumps. */
43:
44: #define CC1_SPEC "%{sun4:} %{target:}"
45:
46: #define PTRDIFF_TYPE "int"
47: /* In 2.4 it should work to delete this.
48: #define SIZE_TYPE "int" */
49: #define WCHAR_TYPE "short unsigned int"
50: #define WCHAR_TYPE_SIZE 16
51:
52: /* Omit frame pointer at high optimization levels. */
53:
54: #define OPTIMIZATION_OPTIONS(OPTIMIZE) \
55: { \
56: if (OPTIMIZE >= 2) \
57: { \
58: flag_omit_frame_pointer = 1; \
59: } \
60: }
61:
62: /* To make profiling work with -f{pic,PIC}, we need to emit the profiling
63: code into the rtl. Also, if we are profiling, we cannot eliminate
64: the frame pointer (because the return address will get smashed). */
65:
66: #define OVERRIDE_OPTIONS \
67: { \
68: if (profile_flag || profile_block_flag) \
69: flag_omit_frame_pointer = 0, flag_pic = 0; \
70: SUBTARGET_OVERRIDE_OPTIONS \
71: }
72:
73: /* This is meant to be redefined in the host dependent files */
74: #define SUBTARGET_OVERRIDE_OPTIONS
75:
76: /* These compiler options take an argument. We ignore -target for now. */
77:
78: #define WORD_SWITCH_TAKES_ARG(STR) \
79: (DEFAULT_WORD_SWITCH_TAKES_ARG (STR) \
80: || !strcmp (STR, "target") || !strcmp (STR, "assert"))
81:
82: /* Names to predefine in the preprocessor for this target machine. */
83:
84: /* The GCC_NEW_VARARGS macro is so that old versions of gcc can compile
85: new versions, which have an incompatible va-sparc.h file. This matters
86: because gcc does "gvarargs.h" instead of <varargs.h>, and thus gets the
87: wrong varargs file when it is compiled with a different version of gcc. */
88:
89: #define CPP_PREDEFINES \
90: "-Dsparc -Dsun -Dunix -D__GCC_NEW_VARARGS__ \
91: -Asystem(unix) -Asystem(bsd) -Acpu(sparc) -Amachine(sparc)"
92:
93: /* Print subsidiary information on the compiler version in use. */
94:
95: #define TARGET_VERSION fprintf (stderr, " (sparc)");
96:
97: /* Generate DBX debugging information. */
98:
99: #define DBX_DEBUGGING_INFO
100:
101: /* Run-time compilation parameters selecting different hardware subsets. */
102:
103: extern int target_flags;
104:
105: /* Nonzero if we should generate code to use the fpu. */
106: #define TARGET_FPU (target_flags & 1)
107:
108: /* Nonzero if we should use FUNCTION_EPILOGUE. Otherwise, we
109: use fast return insns, but lose some generality. */
110: #define TARGET_EPILOGUE (target_flags & 2)
111:
112: /* Nonzero if we should assume that double pointers might be unaligned.
113: This can happen when linking gcc compiled code with other compilers,
114: because the ABI only guarantees 4 byte alignment. */
115: #define TARGET_UNALIGNED_DOUBLES (target_flags & 4)
116:
117: /* Nonzero means that we should generate code for a v8 sparc. */
118: #define TARGET_V8 (target_flags & 64)
119:
120: /* Nonzero means that we should generate code for a sparclite.
121: This enables the sparclite specific instructions, but does not affect
122: whether FPU instructions are emitted. */
123: #define TARGET_SPARCLITE (target_flags & 128)
124:
125: /* Nonzero means that we should generate code using a flat register window
126: model, i.e. no save/restore instructions are generated, in the most
127: efficient manner. This code is not compatible with normal sparc code. */
128: /* This is not a user selectable option yet, because it requires changes
129: that are not yet switchable via command line arguments. */
130: #define TARGET_FRW (target_flags & 256)
131:
132: /* Nonzero means that we should generate code using a flat register window
133: model, i.e. no save/restore instructions are generated, but which is
134: compatible with normal sparc code. This is the same as above, except
135: that the frame pointer is %l6 instead of %fp. This code is not as efficient
136: as TARGET_FRW, because it has one less allocatable register. */
137: /* This is not a user selectable option yet, because it requires changes
138: that are not yet switchable via command line arguments. */
139: #define TARGET_FRW_COMPAT (target_flags & 512)
140:
141: /* Macro to define tables used to set the flags.
142: This is a list in braces of pairs in braces,
143: each pair being { "NAME", VALUE }
144: where VALUE is the bits to set or minus the bits to clear.
145: An empty string NAME is used to identify the default VALUE. */
146:
147: /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
148: The Fujitsu MB86934 is the recent sparclite chip, with an fup.
149: We use -mf930 and -mf934 options to choose which.
150: ??? These should perhaps be -mcpu= options. */
151:
152: #define TARGET_SWITCHES \
153: { {"fpu", 1}, \
154: {"no-fpu", -1}, \
155: {"hard-float", 1}, \
156: {"soft-float", -1}, \
157: {"epilogue", 2}, \
158: {"no-epilogue", -2}, \
159: {"unaligned-doubles", 4}, \
160: {"no-unaligned-doubles", -4},\
161: {"v8", 64}, \
162: {"no-v8", -64}, \
163: {"sparclite", 128}, \
164: {"no-sparclite", -128}, \
165: /* {"frw", 256}, */ \
166: /* {"no-frw", -256}, */ \
167: /* {"frw-compat", 256+512}, */ \
168: /* {"no-frw-compat", -(256+512)}, */ \
169: {"f930", 128}, \
170: {"f930", -1}, \
171: {"f934", 128}, \
172: SUBTARGET_SWITCHES \
173: { "", TARGET_DEFAULT}}
174:
175: #define TARGET_DEFAULT 3
176:
177: /* This is meant to be redefined in the host dependent files */
178: #define SUBTARGET_SWITCHES
179:
180: /* target machine storage layout */
181:
182: #if 0
183: /* ??? This does not work in SunOS 4.x, so it is not enabled here.
184: Instead, it is enabled in sol2.h, because it does work under Solaris. */
185: /* Define for support of TFmode long double and REAL_ARITHMETIC.
186: Sparc ABI says that long double is 4 words. */
187: #define LONG_DOUBLE_TYPE_SIZE 128
188: #endif
189:
190: /* Define for cross-compilation to a sparc target with no TFmode from a host
191: with a different float format (e.g. VAX). */
192: #define REAL_ARITHMETIC
193:
194: /* Define this if most significant bit is lowest numbered
195: in instructions that operate on numbered bit-fields. */
196: #define BITS_BIG_ENDIAN 1
197:
198: /* Define this if most significant byte of a word is the lowest numbered. */
199: /* This is true on the SPARC. */
200: #define BYTES_BIG_ENDIAN 1
201:
202: /* Define this if most significant word of a multiword number is the lowest
203: numbered. */
204: /* Doubles are stored in memory with the high order word first. This
205: matters when cross-compiling. */
206: #define WORDS_BIG_ENDIAN 1
207:
208: /* number of bits in an addressable storage unit */
209: #define BITS_PER_UNIT 8
210:
211: /* Width in bits of a "word", which is the contents of a machine register.
212: Note that this is not necessarily the width of data type `int';
213: if using 16-bit ints on a 68000, this would still be 32.
214: But on a machine with 16-bit registers, this would be 16. */
215: #define BITS_PER_WORD 32
216: #define MAX_BITS_PER_WORD 32
217:
218: /* Width of a word, in units (bytes). */
219: #define UNITS_PER_WORD 4
220:
221: /* Width in bits of a pointer.
222: See also the macro `Pmode' defined below. */
223: #define POINTER_SIZE 32
224:
225: /* Allocation boundary (in *bits*) for storing arguments in argument list. */
226: #define PARM_BOUNDARY 32
227:
228: /* Boundary (in *bits*) on which stack pointer should be aligned. */
229: #define STACK_BOUNDARY 64
230:
231: /* ALIGN FRAMES on double word boundaries */
232:
233: #define SPARC_STACK_ALIGN(LOC) (((LOC)+7) & 0xfffffff8)
234:
235: /* Allocation boundary (in *bits*) for the code of a function. */
236: #define FUNCTION_BOUNDARY 32
237:
238: /* Alignment of field after `int : 0' in a structure. */
239: #define EMPTY_FIELD_BOUNDARY 32
240:
241: /* Every structure's size must be a multiple of this. */
242: #define STRUCTURE_SIZE_BOUNDARY 8
243:
244: /* A bitfield declared as `int' forces `int' alignment for the struct. */
245: #define PCC_BITFIELD_TYPE_MATTERS 1
246:
247: /* No data type wants to be aligned rounder than this. */
248: #define BIGGEST_ALIGNMENT 64
249:
250: /* The best alignment to use in cases where we have a choice. */
251: #define FASTEST_ALIGNMENT 64
252:
253: /* Make strings word-aligned so strcpy from constants will be faster. */
254: #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
255: ((TREE_CODE (EXP) == STRING_CST \
256: && (ALIGN) < FASTEST_ALIGNMENT) \
257: ? FASTEST_ALIGNMENT : (ALIGN))
258:
259: /* Make arrays of chars word-aligned for the same reasons. */
260: #define DATA_ALIGNMENT(TYPE, ALIGN) \
261: (TREE_CODE (TYPE) == ARRAY_TYPE \
262: && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
263: && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
264:
265: /* Set this nonzero if move instructions will actually fail to work
266: when given unaligned data. */
267: #define STRICT_ALIGNMENT 1
268:
269: /* Things that must be doubleword aligned cannot go in the text section,
270: because the linker fails to align the text section enough!
271: Put them in the data section. */
272: #define MAX_TEXT_ALIGN 32
273:
274: #define SELECT_SECTION(T,RELOC) \
275: { \
276: if (TREE_CODE (T) == VAR_DECL) \
277: { \
278: if (TREE_READONLY (T) && ! TREE_SIDE_EFFECTS (T) \
279: && DECL_ALIGN (T) <= MAX_TEXT_ALIGN \
280: && ! (flag_pic && (RELOC))) \
281: text_section (); \
282: else \
283: data_section (); \
284: } \
285: else if (TREE_CODE (T) == CONSTRUCTOR) \
286: { \
287: if (flag_pic != 0 && (RELOC) != 0) \
288: data_section (); \
289: } \
290: else if (*tree_code_type[(int) TREE_CODE (T)] == 'c') \
291: { \
292: if ((TREE_CODE (T) == STRING_CST && flag_writable_strings) \
293: || TYPE_ALIGN (TREE_TYPE (T)) > MAX_TEXT_ALIGN) \
294: data_section (); \
295: else \
296: text_section (); \
297: } \
298: }
299:
300: /* Use text section for a constant
301: unless we need more alignment than that offers. */
302: #define SELECT_RTX_SECTION(MODE, X) \
303: { \
304: if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \
305: && ! (flag_pic && symbolic_operand (X))) \
306: text_section (); \
307: else \
308: data_section (); \
309: }
310:
311: /* Standard register usage. */
312:
313: /* Number of actual hardware registers.
314: The hardware registers are assigned numbers for the compiler
315: from 0 to just below FIRST_PSEUDO_REGISTER.
316: All registers that the compiler knows about must be given numbers,
317: even those that are not normally considered general registers.
318:
319: SPARC has 32 integer registers and 32 floating point registers. */
320:
321: #define FIRST_PSEUDO_REGISTER 64
322:
323: /* 1 for registers that have pervasive standard uses
324: and are not available for the register allocator.
325: g0 is used for the condition code and not to represent %g0, which is
326: hardwired to 0, so reg 0 is *not* fixed.
327: g1 through g4 are free to use as temporaries.
328: g5 through g7 are reserved for the operating system. */
329: #define FIXED_REGISTERS \
330: {0, 0, 0, 0, 0, 1, 1, 1, \
331: 0, 0, 0, 0, 0, 0, 1, 0, \
332: 0, 0, 0, 0, 0, 0, 0, 0, \
333: 0, 0, 0, 0, 0, 0, 1, 1, \
334: \
335: 0, 0, 0, 0, 0, 0, 0, 0, \
336: 0, 0, 0, 0, 0, 0, 0, 0, \
337: 0, 0, 0, 0, 0, 0, 0, 0, \
338: 0, 0, 0, 0, 0, 0, 0, 0}
339:
340: /* 1 for registers not available across function calls.
341: These must include the FIXED_REGISTERS and also any
342: registers that can be used without being saved.
343: The latter must include the registers where values are returned
344: and the register where structure-value addresses are passed.
345: Aside from that, you can include as many other registers as you like. */
346: #define CALL_USED_REGISTERS \
347: {1, 1, 1, 1, 1, 1, 1, 1, \
348: 1, 1, 1, 1, 1, 1, 1, 1, \
349: 0, 0, 0, 0, 0, 0, 0, 0, \
350: 0, 0, 0, 0, 0, 0, 1, 1, \
351: \
352: 1, 1, 1, 1, 1, 1, 1, 1, \
353: 1, 1, 1, 1, 1, 1, 1, 1, \
354: 1, 1, 1, 1, 1, 1, 1, 1, \
355: 1, 1, 1, 1, 1, 1, 1, 1}
356:
357: /* If !TARGET_FPU, then make the fp registers fixed so that they won't
358: be allocated. */
359:
360: #define CONDITIONAL_REGISTER_USAGE \
361: do \
362: { \
363: if (! TARGET_FPU) \
364: { \
365: int regno; \
366: for (regno = 32; regno < 64; regno++) \
367: fixed_regs[regno] = 1; \
368: } \
369: } \
370: while (0)
371:
372: /* Return number of consecutive hard regs needed starting at reg REGNO
373: to hold something of mode MODE.
374: This is ordinarily the length in words of a value of mode MODE
375: but can be less for certain modes in special long registers.
376:
377: On SPARC, ordinary registers hold 32 bits worth;
378: this means both integer and floating point registers.
379:
380: We use vectors to keep this information about registers. */
381:
382: /* How many hard registers it takes to make a register of this mode. */
383: extern int hard_regno_nregs[];
384:
385: #define HARD_REGNO_NREGS(REGNO, MODE) \
386: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
387:
388: /* Value is 1 if register/mode pair is acceptable on sparc. */
389: extern int hard_regno_mode_ok[FIRST_PSEUDO_REGISTER];
390:
391: /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
392: On SPARC, the cpu registers can hold any mode but the float registers
393: can only hold SFmode or DFmode. See sparc.c for how we
394: initialize this. */
395: #define HARD_REGNO_MODE_OK(REGNO, MODE) \
396: ((hard_regno_mode_ok[REGNO] & (1<<(int)(MODE))) != 0)
397:
398: /* Value is 1 if it is a good idea to tie two pseudo registers
399: when one has mode MODE1 and one has mode MODE2.
400: If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
401: for any hard reg, then this must be 0 for correct output. */
402: #define MODES_TIEABLE_P(MODE1, MODE2) \
403: ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
404:
405: /* Specify the registers used for certain standard purposes.
406: The values of these macros are register numbers. */
407:
408: /* SPARC pc isn't overloaded on a register that the compiler knows about. */
409: /* #define PC_REGNUM */
410:
411: /* Register to use for pushing function arguments. */
412: #define STACK_POINTER_REGNUM 14
413:
414: /* Actual top-of-stack address is 92 greater than the contents
415: of the stack pointer register. 92 = 68 + 24. 64 bytes reserving space
416: for the ins and local registers, 4 byte for structure return address, and
417: 24 bytes for the 6 register parameters. */
418: #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(0)
419:
420: /* Base register for access to local variables of the function. */
421: #define FRAME_POINTER_REGNUM 30
422:
423: #if 0
424: /* Register that is used for the return address. */
425: #define RETURN_ADDR_REGNUM 15
426: #endif
427:
428: /* Value should be nonzero if functions must have frame pointers.
429: Zero means the frame pointer need not be set up (and parms
430: may be accessed via the stack pointer) in functions that seem suitable.
431: This is computed in `reload', in reload1.c.
432:
433: Used in flow.c, global.c, and reload1.c. */
434: extern int leaf_function;
435:
436: #define FRAME_POINTER_REQUIRED \
437: (! (leaf_function_p () && only_leaf_regs_used ()))
438:
439: /* C statement to store the difference between the frame pointer
440: and the stack pointer values immediately after the function prologue.
441:
442: Note, we always pretend that this is a leaf function because if
443: it's not, there's no point in trying to eliminate the
444: frame pointer. If it is a leaf function, we guessed right! */
445: #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
446: ((VAR) = (TARGET_FRW ? sparc_frw_compute_frame_size (get_frame_size ()) \
447: : compute_frame_size (get_frame_size (), 1)))
448:
449: /* Base register for access to arguments of the function. */
450: #define ARG_POINTER_REGNUM 30
451:
452: /* Register in which static-chain is passed to a function. This must
453: not be a register used by the prologue. */
454: #define STATIC_CHAIN_REGNUM 2
455:
456: /* Register which holds offset table for position-independent
457: data references. */
458:
459: #define PIC_OFFSET_TABLE_REGNUM 23
460:
461: #define INITIALIZE_PIC initialize_pic ()
462: #define FINALIZE_PIC finalize_pic ()
463:
464: /* Sparc ABI says that quad-precision floats and all structures are returned
465: in memory. */
466: #define RETURN_IN_MEMORY(TYPE) \
467: (TYPE_MODE (TYPE) == BLKmode || TYPE_MODE (TYPE) == TFmode)
468:
469: /* Functions which return large structures get the address
470: to place the wanted value at offset 64 from the frame.
471: Must reserve 64 bytes for the in and local registers. */
472: /* Used only in other #defines in this file. */
473: #define STRUCT_VALUE_OFFSET 64
474:
475: #define STRUCT_VALUE \
476: gen_rtx (MEM, Pmode, \
477: gen_rtx (PLUS, Pmode, stack_pointer_rtx, \
478: gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET)))
479: #define STRUCT_VALUE_INCOMING \
480: gen_rtx (MEM, Pmode, \
481: gen_rtx (PLUS, Pmode, frame_pointer_rtx, \
482: gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET)))
483:
484: /* Define the classes of registers for register constraints in the
485: machine description. Also define ranges of constants.
486:
487: One of the classes must always be named ALL_REGS and include all hard regs.
488: If there is more than one class, another class must be named NO_REGS
489: and contain no registers.
490:
491: The name GENERAL_REGS must be the name of a class (or an alias for
492: another name such as ALL_REGS). This is the class of registers
493: that is allowed by "g" or "r" in a register constraint.
494: Also, registers outside this class are allocated only when
495: instructions express preferences for them.
496:
497: The classes must be numbered in nondecreasing order; that is,
498: a larger-numbered class must never be contained completely
499: in a smaller-numbered class.
500:
501: For any two classes, it is very desirable that there be another
502: class that represents their union. */
503:
504: /* The SPARC has two kinds of registers, general and floating point. */
505:
506: enum reg_class { NO_REGS, GENERAL_REGS, FP_REGS, ALL_REGS, LIM_REG_CLASSES };
507:
508: #define N_REG_CLASSES (int) LIM_REG_CLASSES
509:
510: /* Give names of register classes as strings for dump file. */
511:
512: #define REG_CLASS_NAMES \
513: {"NO_REGS", "GENERAL_REGS", "FP_REGS", "ALL_REGS" }
514:
515: /* Define which registers fit in which classes.
516: This is an initializer for a vector of HARD_REG_SET
517: of length N_REG_CLASSES. */
518:
519: #if 0 && defined (__GNUC__)
520: #define REG_CLASS_CONTENTS {0LL, 0xfffffffeLL, 0xffffffff00000000LL, 0xfffffffffffffffeLL}
521: #else
522: #define REG_CLASS_CONTENTS {{0, 0}, {-2, 0}, {0, -1}, {-2, -1}}
523: #endif
524:
525: /* The same information, inverted:
526: Return the class number of the smallest class containing
527: reg number REGNO. This could be a conditional expression
528: or could index an array. */
529:
530: #define REGNO_REG_CLASS(REGNO) \
531: ((REGNO) >= 32 ? FP_REGS : (REGNO) == 0 ? NO_REGS : GENERAL_REGS)
532:
533: /* This is the order in which to allocate registers
534: normally.
535:
536: We put %f0/%f1 last among the float registers, so as to make it more
537: likely that a pseudo-register which dies in the float return register
538: will get allocated to the float return register, thus saving a move
539: instruction at the end of the function. */
540: #define REG_ALLOC_ORDER \
541: { 8, 9, 10, 11, 12, 13, 2, 3, \
542: 15, 16, 17, 18, 19, 20, 21, 22, \
543: 23, 24, 25, 26, 27, 28, 29, 31, \
544: 34, 35, 36, 37, 38, 39, \
545: 40, 41, 42, 43, 44, 45, 46, 47, \
546: 48, 49, 50, 51, 52, 53, 54, 55, \
547: 56, 57, 58, 59, 60, 61, 62, 63, \
548: 32, 33, \
549: 1, 4, 5, 6, 7, 0, 14, 30}
550:
551: /* This is the order in which to allocate registers for
552: leaf functions. If all registers can fit in the "i" registers,
553: then we have the possibility of having a leaf function. */
554: #define REG_LEAF_ALLOC_ORDER \
555: { 2, 3, 24, 25, 26, 27, 28, 29, \
556: 15, 8, 9, 10, 11, 12, 13, \
557: 16, 17, 18, 19, 20, 21, 22, 23, \
558: 34, 35, 36, 37, 38, 39, \
559: 40, 41, 42, 43, 44, 45, 46, 47, \
560: 48, 49, 50, 51, 52, 53, 54, 55, \
561: 56, 57, 58, 59, 60, 61, 62, 63, \
562: 32, 33, \
563: 1, 4, 5, 6, 7, 0, 14, 30, 31}
564:
565: #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
566:
567: #define LEAF_REGISTERS \
568: { 1, 1, 1, 1, 1, 1, 1, 1, \
569: 0, 0, 0, 0, 0, 0, 1, 0, \
570: 0, 0, 0, 0, 0, 0, 0, 0, \
571: 1, 1, 1, 1, 1, 1, 0, 1, \
572: 1, 1, 1, 1, 1, 1, 1, 1, \
573: 1, 1, 1, 1, 1, 1, 1, 1, \
574: 1, 1, 1, 1, 1, 1, 1, 1, \
575: 1, 1, 1, 1, 1, 1, 1, 1}
576:
577: extern char leaf_reg_remap[];
578: #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
579: extern char leaf_reg_backmap[];
580: #define LEAF_REG_BACKMAP(REGNO) (leaf_reg_backmap[REGNO])
581:
582: /* The class value for index registers, and the one for base regs. */
583: #define INDEX_REG_CLASS GENERAL_REGS
584: #define BASE_REG_CLASS GENERAL_REGS
585:
586: /* Get reg_class from a letter such as appears in the machine description. */
587:
588: #define REG_CLASS_FROM_LETTER(C) \
589: ((C) == 'f' ? FP_REGS : (C) == 'r' ? GENERAL_REGS : NO_REGS)
590:
591: /* The letters I, J, K, L and M in a register constraint string
592: can be used to stand for particular ranges of immediate operands.
593: This macro defines what the ranges are.
594: C is the letter, and VALUE is a constant value.
595: Return 1 if VALUE is in the range specified by C.
596:
597: For SPARC, `I' is used for the range of constants an insn
598: can actually contain.
599: `J' is used for the range which is just zero (since that is R0).
600: `K' is used for constants which can be loaded with a single sethi insn. */
601:
602: #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x1000) < 0x2000)
603:
604: #define CONST_OK_FOR_LETTER_P(VALUE, C) \
605: ((C) == 'I' ? (unsigned) ((VALUE) + 0x1000) < 0x2000 \
606: : (C) == 'J' ? (VALUE) == 0 \
607: : (C) == 'K' ? ((VALUE) & 0x3ff) == 0 \
608: : 0)
609:
610: /* Similar, but for floating constants, and defining letters G and H.
611: Here VALUE is the CONST_DOUBLE rtx itself. */
612:
613: #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
614: ((C) == 'G' ? fp_zero_operand (VALUE) \
615: : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
616: : 0)
617:
618: /* Given an rtx X being reloaded into a reg required to be
619: in class CLASS, return the class of reg to actually use.
620: In general this is just CLASS; but on some machines
621: in some cases it is preferable to use a more restrictive class. */
622: /* We can't load constants into FP registers. We can't load any FP constant
623: if an 'E' constraint fails to match it. */
624: #define PREFERRED_RELOAD_CLASS(X,CLASS) \
625: (CONSTANT_P (X) \
626: && ((CLASS) == FP_REGS \
627: || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
628: && (HOST_FLOAT_FORMAT != IEEE_FLOAT_FORMAT \
629: || HOST_BITS_PER_INT != BITS_PER_WORD))) \
630: ? NO_REGS : (CLASS))
631:
632: /* Return the register class of a scratch register needed to load IN into
633: a register of class CLASS in MODE.
634:
635: On the SPARC, when PIC, we need a temporary when loading some addresses
636: into a register.
637:
638: Also, we need a temporary when loading/storing a HImode/QImode value
639: between memory and the FPU registers. This can happen when combine puts
640: a paradoxical subreg in a float/fix conversion insn. */
641:
642: #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
643: (((CLASS) == FP_REGS && ((MODE) == HImode || (MODE) == QImode)\
644: && (GET_CODE (IN) == MEM \
645: || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
646: && true_regnum (IN) == -1))) ? GENERAL_REGS : NO_REGS)
647:
648: #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \
649: ((CLASS) == FP_REGS && ((MODE) == HImode || (MODE) == QImode) \
650: && (GET_CODE (IN) == MEM \
651: || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
652: && true_regnum (IN) == -1)) ? GENERAL_REGS : NO_REGS)
653:
654: /* On SPARC it is not possible to directly move data between
655: GENERAL_REGS and FP_REGS. */
656: #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
657: (((CLASS1) == FP_REGS && (CLASS2) == GENERAL_REGS) \
658: || ((CLASS1) == GENERAL_REGS && (CLASS2) == FP_REGS))
659:
660: /* Return the stack location to use for secondary memory needed reloads. */
661: #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
662: gen_rtx (MEM, MODE, gen_rtx (PLUS, Pmode, frame_pointer_rtx, \
663: GEN_INT (STARTING_FRAME_OFFSET)))
664:
665: /* Return the maximum number of consecutive registers
666: needed to represent mode MODE in a register of class CLASS. */
667: /* On SPARC, this is the size of MODE in words. */
668: #define CLASS_MAX_NREGS(CLASS, MODE) \
669: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
670:
671: /* Stack layout; function entry, exit and calling. */
672:
673: /* Define the number of register that can hold parameters.
674: These two macros are used only in other macro definitions below. */
675: #define NPARM_REGS 6
676:
677: /* Define this if pushing a word on the stack
678: makes the stack pointer a smaller address. */
679: #define STACK_GROWS_DOWNWARD
680:
681: /* Define this if the nominal address of the stack frame
682: is at the high-address end of the local variables;
683: that is, each additional local variable allocated
684: goes at a more negative offset in the frame. */
685: #define FRAME_GROWS_DOWNWARD
686:
687: /* Offset within stack frame to start allocating local variables at.
688: If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
689: first local allocated. Otherwise, it is the offset to the BEGINNING
690: of the first local allocated. */
691: /* This is 16 to allow space for one TFmode floating point value. */
692: #define STARTING_FRAME_OFFSET (-16)
693:
694: /* If we generate an insn to push BYTES bytes,
695: this says how many the stack pointer really advances by.
696: On SPARC, don't define this because there are no push insns. */
697: /* #define PUSH_ROUNDING(BYTES) */
698:
699: /* Offset of first parameter from the argument pointer register value.
700: This is 64 for the ins and locals, plus 4 for the struct-return reg
701: even if this function isn't going to use it. */
702: #define FIRST_PARM_OFFSET(FNDECL) (STRUCT_VALUE_OFFSET + UNITS_PER_WORD)
703:
704: /* When a parameter is passed in a register, stack space is still
705: allocated for it. */
706: #define REG_PARM_STACK_SPACE(DECL) (NPARM_REGS * UNITS_PER_WORD)
707:
708: /* Keep the stack pointer constant throughout the function.
709: This is both an optimization and a necessity: longjmp
710: doesn't behave itself when the stack pointer moves within
711: the function! */
712: #define ACCUMULATE_OUTGOING_ARGS
713:
714: /* Value is the number of bytes of arguments automatically
715: popped when returning from a subroutine call.
716: FUNTYPE is the data type of the function (as a tree),
717: or for a library call it is an identifier node for the subroutine name.
718: SIZE is the number of bytes of arguments passed on the stack. */
719:
720: #define RETURN_POPS_ARGS(FUNTYPE,SIZE) 0
721:
722: /* Some subroutine macros specific to this machine.
723: When !TARGET_FPU, put float return values in the general registers,
724: since we don't have any fp registers. */
725: #define BASE_RETURN_VALUE_REG(MODE) \
726: (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 : 8)
727: #define BASE_OUTGOING_VALUE_REG(MODE) \
728: (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 \
729: : (TARGET_FRW ? 8 : 24))
730: #define BASE_PASSING_ARG_REG(MODE) (8)
731: #define BASE_INCOMING_ARG_REG(MODE) (TARGET_FRW ? 8 : 24)
732:
733: /* Define this macro if the target machine has "register windows". This
734: C expression returns the register number as seen by the called function
735: corresponding to register number OUT as seen by the calling function.
736: Return OUT if register number OUT is not an outbound register. */
737:
738: #define INCOMING_REGNO(OUT) \
739: ((TARGET_FRW || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16)
740:
741: /* Define this macro if the target machine has "register windows". This
742: C expression returns the register number as seen by the calling function
743: corresponding to register number IN as seen by the called function.
744: Return IN if register number IN is not an inbound register. */
745:
746: #define OUTGOING_REGNO(IN) \
747: ((TARGET_FRW || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16)
748:
749: /* Define how to find the value returned by a function.
750: VALTYPE is the data type of the value (as a tree).
751: If the precise function being called is known, FUNC is its FUNCTION_DECL;
752: otherwise, FUNC is 0. */
753:
754: /* On SPARC the value is found in the first "output" register. */
755:
756: #define FUNCTION_VALUE(VALTYPE, FUNC) \
757: gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
758:
759: /* But the called function leaves it in the first "input" register. */
760:
761: #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
762: gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_OUTGOING_VALUE_REG (TYPE_MODE (VALTYPE)))
763:
764: /* Define how to find the value returned by a library function
765: assuming the value has mode MODE. */
766:
767: #define LIBCALL_VALUE(MODE) \
768: gen_rtx (REG, MODE, BASE_RETURN_VALUE_REG (MODE))
769:
770: /* 1 if N is a possible register number for a function value
771: as seen by the caller.
772: On SPARC, the first "output" reg is used for integer values,
773: and the first floating point register is used for floating point values. */
774:
775: #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
776:
777: /* Define the size of space to allocate for the return value of an
778: untyped_call. */
779:
780: #define APPLY_RESULT_SIZE 16
781:
782: /* 1 if N is a possible register number for function argument passing.
783: On SPARC, these are the "output" registers. */
784:
785: #define FUNCTION_ARG_REGNO_P(N) ((N) < 14 && (N) > 7)
786:
787: /* Define a data type for recording info about an argument list
788: during the scan of that argument list. This data type should
789: hold all necessary information about the function itself
790: and about the args processed so far, enough to enable macros
791: such as FUNCTION_ARG to determine where the next arg should go.
792:
793: On SPARC, this is a single integer, which is a number of words
794: of arguments scanned so far (including the invisible argument,
795: if any, which holds the structure-value-address).
796: Thus 7 or more means all following args should go on the stack. */
797:
798: #define CUMULATIVE_ARGS int
799:
800: #define ROUND_ADVANCE(SIZE) \
801: ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
802:
803: /* Initialize a variable CUM of type CUMULATIVE_ARGS
804: for a call to a function whose data type is FNTYPE.
805: For a library call, FNTYPE is 0.
806:
807: On SPARC, the offset always starts at 0: the first parm reg is always
808: the same reg. */
809:
810: #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) ((CUM) = 0)
811:
812: /* Update the data in CUM to advance over an argument
813: of mode MODE and data type TYPE.
814: (TYPE is null for libcalls where that information may not be available.) */
815:
816: #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
817: ((CUM) += ((MODE) != BLKmode \
818: ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
819: : ROUND_ADVANCE (int_size_in_bytes (TYPE))))
820:
821: /* Determine where to put an argument to a function.
822: Value is zero to push the argument on the stack,
823: or a hard register in which to store the argument.
824:
825: MODE is the argument's machine mode.
826: TYPE is the data type of the argument (as a tree).
827: This is null for libcalls where that information may
828: not be available.
829: CUM is a variable of type CUMULATIVE_ARGS which gives info about
830: the preceding args and about the function being called.
831: NAMED is nonzero if this argument is a named parameter
832: (otherwise it is an extra parameter matching an ellipsis). */
833:
834: /* On SPARC the first six args are normally in registers
835: and the rest are pushed. Any arg that starts within the first 6 words
836: is at least partially passed in a register unless its data type forbids. */
837:
838: #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
839: ((CUM) < NPARM_REGS \
840: && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
841: && ((TYPE)==0 || (MODE) != BLKmode \
842: || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
843: ? gen_rtx (REG, (MODE), (BASE_PASSING_ARG_REG (MODE) + (CUM))) \
844: : 0)
845:
846: /* Define where a function finds its arguments.
847: This is different from FUNCTION_ARG because of register windows. */
848:
849: #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
850: ((CUM) < NPARM_REGS \
851: && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
852: && ((TYPE)==0 || (MODE) != BLKmode \
853: || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
854: ? gen_rtx (REG, (MODE), (BASE_INCOMING_ARG_REG (MODE) + (CUM))) \
855: : 0)
856:
857: /* For an arg passed partly in registers and partly in memory,
858: this is the number of registers used.
859: For args passed entirely in registers or entirely in memory, zero.
860: Any arg that starts in the first 6 regs but won't entirely fit in them
861: needs partial registers on the Sparc. */
862:
863: #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
864: ((CUM) < NPARM_REGS \
865: && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
866: && ((TYPE)==0 || (MODE) != BLKmode \
867: || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
868: && ((CUM) + ((MODE) == BLKmode \
869: ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \
870: : ROUND_ADVANCE (GET_MODE_SIZE (MODE))) - NPARM_REGS > 0)\
871: ? (NPARM_REGS - (CUM)) \
872: : 0)
873:
874: /* The SPARC ABI stipulates passing struct arguments (of any size) and
875: quad-precision floats by invisible reference. */
876: #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
877: ((TYPE && (TREE_CODE (TYPE) == RECORD_TYPE \
878: || TREE_CODE (TYPE) == UNION_TYPE)) \
879: || (MODE == TFmode))
880:
881: /* Define the information needed to generate branch and scc insns. This is
882: stored from the compare operation. Note that we can't use "rtx" here
883: since it hasn't been defined! */
884:
885: extern struct rtx_def *sparc_compare_op0, *sparc_compare_op1;
886:
887: /* Define the function that build the compare insn for scc and bcc. */
888:
889: extern struct rtx_def *gen_compare_reg ();
890:
891: /* Generate the special assembly code needed to tell the assembler whatever
892: it might need to know about the return value of a function.
893:
894: For Sparc assemblers, we need to output a .proc pseudo-op which conveys
895: information to the assembler relating to peephole optimization (done in
896: the assembler). */
897:
898: #define ASM_DECLARE_RESULT(FILE, RESULT) \
899: fprintf ((FILE), "\t.proc\t0%o\n", sparc_type_code (TREE_TYPE (RESULT)))
900:
901: /* Output the label for a function definition. */
902:
903: #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
904: do { \
905: ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \
906: ASM_OUTPUT_LABEL (FILE, NAME); \
907: } while (0)
908:
909: /* This macro generates the assembly code for function entry.
910: FILE is a stdio stream to output the code to.
911: SIZE is an int: how many units of temporary storage to allocate.
912: Refer to the array `regs_ever_live' to determine which registers
913: to save; `regs_ever_live[I]' is nonzero if register number I
914: is ever used in the function. This macro is responsible for
915: knowing which registers should not be saved even if used. */
916:
917: /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
918: of memory. If any fpu reg is used in the function, we allocate
919: such a block here, at the bottom of the frame, just in case it's needed.
920:
921: If this function is a leaf procedure, then we may choose not
922: to do a "save" insn. The decision about whether or not
923: to do this is made in regclass.c. */
924:
925: #define FUNCTION_PROLOGUE(FILE, SIZE) \
926: (TARGET_FRW ? sparc_frw_output_function_prologue (FILE, SIZE, leaf_function)\
927: : output_function_prologue (FILE, SIZE, leaf_function))
928:
929: /* Output assembler code to FILE to increment profiler label # LABELNO
930: for profiling a function entry. */
931:
932: #define FUNCTION_PROFILER(FILE, LABELNO) \
933: do { \
934: fputs ("\tsethi %hi(", (FILE)); \
935: ASM_OUTPUT_INTERNAL_LABELREF (FILE, "LP", LABELNO); \
936: fputs ("),%o0\n\tcall mcount\n\tor %lo(", (FILE)); \
937: ASM_OUTPUT_INTERNAL_LABELREF (FILE, "LP", LABELNO); \
938: fputs ("),%o0,%o0\n", (FILE)); \
939: } while (0)
940:
941: /* Output assembler code to FILE to initialize this source file's
942: basic block profiling info, if that has not already been done. */
943: /* FIXME -- this does not parameterize how it generates labels (like the
944: above FUNCTION_PROFILER). Broken on Solaris-2. [email protected] */
945:
946: #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
947: fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tld [%%lo(LPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(LPBX0),%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n", \
948: (LABELNO), (LABELNO))
949:
950: /* Output assembler code to FILE to increment the entry-count for
951: the BLOCKNO'th basic block in this source file. */
952:
953: #define BLOCK_PROFILER(FILE, BLOCKNO) \
954: { \
955: int blockn = (BLOCKNO); \
956: fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tld [%%lo(LPBX2+%d)+%%g1],%%g2\n\
957: \tadd %%g2,1,%%g2\n\tst %%g2,[%%lo(LPBX2+%d)+%%g1]\n", \
958: 4 * blockn, 4 * blockn, 4 * blockn); \
959: }
960:
961: /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
962: the stack pointer does not matter. The value is tested only in
963: functions that have frame pointers.
964: No definition is equivalent to always zero. */
965:
966: extern int current_function_calls_alloca;
967: extern int current_function_outgoing_args_size;
968:
969: #define EXIT_IGNORE_STACK \
970: (get_frame_size () != 0 \
971: || current_function_calls_alloca || current_function_outgoing_args_size)
972:
973: /* This macro generates the assembly code for function exit,
974: on machines that need it. If FUNCTION_EPILOGUE is not defined
975: then individual return instructions are generated for each
976: return statement. Args are same as for FUNCTION_PROLOGUE.
977:
978: The function epilogue should not depend on the current stack pointer!
979: It should use the frame pointer only. This is mandatory because
980: of alloca; we also take advantage of it to omit stack adjustments
981: before returning. */
982:
983: /* This declaration is needed due to traditional/ANSI
984: incompatibilities which cannot be #ifdefed away
985: because they occur inside of macros. Sigh. */
986: extern union tree_node *current_function_decl;
987:
988: #define FUNCTION_EPILOGUE(FILE, SIZE) \
989: (TARGET_FRW ? sparc_frw_output_function_epilogue (FILE, SIZE, leaf_function)\
990: : output_function_epilogue (FILE, SIZE, leaf_function))
991:
992: #define DELAY_SLOTS_FOR_EPILOGUE \
993: (TARGET_FRW ? sparc_frw_epilogue_delay_slots () : 1)
994: #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \
995: (TARGET_FRW ? sparc_frw_eligible_for_epilogue_delay (trial, slots_filled) \
996: : eligible_for_epilogue_delay (trial, slots_filled))
997:
998: /* Output assembler code for a block containing the constant parts
999: of a trampoline, leaving space for the variable parts. */
1000:
1001: /* On the sparc, the trampoline contains five instructions:
1002: sethi #TOP_OF_FUNCTION,%g1
1003: or #BOTTOM_OF_FUNCTION,%g1,%g1
1004: sethi #TOP_OF_STATIC,%g2
1005: jmp g1
1006: or #BOTTOM_OF_STATIC,%g2,%g2 */
1007: #define TRAMPOLINE_TEMPLATE(FILE) \
1008: { \
1009: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
1010: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
1011: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
1012: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x81C04000)); \
1013: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
1014: }
1015:
1016: /* Length in units of the trampoline for entering a nested function. */
1017:
1018: #define TRAMPOLINE_SIZE 20
1019:
1020: /* Emit RTL insns to initialize the variable parts of a trampoline.
1021: FNADDR is an RTX for the address of the function's pure code.
1022: CXT is an RTX for the static chain value for the function.
1023:
1024: This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
1025: (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
1026: (to store insns). This is a bit excessive. Perhaps a different
1027: mechanism would be better here.
1028:
1029: Emit 3 FLUSH instructions (UNSPEC_VOLATILE 2) to synchonize the data
1030: and instruction caches. */
1031:
1032: #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1033: { \
1034: rtx high_cxt = expand_shift (RSHIFT_EXPR, SImode, CXT, \
1035: size_int (10), 0, 1); \
1036: rtx high_fn = expand_shift (RSHIFT_EXPR, SImode, FNADDR, \
1037: size_int (10), 0, 1); \
1038: rtx low_cxt = expand_and (CXT, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); \
1039: rtx low_fn = expand_and (FNADDR, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); \
1040: rtx g1_sethi = gen_rtx (HIGH, SImode, \
1041: gen_rtx (CONST_INT, VOIDmode, 0x03000000)); \
1042: rtx g2_sethi = gen_rtx (HIGH, SImode, \
1043: gen_rtx (CONST_INT, VOIDmode, 0x05000000)); \
1044: rtx g1_ori = gen_rtx (HIGH, SImode, \
1045: gen_rtx (CONST_INT, VOIDmode, 0x82106000)); \
1046: rtx g2_ori = gen_rtx (HIGH, SImode, \
1047: gen_rtx (CONST_INT, VOIDmode, 0x8410A000)); \
1048: rtx tem = gen_reg_rtx (SImode); \
1049: emit_move_insn (tem, g1_sethi); \
1050: emit_insn (gen_iorsi3 (high_fn, high_fn, tem)); \
1051: emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 0)), high_fn);\
1052: emit_move_insn (tem, g1_ori); \
1053: emit_insn (gen_iorsi3 (low_fn, low_fn, tem)); \
1054: emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 4)), low_fn);\
1055: emit_move_insn (tem, g2_sethi); \
1056: emit_insn (gen_iorsi3 (high_cxt, high_cxt, tem)); \
1057: emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 8)), high_cxt);\
1058: emit_move_insn (tem, g2_ori); \
1059: emit_insn (gen_iorsi3 (low_cxt, low_cxt, tem)); \
1060: emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 16)), low_cxt);\
1061: emit_insn (gen_rtx (UNSPEC_VOLATILE, VOIDmode, \
1062: gen_rtvec (1, plus_constant (TRAMP, 0)), \
1063: 2)); \
1064: emit_insn (gen_rtx (UNSPEC_VOLATILE, VOIDmode, \
1065: gen_rtvec (1, plus_constant (TRAMP, 8)), \
1066: 2)); \
1067: emit_insn (gen_rtx (UNSPEC_VOLATILE, VOIDmode, \
1068: gen_rtvec (1, plus_constant (TRAMP, 16)), \
1069: 2)); \
1070: }
1071:
1072: /* Generate necessary RTL for __builtin_saveregs().
1073: ARGLIST is the argument list; see expr.c. */
1074: extern struct rtx_def *sparc_builtin_saveregs ();
1075: #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) sparc_builtin_saveregs (ARGLIST)
1076:
1077: /* Generate RTL to flush the register windows so as to make arbitrary frames
1078: available. */
1079: #define SETUP_FRAME_ADDRESSES() \
1080: emit_insn (gen_flush_register_windows ())
1081:
1082: /* Given an rtx for the address of a frame,
1083: return an rtx for the address of the word in the frame
1084: that holds the dynamic chain--the previous frame's address. */
1085: #define DYNAMIC_CHAIN_ADDRESS(frame) \
1086: gen_rtx (PLUS, Pmode, frame, gen_rtx (CONST_INT, VOIDmode, 56))
1087:
1088: /* The return address isn't on the stack, it is in a register, so we can't
1089: access it from the current frame pointer. We can access it from the
1090: previous frame pointer though by reading a value from the register window
1091: save area. */
1092: #define RETURN_ADDR_IN_PREVIOUS_FRAME
1093:
1094: /* The current return address is in %i7. The return address of anything
1095: farther back is in the register window save area at [%fp+60]. */
1096: /* ??? This ignores the fact that the actual return address is +8 for normal
1097: returns, and +12 for structure returns. */
1098: #define RETURN_ADDR_RTX(count, frame) \
1099: ((count == -1) \
1100: ? gen_rtx (REG, Pmode, 31) \
1101: : copy_to_reg (gen_rtx (MEM, Pmode, \
1102: memory_address (Pmode, plus_constant (frame, 60)))))
1103:
1104: /* Addressing modes, and classification of registers for them. */
1105:
1106: /* #define HAVE_POST_INCREMENT */
1107: /* #define HAVE_POST_DECREMENT */
1108:
1109: /* #define HAVE_PRE_DECREMENT */
1110: /* #define HAVE_PRE_INCREMENT */
1111:
1112: /* Macros to check register numbers against specific register classes. */
1113:
1114: /* These assume that REGNO is a hard or pseudo reg number.
1115: They give nonzero only if REGNO is a hard reg of the suitable class
1116: or a pseudo reg currently allocated to a suitable hard reg.
1117: Since they use reg_renumber, they are safe only once reg_renumber
1118: has been allocated, which happens in local-alloc.c. */
1119:
1120: #define REGNO_OK_FOR_INDEX_P(REGNO) \
1121: (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0)
1122: #define REGNO_OK_FOR_BASE_P(REGNO) \
1123: (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0)
1124: #define REGNO_OK_FOR_FP_P(REGNO) \
1125: (((REGNO) ^ 0x20) < 32 \
1126: || (((REGNO) != 0) && (unsigned) (reg_renumber[REGNO] ^ 0x20) < 32))
1127:
1128: /* Now macros that check whether X is a register and also,
1129: strictly, whether it is in a specified class.
1130:
1131: These macros are specific to the SPARC, and may be used only
1132: in code for printing assembler insns and in conditions for
1133: define_optimization. */
1134:
1135: /* 1 if X is an fp register. */
1136:
1137: #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1138:
1139: /* Maximum number of registers that can appear in a valid memory address. */
1140:
1141: #define MAX_REGS_PER_ADDRESS 2
1142:
1143: /* Recognize any constant value that is a valid address.
1144: When PIC, we do not accept an address that would require a scratch reg
1145: to load into a register. */
1146:
1147: #define CONSTANT_ADDRESS_P(X) \
1148: (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1149: || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
1150: || (GET_CODE (X) == CONST \
1151: && ! (flag_pic && pic_address_needs_scratch (X))))
1152:
1153: /* Define this, so that when PIC, reload won't try to reload invalid
1154: addresses which require two reload registers. */
1155:
1156: #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
1157:
1158: /* Nonzero if the constant value X is a legitimate general operand.
1159: Anything can be made to work except floating point constants. */
1160:
1161: #define LEGITIMATE_CONSTANT_P(X) \
1162: (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode)
1163:
1164: /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1165: and check its validity for a certain class.
1166: We have two alternate definitions for each of them.
1167: The usual definition accepts all pseudo regs; the other rejects
1168: them unless they have been allocated suitable hard regs.
1169: The symbol REG_OK_STRICT causes the latter definition to be used.
1170:
1171: Most source files want to accept pseudo regs in the hope that
1172: they will get allocated to the class that the insn wants them to be in.
1173: Source files for reload pass need to be strict.
1174: After reload, it makes no difference, since pseudo regs have
1175: been eliminated by then. */
1176:
1177: /* Optional extra constraints for this machine. Borrowed from romp.h.
1178:
1179: For the SPARC, `Q' means that this is a memory operand but not a
1180: symbolic memory operand. Note that an unassigned pseudo register
1181: is such a memory operand. Needed because reload will generate
1182: these things in insns and then not re-recognize the insns, causing
1183: constrain_operands to fail.
1184:
1185: `S' handles constraints for calls. */
1186:
1187: #ifndef REG_OK_STRICT
1188:
1189: /* Nonzero if X is a hard reg that can be used as an index
1190: or if it is a pseudo reg. */
1191: #define REG_OK_FOR_INDEX_P(X) (((unsigned) REGNO (X)) - 32 >= 32 && REGNO (X) != 0)
1192: /* Nonzero if X is a hard reg that can be used as a base reg
1193: or if it is a pseudo reg. */
1194: #define REG_OK_FOR_BASE_P(X) (((unsigned) REGNO (X)) - 32 >= 32 && REGNO (X) != 0)
1195:
1196: #define EXTRA_CONSTRAINT(OP, C) \
1197: ((C) == 'Q' \
1198: ? ((GET_CODE (OP) == MEM \
1199: && memory_address_p (GET_MODE (OP), XEXP (OP, 0)) \
1200: && ! symbolic_memory_operand (OP, VOIDmode)) \
1201: || (reload_in_progress && GET_CODE (OP) == REG \
1202: && REGNO (OP) >= FIRST_PSEUDO_REGISTER)) \
1203: : (C) == 'T' \
1204: ? (mem_aligned_8 (OP)) \
1205: : (C) == 'U' \
1206: ? (register_ok_for_ldd (OP)) \
1207: : 0)
1208:
1209: #else
1210:
1211: /* Nonzero if X is a hard reg that can be used as an index. */
1212: #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1213: /* Nonzero if X is a hard reg that can be used as a base reg. */
1214: #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1215:
1216: #define EXTRA_CONSTRAINT(OP, C) \
1217: ((C) == 'Q' \
1218: ? (GET_CODE (OP) == REG \
1219: ? (REGNO (OP) >= FIRST_PSEUDO_REGISTER \
1220: && reg_renumber[REGNO (OP)] < 0) \
1221: : GET_CODE (OP) == MEM) \
1222: : (C) == 'T' \
1223: ? mem_aligned_8 (OP) && strict_memory_address_p (Pmode, XEXP (OP, 0)) \
1224: : (C) == 'U' \
1225: ? (GET_CODE (OP) == REG \
1226: && (REGNO (OP) < FIRST_PSEUDO_REGISTER \
1227: || reg_renumber[REGNO (OP)] > 0) \
1228: && register_ok_for_ldd (OP)) : 0)
1229: #endif
1230:
1231: /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1232: that is a valid memory address for an instruction.
1233: The MODE argument is the machine mode for the MEM expression
1234: that wants to use this address.
1235:
1236: On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
1237: ordinarily. This changes a bit when generating PIC.
1238:
1239: If you change this, execute "rm explow.o recog.o reload.o". */
1240:
1241: #define RTX_OK_FOR_BASE_P(X) \
1242: ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1243: || (GET_CODE (X) == SUBREG \
1244: && GET_CODE (SUBREG_REG (X)) == REG \
1245: && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
1246:
1247: #define RTX_OK_FOR_INDEX_P(X) \
1248: ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1249: || (GET_CODE (X) == SUBREG \
1250: && GET_CODE (SUBREG_REG (X)) == REG \
1251: && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
1252:
1253: #define RTX_OK_FOR_OFFSET_P(X) \
1254: (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000)
1255:
1256: #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1257: { if (RTX_OK_FOR_BASE_P (X)) \
1258: goto ADDR; \
1259: else if (GET_CODE (X) == PLUS) \
1260: { \
1261: register rtx op0 = XEXP (X, 0); \
1262: register rtx op1 = XEXP (X, 1); \
1263: if (flag_pic && op0 == pic_offset_table_rtx) \
1264: { \
1265: if (RTX_OK_FOR_BASE_P (op1)) \
1266: goto ADDR; \
1267: else if (flag_pic == 1 \
1268: && GET_CODE (op1) != REG \
1269: && GET_CODE (op1) != LO_SUM \
1270: && GET_CODE (op1) != MEM \
1271: && (GET_CODE (op1) != CONST_INT \
1272: || SMALL_INT (op1))) \
1273: goto ADDR; \
1274: } \
1275: else if (RTX_OK_FOR_BASE_P (op0)) \
1276: { \
1277: if (RTX_OK_FOR_INDEX_P (op1) \
1278: || RTX_OK_FOR_OFFSET_P (op1)) \
1279: goto ADDR; \
1280: } \
1281: else if (RTX_OK_FOR_BASE_P (op1)) \
1282: { \
1283: if (RTX_OK_FOR_INDEX_P (op0) \
1284: || RTX_OK_FOR_OFFSET_P (op0)) \
1285: goto ADDR; \
1286: } \
1287: } \
1288: else if (GET_CODE (X) == LO_SUM) \
1289: { \
1290: register rtx op0 = XEXP (X, 0); \
1291: register rtx op1 = XEXP (X, 1); \
1292: if (RTX_OK_FOR_BASE_P (op0) \
1293: && CONSTANT_P (op1)) \
1294: goto ADDR; \
1295: } \
1296: else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \
1297: goto ADDR; \
1298: }
1299:
1300: /* Try machine-dependent ways of modifying an illegitimate address
1301: to be legitimate. If we find one, return the new, valid address.
1302: This macro is used in only one place: `memory_address' in explow.c.
1303:
1304: OLDX is the address as it was before break_out_memory_refs was called.
1305: In some cases it is useful to look at this to decide what needs to be done.
1306:
1307: MODE and WIN are passed so that this macro can use
1308: GO_IF_LEGITIMATE_ADDRESS.
1309:
1310: It is always safe for this macro to do nothing. It exists to recognize
1311: opportunities to optimize the output. */
1312:
1313: /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
1314: extern struct rtx_def *legitimize_pic_address ();
1315: #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1316: { rtx sparc_x = (X); \
1317: if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \
1318: (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \
1319: force_operand (XEXP (X, 0), NULL_RTX)); \
1320: if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \
1321: (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1322: force_operand (XEXP (X, 1), NULL_RTX)); \
1323: if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \
1324: (X) = gen_rtx (PLUS, Pmode, force_operand (XEXP (X, 0), NULL_RTX),\
1325: XEXP (X, 1)); \
1326: if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \
1327: (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1328: force_operand (XEXP (X, 1), NULL_RTX)); \
1329: if (sparc_x != (X) && memory_address_p (MODE, X)) \
1330: goto WIN; \
1331: if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0); \
1332: else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1333: (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1334: copy_to_mode_reg (Pmode, XEXP (X, 1))); \
1335: else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \
1336: (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \
1337: copy_to_mode_reg (Pmode, XEXP (X, 0))); \
1338: else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
1339: || GET_CODE (X) == LABEL_REF) \
1340: (X) = gen_rtx (LO_SUM, Pmode, \
1341: copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \
1342: if (memory_address_p (MODE, X)) \
1343: goto WIN; }
1344:
1345: /* Go to LABEL if ADDR (a legitimate address expression)
1346: has an effect that depends on the machine mode it is used for.
1347: On the SPARC this is never true. */
1348:
1349: #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
1350:
1351: /* Specify the machine mode that this machine uses
1352: for the index in the tablejump instruction. */
1353: #define CASE_VECTOR_MODE SImode
1354:
1355: /* Define this if the tablejump instruction expects the table
1356: to contain offsets from the address of the table.
1357: Do not define this if the table should contain absolute addresses. */
1358: /* #define CASE_VECTOR_PC_RELATIVE */
1359:
1360: /* Specify the tree operation to be used to convert reals to integers. */
1361: #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1362:
1363: /* This is the kind of divide that is easiest to do in the general case. */
1364: #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1365:
1366: /* Define this as 1 if `char' should by default be signed; else as 0. */
1367: #define DEFAULT_SIGNED_CHAR 1
1368:
1369: /* Max number of bytes we can move from memory to memory
1370: in one reasonably fast instruction. */
1371: #define MOVE_MAX 8
1372:
1373: #if 0 /* Sun 4 has matherr, so this is no good. */
1374: /* This is the value of the error code EDOM for this machine,
1375: used by the sqrt instruction. */
1376: #define TARGET_EDOM 33
1377:
1378: /* This is how to refer to the variable errno. */
1379: #define GEN_ERRNO_RTX \
1380: gen_rtx (MEM, SImode, gen_rtx (SYMBOL_REF, Pmode, "errno"))
1381: #endif /* 0 */
1382:
1383: /* Define if operations between registers always perform the operation
1384: on the full register even if a narrower mode is specified. */
1385: #define WORD_REGISTER_OPERATIONS
1386:
1387: /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1388: will either zero-extend or sign-extend. The value of this macro should
1389: be the code that says which one of the two operations is implicitly
1390: done, NIL if none. */
1391: #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1392:
1393: /* Nonzero if access to memory by bytes is slow and undesirable.
1394: For RISC chips, it means that access to memory by bytes is no
1395: better than access by words when possible, so grab a whole word
1396: and maybe make use of that. */
1397: #define SLOW_BYTE_ACCESS 1
1398:
1399: /* We assume that the store-condition-codes instructions store 0 for false
1400: and some other value for true. This is the value stored for true. */
1401:
1402: #define STORE_FLAG_VALUE 1
1403:
1404: /* When a prototype says `char' or `short', really pass an `int'. */
1405: #define PROMOTE_PROTOTYPES
1406:
1407: /* Define this to be nonzero if shift instructions ignore all but the low-order
1408: few bits. */
1409: #define SHIFT_COUNT_TRUNCATED 1
1410:
1411: /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1412: is done just by pretending it is already truncated. */
1413: #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1414:
1415: /* Specify the machine mode that pointers have.
1416: After generation of rtl, the compiler makes no further distinction
1417: between pointers and any other objects of this machine mode. */
1418: #define Pmode SImode
1419:
1420: /* Generate calls to memcpy, memcmp and memset. */
1421: #define TARGET_MEM_FUNCTIONS
1422:
1423: /* Add any extra modes needed to represent the condition code.
1424:
1425: On the Sparc, we have a "no-overflow" mode which is used when an add or
1426: subtract insn is used to set the condition code. Different branches are
1427: used in this case for some operations.
1428:
1429: We also have two modes to indicate that the relevant condition code is
1430: in the floating-point condition code register. One for comparisons which
1431: will generate an exception if the result is unordered (CCFPEmode) and
1432: one for comparisons which will never trap (CCFPmode). This really should
1433: be a separate register, but we don't want to go to 65 registers. */
1434: #define EXTRA_CC_MODES CC_NOOVmode, CCFPmode, CCFPEmode
1435:
1436: /* Define the names for the modes specified above. */
1437: #define EXTRA_CC_NAMES "CC_NOOV", "CCFP", "CCFPE"
1438:
1439: /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1440: return the mode to be used for the comparison. For floating-point,
1441: CCFP[E]mode is used. CC_NOOVmode should be used when the first operand is a
1442: PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
1443: processing is needed. */
1444: #define SELECT_CC_MODE(OP,X,Y) \
1445: (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1446: ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \
1447: : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \
1448: || GET_CODE (X) == NEG || GET_CODE (X) == ASHIFT) \
1449: ? CC_NOOVmode : CCmode))
1450:
1451: /* A function address in a call instruction
1452: is a byte address (for indexing purposes)
1453: so give the MEM rtx a byte's mode. */
1454: #define FUNCTION_MODE SImode
1455:
1456: /* Define this if addresses of constant functions
1457: shouldn't be put through pseudo regs where they can be cse'd.
1458: Desirable on machines where ordinary constants are expensive
1459: but a CALL with constant address is cheap. */
1460: #define NO_FUNCTION_CSE
1461:
1462: /* alloca should avoid clobbering the old register save area. */
1463: #define SETJMP_VIA_SAVE_AREA
1464:
1465: /* Define subroutines to call to handle multiply and divide.
1466: Use the subroutines that Sun's library provides.
1467: The `*' prevents an underscore from being prepended by the compiler. */
1468:
1469: #define DIVSI3_LIBCALL "*.div"
1470: #define UDIVSI3_LIBCALL "*.udiv"
1471: #define MODSI3_LIBCALL "*.rem"
1472: #define UMODSI3_LIBCALL "*.urem"
1473: /* .umul is a little faster than .mul. */
1474: #define MULSI3_LIBCALL "*.umul"
1475:
1476: /* Compute the cost of computing a constant rtl expression RTX
1477: whose rtx-code is CODE. The body of this macro is a portion
1478: of a switch statement. If the code is computed here,
1479: return it with a return statement. Otherwise, break from the switch. */
1480:
1481: #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1482: case CONST_INT: \
1483: if (INTVAL (RTX) < 0x1000 && INTVAL (RTX) >= -0x1000) \
1484: return 0; \
1485: case HIGH: \
1486: return 2; \
1487: case CONST: \
1488: case LABEL_REF: \
1489: case SYMBOL_REF: \
1490: return 4; \
1491: case CONST_DOUBLE: \
1492: if (GET_MODE (RTX) == DImode) \
1493: if ((XINT (RTX, 3) == 0 \
1494: && (unsigned) XINT (RTX, 2) < 0x1000) \
1495: || (XINT (RTX, 3) == -1 \
1496: && XINT (RTX, 2) < 0 \
1497: && XINT (RTX, 2) >= -0x1000)) \
1498: return 0; \
1499: return 8;
1500:
1501: /* SPARC offers addressing modes which are "as cheap as a register".
1502: See sparc.c (or gcc.texinfo) for details. */
1503:
1504: #define ADDRESS_COST(RTX) \
1505: (GET_CODE (RTX) == REG ? 1 : sparc_address_cost (RTX))
1506:
1507: /* Compute extra cost of moving data between one register class
1508: and another. */
1509: #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
1510: (((CLASS1 == FP_REGS && CLASS2 == GENERAL_REGS) \
1511: || (CLASS1 == GENERAL_REGS && CLASS2 == FP_REGS)) ? 6 : 2)
1512:
1513: /* Provide the costs of a rtl expression. This is in the body of a
1514: switch on CODE. The purpose for the cost of MULT is to encourage
1515: `synth_mult' to find a synthetic multiply when reasonable.
1516:
1517: If we need more than 12 insns to do a multiply, then go out-of-line,
1518: since the call overhead will be < 10% of the cost of the multiply. */
1519:
1520: #define RTX_COSTS(X,CODE,OUTER_CODE) \
1521: case MULT: \
1522: return TARGET_V8 ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25); \
1523: case DIV: \
1524: case UDIV: \
1525: case MOD: \
1526: case UMOD: \
1527: return COSTS_N_INSNS (25); \
1528: /* Make FLOAT and FIX more expensive than CONST_DOUBLE,\
1529: so that cse will favor the latter. */ \
1530: case FLOAT: \
1531: case FIX: \
1532: return 19;
1533:
1534: /* Conditional branches with empty delay slots have a length of two. */
1535: #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
1536: if (GET_CODE (INSN) == CALL_INSN \
1537: || (GET_CODE (INSN) == JUMP_INSN && ! simplejump_p (insn))) \
1538: LENGTH += 1;
1539:
1540: /* Control the assembler format that we output. */
1541:
1542: /* Output at beginning of assembler file. */
1543:
1544: #define ASM_FILE_START(file)
1545:
1546: /* Output to assembler file text saying following lines
1547: may contain character constants, extra white space, comments, etc. */
1548:
1549: #define ASM_APP_ON ""
1550:
1551: /* Output to assembler file text saying following lines
1552: no longer contain unusual constructs. */
1553:
1554: #define ASM_APP_OFF ""
1555:
1556: #define ASM_LONG ".word"
1557: #define ASM_SHORT ".half"
1558: #define ASM_BYTE_OP ".byte"
1559:
1560: /* Output before read-only data. */
1561:
1562: #define TEXT_SECTION_ASM_OP ".text"
1563:
1564: /* Output before writable data. */
1565:
1566: #define DATA_SECTION_ASM_OP ".data"
1567:
1568: /* How to refer to registers in assembler output.
1569: This sequence is indexed by compiler's hard-register-number (see above). */
1570:
1571: #define REGISTER_NAMES \
1572: {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
1573: "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
1574: "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
1575: "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
1576: "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
1577: "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
1578: "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
1579: "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31"}
1580:
1581: /* Define additional names for use in asm clobbers and asm declarations.
1582:
1583: We define the fake Condition Code register as an alias for reg 0 (which
1584: is our `condition code' register), so that condition codes can easily
1585: be clobbered by an asm. No such register actually exists. Condition
1586: codes are partly stored in the PSR and partly in the FSR. */
1587:
1588: #define ADDITIONAL_REGISTER_NAMES {"ccr", 0, "cc", 0}
1589:
1590: /* How to renumber registers for dbx and gdb. */
1591:
1592: #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1593:
1594: /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1595: since the length can run past this up to a continuation point. */
1596: #define DBX_CONTIN_LENGTH 1500
1597:
1598: /* This is how to output a note to DBX telling it the line number
1599: to which the following sequence of instructions corresponds.
1600:
1601: This is needed for SunOS 4.0, and should not hurt for 3.2
1602: versions either. */
1603: #define ASM_OUTPUT_SOURCE_LINE(file, line) \
1604: { static int sym_lineno = 1; \
1605: fprintf (file, ".stabn 68,0,%d,LM%d\nLM%d:\n", \
1606: line, sym_lineno, sym_lineno); \
1607: sym_lineno += 1; }
1608:
1609: /* This is how to output the definition of a user-level label named NAME,
1610: such as the label on a static function or variable NAME. */
1611:
1612: #define ASM_OUTPUT_LABEL(FILE,NAME) \
1613: do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1614:
1615: /* This is how to output a command to make the user-level label named NAME
1616: defined for reference from other files. */
1617:
1618: #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1619: do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
1620:
1621: /* This is how to output a reference to a user-level label named NAME.
1622: `assemble_name' uses this. */
1623:
1624: #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1625: fprintf (FILE, "_%s", NAME)
1626:
1627: /* This is how to output a definition of an internal numbered label where
1628: PREFIX is the class of label and NUM is the number within the class. */
1629:
1630: #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1631: fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1632:
1633: /* This is how to output a reference to an internal numbered label where
1634: PREFIX is the class of label and NUM is the number within the class. */
1635: /* FIXME: This should be used throughout gcc, and documented in the texinfo
1636: files. There is no reason you should have to allocate a buffer and
1637: `sprintf' to reference an internal label (as opposed to defining it). */
1638:
1639: #define ASM_OUTPUT_INTERNAL_LABELREF(FILE,PREFIX,NUM) \
1640: fprintf (FILE, "%s%d", PREFIX, NUM)
1641:
1642: /* This is how to store into the string LABEL
1643: the symbol_ref name of an internal numbered label where
1644: PREFIX is the class of label and NUM is the number within the class.
1645: This is suitable for output with `assemble_name'. */
1646:
1647: #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1648: sprintf (LABEL, "*%s%d", PREFIX, NUM)
1649:
1650: /* This is how to output an assembler line defining a `double' constant. */
1651:
1652: #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1653: { \
1654: long t[2]; \
1655: REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
1656: fprintf (FILE, "\t%s\t0x%lx\n\t%s\t0x%lx\n", \
1657: ASM_LONG, t[0], ASM_LONG, t[1]); \
1658: }
1659:
1660: /* This is how to output an assembler line defining a `float' constant. */
1661:
1662: #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1663: { \
1664: long t; \
1665: REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
1666: fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t); \
1667: } \
1668:
1669: /* This is how to output an assembler line defining a `long double'
1670: constant. */
1671:
1672: #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \
1673: { \
1674: long t[4]; \
1675: REAL_VALUE_TO_TARGET_LONG_DOUBLE ((VALUE), t); \
1676: fprintf (FILE, "\t%s\t0x%lx\n\t%s\t0x%lx\n\t%s\t0x%lx\n\t%s\t0x%lx\n", \
1677: ASM_LONG, t[0], ASM_LONG, t[1], ASM_LONG, t[2], ASM_LONG, t[3]); \
1678: }
1679:
1680: /* This is how to output an assembler line defining an `int' constant. */
1681:
1682: #define ASM_OUTPUT_INT(FILE,VALUE) \
1683: ( fprintf (FILE, "\t%s\t", ASM_LONG), \
1684: output_addr_const (FILE, (VALUE)), \
1685: fprintf (FILE, "\n"))
1686:
1687: /* This is how to output an assembler line defining a DImode constant. */
1688: #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
1689: output_double_int (FILE, VALUE)
1690:
1691: /* Likewise for `char' and `short' constants. */
1692:
1693: #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1694: ( fprintf (FILE, "\t%s\t", ASM_SHORT), \
1695: output_addr_const (FILE, (VALUE)), \
1696: fprintf (FILE, "\n"))
1697:
1698: #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1699: ( fprintf (FILE, "\t%s\t", ASM_BYTE_OP), \
1700: output_addr_const (FILE, (VALUE)), \
1701: fprintf (FILE, "\n"))
1702:
1703: /* This is how to output an assembler line for a numeric constant byte. */
1704:
1705: #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1706: fprintf (FILE, "\t%s\t0x%x\n", ASM_BYTE_OP, (VALUE))
1707:
1708: /* This is how to output an element of a case-vector that is absolute. */
1709:
1710: #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1711: do { \
1712: char label[30]; \
1713: ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1714: fprintf (FILE, "\t.word\t"); \
1715: assemble_name (FILE, label); \
1716: fprintf (FILE, "\n"); \
1717: } while (0)
1718:
1719: /* This is how to output an element of a case-vector that is relative.
1720: (SPARC uses such vectors only when generating PIC.) */
1721:
1722: #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1723: do { \
1724: char label[30]; \
1725: ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1726: fprintf (FILE, "\t.word\t"); \
1727: assemble_name (FILE, label); \
1728: fprintf (FILE, "-1b\n"); \
1729: } while (0)
1730:
1731: /* This is how to output an assembler line
1732: that says to advance the location counter
1733: to a multiple of 2**LOG bytes. */
1734:
1735: #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1736: if ((LOG) != 0) \
1737: fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
1738:
1739: #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1740: fprintf (FILE, "\t.skip %u\n", (SIZE))
1741:
1742: /* This says how to output an assembler line
1743: to define a global common symbol. */
1744:
1745: #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1746: ( fputs ("\t.global ", (FILE)), \
1747: assemble_name ((FILE), (NAME)), \
1748: fputs ("\n\t.common ", (FILE)), \
1749: assemble_name ((FILE), (NAME)), \
1750: fprintf ((FILE), ",%u,\"bss\"\n", (ROUNDED)))
1751:
1752: /* This says how to output an assembler line
1753: to define a local common symbol. */
1754:
1755: #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1756: ( fputs ("\n\t.reserve ", (FILE)), \
1757: assemble_name ((FILE), (NAME)), \
1758: fprintf ((FILE), ",%u,\"bss\"\n", (ROUNDED)))
1759:
1760: /* Store in OUTPUT a string (made with alloca) containing
1761: an assembler-name for a local static variable named NAME.
1762: LABELNO is an integer which is different for each call. */
1763:
1764: #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1765: ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1766: sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1767:
1768: #define IDENT_ASM_OP ".ident"
1769:
1770: /* Output #ident as a .ident. */
1771:
1772: #define ASM_OUTPUT_IDENT(FILE, NAME) \
1773: fprintf (FILE, "\t%s\t\"%s\"\n", IDENT_ASM_OP, NAME);
1774:
1775: /* Define the parentheses used to group arithmetic operations
1776: in assembler code. */
1777:
1778: #define ASM_OPEN_PAREN "("
1779: #define ASM_CLOSE_PAREN ")"
1780:
1781: /* Define results of standard character escape sequences. */
1782: #define TARGET_BELL 007
1783: #define TARGET_BS 010
1784: #define TARGET_TAB 011
1785: #define TARGET_NEWLINE 012
1786: #define TARGET_VT 013
1787: #define TARGET_FF 014
1788: #define TARGET_CR 015
1789:
1790: #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1791: ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '(')
1792:
1793: /* Print operand X (an rtx) in assembler syntax to file FILE.
1794: CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1795: For `%' followed by punctuation, CODE is the punctuation and X is null. */
1796:
1797: #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1798:
1799: /* Print a memory address as an operand to reference that memory location. */
1800:
1801: #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1802: { register rtx base, index = 0; \
1803: int offset = 0; \
1804: register rtx addr = ADDR; \
1805: if (GET_CODE (addr) == REG) \
1806: fputs (reg_names[REGNO (addr)], FILE); \
1807: else if (GET_CODE (addr) == PLUS) \
1808: { \
1809: if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
1810: offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
1811: else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
1812: offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
1813: else \
1814: base = XEXP (addr, 0), index = XEXP (addr, 1); \
1815: fputs (reg_names[REGNO (base)], FILE); \
1816: if (index == 0) \
1817: fprintf (FILE, "%+d", offset); \
1818: else if (GET_CODE (index) == REG) \
1819: fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
1820: else if (GET_CODE (index) == SYMBOL_REF) \
1821: fputc ('+', FILE), output_addr_const (FILE, index); \
1822: else abort (); \
1823: } \
1824: else if (GET_CODE (addr) == MINUS \
1825: && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
1826: { \
1827: output_addr_const (FILE, XEXP (addr, 0)); \
1828: fputs ("-(", FILE); \
1829: output_addr_const (FILE, XEXP (addr, 1)); \
1830: fputs ("-.)", FILE); \
1831: } \
1832: else if (GET_CODE (addr) == LO_SUM) \
1833: { \
1834: output_operand (XEXP (addr, 0), 0); \
1835: fputs ("+%lo(", FILE); \
1836: output_address (XEXP (addr, 1)); \
1837: fputc (')', FILE); \
1838: } \
1839: else if (flag_pic && GET_CODE (addr) == CONST \
1840: && GET_CODE (XEXP (addr, 0)) == MINUS \
1841: && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
1842: && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
1843: && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
1844: { \
1845: addr = XEXP (addr, 0); \
1846: output_addr_const (FILE, XEXP (addr, 0)); \
1847: /* Group the args of the second CONST in parenthesis. */ \
1848: fputs ("-(", FILE); \
1849: /* Skip past the second CONST--it does nothing for us. */\
1850: output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
1851: /* Close the parenthesis. */ \
1852: fputc (')', FILE); \
1853: } \
1854: else \
1855: { \
1856: output_addr_const (FILE, addr); \
1857: } \
1858: }
1859:
1860: /* Declare functions defined in sparc.c and used in templates. */
1861:
1862: extern char *singlemove_string ();
1863: extern char *output_move_double ();
1864: extern char *output_move_quad ();
1865: extern char *output_fp_move_double ();
1866: extern char *output_fp_move_quad ();
1867: extern char *output_block_move ();
1868: extern char *output_scc_insn ();
1869: extern char *output_cbranch ();
1870: extern char *output_return ();
1871:
1872: /* Defined in flags.h, but insn-emit.c does not include flags.h. */
1873:
1874: extern int flag_pic;
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.