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1.1 root 1: ;;- Machine description for GNU compiler
2: ;;- Tahoe version
3: ;; Copyright (C) 1989 Free Software Foundation, Inc.
4:
5: ;; This file is part of GNU CC.
6:
7: ;; GNU CC is free software; you can redistribute it and/or modify
8: ;; it under the terms of the GNU General Public License as published by
9: ;; the Free Software Foundation; either version 2, or (at your option)
10: ;; any later version.
11:
12: ;; GNU CC is distributed in the hope that it will be useful,
13: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: ;; GNU General Public License for more details.
16:
17: ;; You should have received a copy of the GNU General Public License
18: ;; along with GNU CC; see the file COPYING. If not, write to
19: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20:
21:
22: ; File: tahoe.md
23: ;
24: ; Original port made at the University of Buffalo by Devon Bowen,
25: ; Dale Wiles and Kevin Zachmann.
26: ;
27: ; Piet van Oostrum ([email protected]) made changes for HCX/UX, fixed
28: ; some bugs and made some improvements (hopefully).
29: ;
30: ; Mail bugs reports or fixes to: [email protected]
31:
32:
33: ; movdi must call the output_move_double routine to move it around since
34: ; the tahoe doesn't efficiently support 8 bit moves.
35:
36: (define_insn "movdi"
37: [(set (match_operand:DI 0 "general_operand" "=g")
38: (match_operand:DI 1 "general_operand" "g"))]
39: ""
40: "*
41: {
42: CC_STATUS_INIT;
43: return output_move_double (operands);
44: }")
45:
46:
47: ; the trick in the movsi is accessing the contents of the sp register. The
48: ; tahoe doesn't allow you to access it directly so you have to access the
49: ; address of the top of the stack instead.
50:
51: (define_insn "movsi"
52: [(set (match_operand:SI 0 "general_operand" "=g")
53: (match_operand:SI 1 "general_operand" "g"))]
54: ""
55: "*
56: {
57: rtx link;
58: if (operands[1] == const1_rtx
59: && (link = find_reg_note (insn, REG_WAS_0, 0))
60: && ! INSN_DELETED_P (XEXP (link, 0))
61: && GET_CODE (XEXP (link, 0)) != NOTE
62: && no_labels_between_p (XEXP (link, 0), insn)
63: /* Make sure the reg hasn't been clobbered. */
64: && ! reg_set_between_p (operands[0], XEXP (link, 0), insn))
65: return \"incl %0\";
66: if (GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST)
67: {
68: if (push_operand (operands[0], SImode))
69: return \"pushab %a1\";
70: return \"movab %a1,%0\";
71: }
72: if (operands[1] == const0_rtx)
73: return \"clrl %0\";
74: if (push_operand (operands[0], SImode))
75: return \"pushl %1\";
76: if (GET_CODE(operands[1]) == REG && REGNO(operands[1]) == 14)
77: return \"moval (sp),%0\";
78: return \"movl %1,%0\";
79: }")
80:
81:
82: (define_insn "movhi"
83: [(set (match_operand:HI 0 "general_operand" "=g")
84: (match_operand:HI 1 "general_operand" "g"))]
85: ""
86: "*
87: {
88: rtx link;
89: if (operands[1] == const1_rtx
90: && (link = find_reg_note (insn, REG_WAS_0, 0))
91: && ! INSN_DELETED_P (XEXP (link, 0))
92: && GET_CODE (XEXP (link, 0)) != NOTE
93: && no_labels_between_p (XEXP (link, 0), insn)
94: /* Make sure the reg hasn't been clobbered. */
95: && ! reg_set_between_p (operands[0], XEXP (link, 0), insn))
96: return \"incw %0\";
97: if (operands[1] == const0_rtx)
98: return \"clrw %0\";
99: return \"movw %1,%0\";
100: }")
101:
102:
103: (define_insn "movqi"
104: [(set (match_operand:QI 0 "general_operand" "=g")
105: (match_operand:QI 1 "general_operand" "g"))]
106: ""
107: "*
108: {
109: if (operands[1] == const0_rtx)
110: return \"clrb %0\";
111: return \"movb %1,%0\";
112: }")
113:
114:
115: ; movsf has three cases since they can move from one place to another
116: ; or to/from the fpp and since different instructions are needed for
117: ; each case. The fpp related instructions don't set the flags properly.
118:
119: (define_insn "movsf"
120: [(set (match_operand:SF 0 "general_operand" "=g,=a,=g")
121: (match_operand:SF 1 "general_operand" "g,g,a"))]
122: ""
123: "*
124: {
125: CC_STATUS_INIT;
126: switch (which_alternative)
127: {
128: case 0: return \"movl %1,%0\";
129: case 1: return \"ldf %1\";
130: case 2: return \"stf %0\";
131: }
132: }")
133:
134:
135: ; movdf has a number of different cases. If it's going to or from
136: ; the fpp, use the special instructions to do it. If not, use the
137: ; output_move_double function.
138:
139: (define_insn "movdf"
140: [(set (match_operand:DF 0 "general_operand" "=a,=g,?=g")
141: (match_operand:DF 1 "general_operand" "g,a,g"))]
142: ""
143: "*
144: {
145: CC_STATUS_INIT;
146: switch (which_alternative)
147: {
148: case 0:
149: return \"ldd %1\";
150: case 1:
151: if (push_operand (operands[0], DFmode))
152: return \"pushd\";
153: else
154: return \"std %0\";
155: case 2:
156: return output_move_double (operands);
157: }
158: }")
159:
160:
161: ;========================================================================
162: ; The tahoe has the following semantics for byte (and similar for word)
163: ; operands: if the operand is a register or immediate, it takes the full 32
164: ; bit operand, if the operand is memory, it sign-extends the byte. The
165: ; operation is performed on the 32 bit values. If the destination is a
166: ; register, the full 32 bit result is stored, if the destination is memory,
167: ; of course only the low part is stored. The condition code is based on the
168: ; 32 bit operation. Only on the movz instructions the byte from memory is
169: ; zero-extended rather than sign-extended.
170:
171: ; This means that for arithmetic instructions we can use addb etc. to
172: ; perform a long add from a signed byte from memory to a register. Of
173: ; course this would also work for logical operations, but that doesn't seem
174: ; very useful.
175:
176: (define_insn ""
177: [(set (match_operand:SI 0 "register_operand" "=r")
178: (plus:SI (sign_extend:SI (match_operand:QI 1 "memory_operand" "m"))
179: (sign_extend:SI (match_operand:QI 2 "memory_operand" "m"))))]
180: ""
181: "addb3 %1,%2,%0")
182:
183: (define_insn ""
184: [(set (match_operand:SI 0 "register_operand" "=r")
185: (plus:SI (match_operand:SI 1 "nonmemory_operand" "%ri")
186: (sign_extend:SI (match_operand:QI 2 "memory_operand" "m"))))]
187: ""
188: "*
189: {
190: if (rtx_equal_p (operands[0], operands[1]))
191: return \"addb2 %2,%0\";
192: return \"addb3 %1,%2,%0\";
193: }")
194:
195: ; We can also consider the result to be a half integer
196:
197: (define_insn ""
198: [(set (match_operand:HI 0 "register_operand" "=r")
199: (plus:HI (sign_extend:HI (match_operand:QI 1 "memory_operand" "m"))
200: (sign_extend:HI (match_operand:QI 2 "memory_operand" "m"))))]
201: ""
202: "addb3 %1,%2,%0")
203:
204: (define_insn ""
205: [(set (match_operand:HI 0 "register_operand" "=r")
206: (plus:HI (match_operand:HI 1 "nonmemory_operand" "%ri")
207: (sign_extend:HI (match_operand:QI 2 "memory_operand" "m"))))]
208: ""
209: "*
210: {
211: if (rtx_equal_p (operands[0], operands[1]))
212: return \"addb2 %2,%0\";
213: return \"addb3 %1,%2,%0\";
214: }")
215:
216: ; The same applies to words (HI)
217:
218: (define_insn ""
219: [(set (match_operand:SI 0 "register_operand" "=r")
220: (plus:SI (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))
221: (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))]
222: ""
223: "addw3 %1,%2,%0")
224:
225: (define_insn ""
226: [(set (match_operand:SI 0 "register_operand" "=r")
227: (plus:SI (match_operand:SI 1 "nonmemory_operand" "%ri")
228: (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))]
229: ""
230: "*
231: {
232: if (rtx_equal_p (operands[0], operands[1]))
233: return \"addw2 %2,%0\";
234: return \"addw3 %1,%2,%0\";
235: }")
236:
237: ; ======================= Now for subtract ==============================
238:
239: (define_insn ""
240: [(set (match_operand:SI 0 "register_operand" "=r")
241: (minus:SI (sign_extend:SI (match_operand:QI 1 "memory_operand" "m"))
242: (sign_extend:SI (match_operand:QI 2 "memory_operand" "m"))))]
243: ""
244: "subb3 %2,%1,%0")
245:
246: (define_insn ""
247: [(set (match_operand:SI 0 "register_operand" "=r")
248: (minus:SI (match_operand:SI 1 "nonmemory_operand" "ri")
249: (sign_extend:SI (match_operand:QI 2 "memory_operand" "m"))))]
250: ""
251: "*
252: {
253: if (rtx_equal_p (operands[0], operands[1]))
254: return \"subb2 %2,%0\";
255: return \"subb3 %2,%1,%0\";
256: }")
257:
258: (define_insn ""
259: [(set (match_operand:SI 0 "register_operand" "=r")
260: (minus:SI (sign_extend:SI (match_operand:QI 1 "memory_operand" "m"))
261: (match_operand:SI 2 "nonmemory_operand" "ri")))]
262: ""
263: "subb3 %2,%1,%0")
264:
265: ; We can also consider the result to be a half integer
266:
267: (define_insn ""
268: [(set (match_operand:HI 0 "register_operand" "=r")
269: (minus:HI (sign_extend:HI (match_operand:QI 1 "memory_operand" "m"))
270: (sign_extend:HI (match_operand:QI 2 "memory_operand" "m"))))]
271: ""
272: "subb3 %2,%1,%0")
273:
274: (define_insn ""
275: [(set (match_operand:HI 0 "register_operand" "=r")
276: (minus:HI (match_operand:HI 1 "nonmemory_operand" "%ri")
277: (sign_extend:HI (match_operand:QI 2 "memory_operand" "m"))))]
278: ""
279: "*
280: {
281: if (rtx_equal_p (operands[0], operands[1]))
282: return \"subb2 %2,%0\";
283: return \"subb3 %2,%1,%0\";
284: }")
285:
286: (define_insn ""
287: [(set (match_operand:HI 0 "register_operand" "=r")
288: (minus:HI (sign_extend:HI (match_operand:QI 1 "memory_operand" "m"))
289: (match_operand:HI 2 "nonmemory_operand" "ri")))]
290: ""
291: "subb3 %2,%1,%0")
292:
293: ; The same applies to words (HI)
294:
295: (define_insn ""
296: [(set (match_operand:SI 0 "register_operand" "=r")
297: (minus:SI (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))
298: (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))]
299: ""
300: "subw3 %2,%1,%0")
301:
302: (define_insn ""
303: [(set (match_operand:SI 0 "register_operand" "=r")
304: (minus:SI (match_operand:SI 1 "nonmemory_operand" "ri")
305: (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))]
306: ""
307: "*
308: {
309: if (rtx_equal_p (operands[0], operands[1]))
310: return \"subw2 %2,%0\";
311: return \"subw3 %2,%1,%0\";
312: }")
313:
314: (define_insn ""
315: [(set (match_operand:SI 0 "register_operand" "=r")
316: (minus:SI (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))
317: (match_operand:SI 2 "nonmemory_operand" "ri")))]
318: ""
319: "subw3 %2,%1,%0")
320:
321: ; ======================= Now for neg ==============================
322:
323: (define_insn ""
324: [(set (match_operand:SI 0 "register_operand" "=r")
325: (neg:SI (sign_extend:SI (match_operand:QI 1 "memory_operand" "m"))))]
326: ""
327: "mnegb %1,%0")
328:
329: (define_insn ""
330: [(set (match_operand:HI 0 "register_operand" "=r")
331: (neg:HI (sign_extend:HI (match_operand:QI 1 "memory_operand" "m"))))]
332: ""
333: "mnegb %1,%0")
334:
335: (define_insn ""
336: [(set (match_operand:SI 0 "register_operand" "=r")
337: (neg:SI (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))))]
338: ""
339: "mnegw %1,%0")
340:
341: ;========================================================================
342:
343:
344: (define_insn "addsi3"
345: [(set (match_operand:SI 0 "general_operand" "=g")
346: (plus:SI (match_operand:SI 1 "general_operand" "g")
347: (match_operand:SI 2 "general_operand" "g")))]
348: ""
349: "*
350: {
351: if (rtx_equal_p (operands[0], operands[1]))
352: {
353: if (operands[2] == const1_rtx)
354: return \"incl %0\";
355: if (GET_CODE (operands[2]) == CONST_INT
356: && INTVAL (operands[2]) == -1)
357: return \"decl %0\";
358: if (GET_CODE (operands[2]) == CONST_INT
359: && (unsigned) (- INTVAL (operands[2])) < 64)
360: return \"subl2 $%n2,%0\";
361: return \"addl2 %2,%0\";
362: }
363: if (rtx_equal_p (operands[0], operands[2]))
364: return \"addl2 %1,%0\";
365: if (GET_CODE (operands[2]) == CONST_INT
366: && GET_CODE (operands[1]) == REG)
367: {
368: if (push_operand (operands[0], SImode))
369: return \"pushab %c2(%1)\";
370: return \"movab %c2(%1),%0\";
371: }
372: if (GET_CODE (operands[2]) == CONST_INT
373: && (unsigned) (- INTVAL (operands[2])) < 64)
374: return \"subl3 $%n2,%1,%0\";
375: return \"addl3 %1,%2,%0\";
376: }")
377:
378:
379: (define_insn "addhi3"
380: [(set (match_operand:HI 0 "general_operand" "=g")
381: (plus:HI (match_operand:HI 1 "general_operand" "g")
382: (match_operand:HI 2 "general_operand" "g")))]
383: ""
384: "*
385: {
386: if (rtx_equal_p (operands[0], operands[1]))
387: {
388: if (operands[2] == const1_rtx)
389: return \"incw %0\";
390: if (GET_CODE (operands[2]) == CONST_INT
391: && INTVAL (operands[2]) == -1)
392: return \"decw %0\";
393: if (GET_CODE (operands[2]) == CONST_INT
394: && (unsigned) (- INTVAL (operands[2])) < 64)
395: return \"subw2 $%n2,%0\";
396: return \"addw2 %2,%0\";
397: }
398: if (rtx_equal_p (operands[0], operands[2]))
399: return \"addw2 %1,%0\";
400: if (GET_CODE (operands[2]) == CONST_INT
401: && (unsigned) (- INTVAL (operands[2])) < 64)
402: return \"subw3 $%n2,%1,%0\";
403: return \"addw3 %1,%2,%0\";
404: }")
405:
406:
407: (define_insn "addqi3"
408: [(set (match_operand:QI 0 "general_operand" "=g")
409: (plus:QI (match_operand:QI 1 "general_operand" "g")
410: (match_operand:QI 2 "general_operand" "g")))]
411: ""
412: "*
413: {
414: if (rtx_equal_p (operands[0], operands[1]))
415: {
416: if (operands[2] == const1_rtx)
417: return \"incb %0\";
418: if (GET_CODE (operands[2]) == CONST_INT
419: && INTVAL (operands[2]) == -1)
420: return \"decb %0\";
421: if (GET_CODE (operands[2]) == CONST_INT
422: && (unsigned) (- INTVAL (operands[2])) < 64)
423: return \"subb2 $%n2,%0\";
424: return \"addb2 %2,%0\";
425: }
426: if (rtx_equal_p (operands[0], operands[2]))
427: return \"addb2 %1,%0\";
428: if (GET_CODE (operands[2]) == CONST_INT
429: && (unsigned) (- INTVAL (operands[2])) < 64)
430: return \"subb3 $%n2,%1,%0\";
431: return \"addb3 %1,%2,%0\";
432: }")
433:
434: ; addsf3 can only add into the fpp register since the fpp is treated
435: ; as a separate unit in the machine. It also doesn't set the flags at
436: ; all.
437:
438: (define_insn "addsf3"
439: [(set (match_operand:SF 0 "register_operand" "=a")
440: (plus:SF (match_operand:SF 1 "register_operand" "%0")
441: (match_operand:SF 2 "general_operand" "g")))]
442: ""
443: "*
444: {
445: CC_STATUS_INIT;
446: return \"addf %2\";
447: }")
448:
449:
450: ; adddf3 can only add into the fpp reg since the fpp is treated as a
451: ; separate entity. Doubles can only be read from a register or memory
452: ; since a double is not an immediate mode. Flags are not set by this
453: ; instruction.
454:
455: (define_insn "adddf3"
456: [(set (match_operand:DF 0 "register_operand" "=a")
457: (plus:DF (match_operand:DF 1 "register_operand" "%0")
458: (match_operand:DF 2 "general_operand" "rm")))]
459: ""
460: "*
461: {
462: CC_STATUS_INIT;
463: return \"addd %2\";
464: }")
465:
466:
467: ; Subtraction from the sp (needed by the built in alloc function) needs
468: ; to be different since the sp cannot be directly read on the tahoe.
469: ; If it's a simple constant, you just use displacement. Otherwise, you
470: ; push the sp, and then do the subtraction off the stack.
471:
472: (define_insn "subsi3"
473: [(set (match_operand:SI 0 "general_operand" "=g")
474: (minus:SI (match_operand:SI 1 "general_operand" "g")
475: (match_operand:SI 2 "general_operand" "g")))]
476: ""
477: "*
478: {
479: if (rtx_equal_p (operands[0], operands[1]))
480: {
481: if (operands[2] == const1_rtx)
482: return \"decl %0\";
483: if (GET_CODE(operands[0]) == REG && REGNO(operands[0]) == 14)
484: {
485: if (GET_CODE(operands[2]) == CONST_INT)
486: return \"movab %n2(sp),sp\";
487: else
488: return \"pushab (sp)\;subl3 %2,(sp),sp\";
489: }
490: return \"subl2 %2,%0\";
491: }
492: if (rtx_equal_p (operands[1], operands[2]))
493: return \"clrl %0\";
494: return \"subl3 %2,%1,%0\";
495: }")
496:
497:
498: (define_insn "subhi3"
499: [(set (match_operand:HI 0 "general_operand" "=g")
500: (minus:HI (match_operand:HI 1 "general_operand" "g")
501: (match_operand:HI 2 "general_operand" "g")))]
502: ""
503: "*
504: {
505: if (rtx_equal_p (operands[0], operands[1]))
506: {
507: if (operands[2] == const1_rtx)
508: return \"decw %0\";
509: return \"subw2 %2,%0\";
510: }
511: if (rtx_equal_p (operands[1], operands[2]))
512: return \"clrw %0\";
513: return \"subw3 %2,%1,%0\";
514: }")
515:
516:
517: (define_insn "subqi3"
518: [(set (match_operand:QI 0 "general_operand" "=g")
519: (minus:QI (match_operand:QI 1 "general_operand" "g")
520: (match_operand:QI 2 "general_operand" "g")))]
521: ""
522: "*
523: {
524: if (rtx_equal_p (operands[0], operands[1]))
525: {
526: if (operands[2] == const1_rtx)
527: return \"decb %0\";
528: return \"subb2 %2,%0\";
529: }
530: if (rtx_equal_p (operands[1], operands[2]))
531: return \"clrb %0\";
532: return \"subb3 %2,%1,%0\";
533: }")
534:
535:
536: ; subsf3 can only subtract into the fpp accumulator due to the way
537: ; the fpp reg is limited by the instruction set. This also doesn't
538: ; bother setting up flags.
539:
540: (define_insn "subsf3"
541: [(set (match_operand:SF 0 "register_operand" "=a")
542: (minus:SF (match_operand:SF 1 "register_operand" "0")
543: (match_operand:SF 2 "general_operand" "g")))]
544: ""
545: "*
546: {
547: CC_STATUS_INIT;
548: return \"subf %2\";
549: }")
550:
551:
552: ; subdf3 is set up to subtract into the fpp reg due to limitations
553: ; of the fpp instruction set. Doubles can not be immediate. This
554: ; instruction does not set the flags.
555:
556: (define_insn "subdf3"
557: [(set (match_operand:DF 0 "register_operand" "=a")
558: (minus:DF (match_operand:DF 1 "register_operand" "0")
559: (match_operand:DF 2 "general_operand" "rm")))]
560: ""
561: "*
562: {
563: CC_STATUS_INIT;
564: return \"subd %2\";
565: }")
566:
567:
568: (define_insn "mulsi3"
569: [(set (match_operand:SI 0 "general_operand" "=g")
570: (mult:SI (match_operand:SI 1 "general_operand" "g")
571: (match_operand:SI 2 "general_operand" "g")))]
572: ""
573: "*
574: {
575: if (rtx_equal_p (operands[0], operands[1]))
576: return \"mull2 %2,%0\";
577: if (rtx_equal_p (operands[0], operands[2]))
578: return \"mull2 %1,%0\";
579: return \"mull3 %1,%2,%0\";
580: }")
581:
582:
583: ; mulsf3 can only multiply into the fpp accumulator due to limitations
584: ; of the fpp. It also does not set the condition codes properly.
585:
586: (define_insn "mulsf3"
587: [(set (match_operand:SF 0 "register_operand" "=a")
588: (mult:SF (match_operand:SF 1 "register_operand" "%0")
589: (match_operand:SF 2 "general_operand" "g")))]
590: ""
591: "*
592: {
593: CC_STATUS_INIT;
594: return \"mulf %2\";
595: }")
596:
597:
598: ; muldf3 can only multiply into the fpp reg since the fpp is limited
599: ; from the rest. Doubles may not be immediate mode. This does not set
600: ; the flags like gcc would expect.
601:
602: (define_insn "muldf3"
603: [(set (match_operand:DF 0 "register_operand" "=a")
604: (mult:DF (match_operand:DF 1 "register_operand" "%0")
605: (match_operand:DF 2 "general_operand" "rm")))]
606: ""
607: "*
608: {
609: CC_STATUS_INIT;
610: return \"muld %2\";
611: }")
612:
613:
614:
615: (define_insn "divsi3"
616: [(set (match_operand:SI 0 "general_operand" "=g")
617: (div:SI (match_operand:SI 1 "general_operand" "g")
618: (match_operand:SI 2 "general_operand" "g")))]
619: ""
620: "*
621: {
622: if (rtx_equal_p (operands[1], operands[2]))
623: return \"movl $1,%0\";
624: if (operands[1] == const0_rtx)
625: return \"clrl %0\";
626: if (GET_CODE (operands[2]) == CONST_INT
627: && INTVAL (operands[2]) == -1)
628: return \"mnegl %1,%0\";
629: if (rtx_equal_p (operands[0], operands[1]))
630: return \"divl2 %2,%0\";
631: return \"divl3 %2,%1,%0\";
632: }")
633:
634:
635: ; divsf3 must divide into the fpp accumulator. Flags are not set by
636: ; this instruction, so they are cleared.
637:
638: (define_insn "divsf3"
639: [(set (match_operand:SF 0 "register_operand" "=a")
640: (div:SF (match_operand:SF 1 "register_operand" "0")
641: (match_operand:SF 2 "general_operand" "g")))]
642: ""
643: "*
644: {
645: CC_STATUS_INIT;
646: return \"divf %2\";
647: }")
648:
649:
650: ; divdf3 also must divide into the fpp reg so optimization isn't
651: ; possible. Note that doubles cannot be immediate. The flags here
652: ; are not set correctly so they must be ignored.
653:
654: (define_insn "divdf3"
655: [(set (match_operand:DF 0 "register_operand" "=a")
656: (div:DF (match_operand:DF 1 "register_operand" "0")
657: (match_operand:DF 2 "general_operand" "rm")))]
658: ""
659: "*
660: {
661: CC_STATUS_INIT;
662: return \"divd %2\";
663: }")
664:
665:
666:
667: (define_insn "andsi3"
668: [(set (match_operand:SI 0 "general_operand" "=g")
669: (and:SI (match_operand:SI 1 "general_operand" "g")
670: (match_operand:SI 2 "general_operand" "g")))]
671: ""
672: "*
673: {
674: if (rtx_equal_p (operands[0], operands[1]))
675: return \"andl2 %2,%0\";
676: if (rtx_equal_p (operands[0], operands[2]))
677: return \"andl2 %1,%0\";
678: return \"andl3 %2,%1,%0\";
679: }")
680:
681:
682:
683: (define_insn "andhi3"
684: [(set (match_operand:HI 0 "general_operand" "=g")
685: (and:HI (match_operand:HI 1 "general_operand" "g")
686: (match_operand:HI 2 "general_operand" "g")))]
687: ""
688: "*
689: {
690: if (rtx_equal_p (operands[0], operands[1]))
691: return \"andw2 %2,%0\";
692: if (rtx_equal_p (operands[0], operands[2]))
693: return \"andw2 %1,%0\";
694: return \"andw3 %2,%1,%0\";
695: }")
696:
697:
698: (define_insn "andqi3"
699: [(set (match_operand:QI 0 "general_operand" "=g")
700: (and:QI (match_operand:QI 1 "general_operand" "g")
701: (match_operand:QI 2 "general_operand" "g")))]
702: ""
703: "*
704: {
705: if (rtx_equal_p (operands[0], operands[1]))
706: return \"andb2 %2,%0\";
707: if (rtx_equal_p (operands[0], operands[2]))
708: return \"andb2 %1,%0\";
709: return \"andb3 %2,%1,%0\";
710: }")
711:
712:
713: (define_insn "iorsi3"
714: [(set (match_operand:SI 0 "general_operand" "=g")
715: (ior:SI (match_operand:SI 1 "general_operand" "g")
716: (match_operand:SI 2 "general_operand" "g")))]
717: ""
718: "*
719: {
720: if (rtx_equal_p (operands[0], operands[1]))
721: return \"orl2 %2,%0\";
722: if (rtx_equal_p (operands[0], operands[2]))
723: return \"orl2 %1,%0\";
724: return \"orl3 %2,%1,%0\";
725: }")
726:
727:
728:
729: (define_insn "iorhi3"
730: [(set (match_operand:HI 0 "general_operand" "=g")
731: (ior:HI (match_operand:HI 1 "general_operand" "g")
732: (match_operand:HI 2 "general_operand" "g")))]
733: ""
734: "*
735: {
736: if (rtx_equal_p (operands[0], operands[1]))
737: return \"orw2 %2,%0\";
738: if (rtx_equal_p (operands[0], operands[2]))
739: return \"orw2 %1,%0\";
740: return \"orw3 %2,%1,%0\";
741: }")
742:
743:
744:
745: (define_insn "iorqi3"
746: [(set (match_operand:QI 0 "general_operand" "=g")
747: (ior:QI (match_operand:QI 1 "general_operand" "g")
748: (match_operand:QI 2 "general_operand" "g")))]
749: ""
750: "*
751: {
752: if (rtx_equal_p (operands[0], operands[1]))
753: return \"orb2 %2,%0\";
754: if (rtx_equal_p (operands[0], operands[2]))
755: return \"orb2 %1,%0\";
756: return \"orb3 %2,%1,%0\";
757: }")
758:
759:
760: (define_insn "xorsi3"
761: [(set (match_operand:SI 0 "general_operand" "=g")
762: (xor:SI (match_operand:SI 1 "general_operand" "g")
763: (match_operand:SI 2 "general_operand" "g")))]
764: ""
765: "*
766: {
767: if (rtx_equal_p (operands[0], operands[1]))
768: return \"xorl2 %2,%0\";
769: if (rtx_equal_p (operands[0], operands[2]))
770: return \"xorl2 %1,%0\";
771: return \"xorl3 %2,%1,%0\";
772: }")
773:
774:
775: (define_insn "xorhi3"
776: [(set (match_operand:HI 0 "general_operand" "=g")
777: (xor:HI (match_operand:HI 1 "general_operand" "g")
778: (match_operand:HI 2 "general_operand" "g")))]
779: ""
780: "*
781: {
782: if (rtx_equal_p (operands[0], operands[1]))
783: return \"xorw2 %2,%0\";
784: if (rtx_equal_p (operands[0], operands[2]))
785: return \"xorw2 %1,%0\";
786: return \"xorw3 %2,%1,%0\";
787: }")
788:
789:
790: (define_insn "xorqi3"
791: [(set (match_operand:QI 0 "general_operand" "=g")
792: (xor:QI (match_operand:QI 1 "general_operand" "g")
793: (match_operand:QI 2 "general_operand" "g")))]
794: ""
795: "*
796: {
797: if (rtx_equal_p (operands[0], operands[1]))
798: return \"xorb2 %2,%0\";
799: if (rtx_equal_p (operands[0], operands[2]))
800: return \"xorb2 %1,%0\";
801: return \"xorb3 %2,%1,%0\";
802: }")
803:
804:
805: ; shifts on the tahoe are expensive, try some magic first...
806:
807: (define_insn "ashlsi3"
808: [(set (match_operand:SI 0 "general_operand" "=g")
809: (ashift:SI (match_operand:SI 1 "general_operand" "g")
810: (match_operand:QI 2 "general_operand" "g")))]
811: ""
812: "*
813: {
814: if (GET_CODE(operands[2]) == REG)
815: return \"mull3 ___shtab[%2],%1,%0\";
816: /* if (GET_CODE(operands[2]) == REG)
817: if (rtx_equal_p (operands[0], operands[1]))
818: return \"mull2 ___shtab[%2],%1\";
819: else
820: return \"mull3 ___shtab[%2],%1,%0\"; */
821: if (GET_CODE(operands[1]) == REG)
822: {
823: if (operands[2] == const1_rtx)
824: {
825: CC_STATUS_INIT;
826: return \"movaw 0[%1],%0\";
827: }
828: if (GET_CODE(operands[2]) == CONST_INT && INTVAL(operands[2]) == 2)
829: {
830: CC_STATUS_INIT;
831: return \"moval 0[%1],%0\";
832: }
833: }
834: if (GET_CODE(operands[2]) != CONST_INT || INTVAL(operands[2]) == 1)
835: return \"shal %2,%1,%0\";
836: if (rtx_equal_p (operands[0], operands[1]))
837: return \"mull2 %s2,%1\";
838: else
839: return \"mull3 %s2,%1,%0\";
840: }")
841:
842:
843: (define_insn "ashrsi3"
844: [(set (match_operand:SI 0 "general_operand" "=g")
845: (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
846: (match_operand:QI 2 "general_operand" "g")))]
847: ""
848: "shar %2,%1,%0")
849:
850:
851: ; shifts are very expensive, try some magic first...
852:
853: (define_insn "lshlsi3"
854: [(set (match_operand:SI 0 "general_operand" "=g")
855: (lshift:SI (match_operand:SI 1 "general_operand" "g")
856: (match_operand:QI 2 "general_operand" "g")))]
857: ""
858: "*
859: {
860: if (GET_CODE(operands[2]) == REG)
861: return \"mull3 ___shtab[%2],%1,%0\";
862: /* if (GET_CODE(operands[2]) == REG)
863: if (rtx_equal_p (operands[0], operands[1]))
864: return \"mull2 ___shtab[%2],%1\";
865: else
866: return \"mull3 ___shtab[%2],%1,%0\"; */
867: if (GET_CODE(operands[1]) == REG)
868: {
869: if (operands[2] == const1_rtx)
870: {
871: CC_STATUS_INIT;
872: return \"movaw 0[%1],%0\";
873: }
874: if (GET_CODE(operands[2]) == CONST_INT && INTVAL(operands[2]) == 2)
875: {
876: CC_STATUS_INIT;
877: return \"moval 0[%1],%0\";
878: }
879: }
880: if (GET_CODE(operands[2]) != CONST_INT || INTVAL(operands[2]) == 1)
881: return \"shll %2,%1,%0\";
882: if (rtx_equal_p (operands[0], operands[1]))
883: return \"mull2 %s2,%1\";
884: else
885: return \"mull3 %s2,%1,%0\";
886: }")
887:
888:
889: (define_insn "lshrsi3"
890: [(set (match_operand:SI 0 "general_operand" "=g")
891: (lshiftrt:SI (match_operand:SI 1 "general_operand" "g")
892: (match_operand:QI 2 "general_operand" "g")))]
893: ""
894: "shrl %2,%1,%0")
895:
896:
897: (define_insn "negsi2"
898: [(set (match_operand:SI 0 "general_operand" "=g")
899: (neg:SI (match_operand:SI 1 "general_operand" "g")))]
900: ""
901: "mnegl %1,%0")
902:
903:
904: (define_insn "neghi2"
905: [(set (match_operand:HI 0 "general_operand" "=g")
906: (neg:HI (match_operand:HI 1 "general_operand" "g")))]
907: ""
908: "mnegw %1,%0")
909:
910:
911: (define_insn "negqi2"
912: [(set (match_operand:QI 0 "general_operand" "=g")
913: (neg:QI (match_operand:QI 1 "general_operand" "g")))]
914: ""
915: "mnegb %1,%0")
916:
917:
918: ; negsf2 can only negate the value already in the fpp accumulator.
919: ; The value remains in the fpp accumulator. No flags are set.
920:
921: (define_insn "negsf2"
922: [(set (match_operand:SF 0 "register_operand" "=a,=a")
923: (neg:SF (match_operand:SF 1 "register_operand" "a,g")))]
924: ""
925: "*
926: {
927: CC_STATUS_INIT;
928: switch (which_alternative)
929: {
930: case 0: return \"negf\";
931: case 1: return \"lnf %1\";
932: }
933: }")
934:
935:
936: ; negdf2 can only negate the value already in the fpp accumulator.
937: ; The value remains in the fpp accumulator. No flags are set.
938:
939: (define_insn "negdf2"
940: [(set (match_operand:DF 0 "register_operand" "=a,=a")
941: (neg:DF (match_operand:DF 1 "register_operand" "a,g")))]
942: ""
943: "*
944: {
945: CC_STATUS_INIT;
946: switch (which_alternative)
947: {
948: case 0: return \"negd\";
949: case 1: return \"lnd %1\";
950: }
951: }")
952:
953:
954: ; sqrtsf2 tahoe can calculate the square root of a float in the
955: ; fpp accumulator. The answer remains in the fpp accumulator. No
956: ; flags are set by this function.
957:
958: (define_insn "sqrtsf2"
959: [(set (match_operand:SF 0 "register_operand" "=a")
960: (sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
961: ""
962: "*
963: {
964: CC_STATUS_INIT;
965: return \"sqrtf\";
966: }")
967:
968:
969: ; ffssi2 tahoe instruction gives one less than gcc desired result for
970: ; any given input. So the increment is necessary here.
971:
972: (define_insn "ffssi2"
973: [(set (match_operand:SI 0 "general_operand" "=g")
974: (ffs:SI (match_operand:SI 1 "general_operand" "g")))]
975: ""
976: "*
977: {
978: if (push_operand(operands[0], SImode))
979: return \"ffs %1,%0\;incl (sp)\";
980: return \"ffs %1,%0\;incl %0\";
981: }")
982:
983:
984: (define_insn "one_cmplsi2"
985: [(set (match_operand:SI 0 "general_operand" "=g")
986: (not:SI (match_operand:SI 1 "general_operand" "g")))]
987: ""
988: "mcoml %1,%0")
989:
990:
991: (define_insn "one_cmplhi2"
992: [(set (match_operand:HI 0 "general_operand" "=g")
993: (not:HI (match_operand:HI 1 "general_operand" "g")))]
994: ""
995: "mcomw %1,%0")
996:
997:
998: (define_insn "one_cmplqi2"
999: [(set (match_operand:QI 0 "general_operand" "=g")
1000: (not:QI (match_operand:QI 1 "general_operand" "g")))]
1001: ""
1002: "mcomb %1,%0")
1003:
1004:
1005: ; cmpsi works fine, but due to microcode problems, the tahoe doesn't
1006: ; properly compare hi's and qi's. Leaving them out seems to be acceptable
1007: ; to the compiler, so they were left out. Compares of the stack are
1008: ; possible, though.
1009:
1010: ; There are optimized cases possible, however. These follow first.
1011:
1012: (define_insn ""
1013: [(set (cc0)
1014: (compare (sign_extend:SI (match_operand:HI 0 "memory_operand" "m"))
1015: (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))))]
1016: ""
1017: "cmpw %0,%1")
1018:
1019: (define_insn ""
1020: [(set (cc0)
1021: (compare (match_operand:SI 0 "nonmemory_operand" "ri")
1022: (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))))]
1023: ""
1024: "cmpw %0,%1")
1025:
1026: (define_insn ""
1027: [(set (cc0)
1028: (compare (sign_extend:SI (match_operand:HI 0 "memory_operand" "m"))
1029: (match_operand:SI 1 "nonmemory_operand" "ri")))]
1030: ""
1031: "cmpw %0,%1")
1032:
1033: ; zero-extended compares give the same result as sign-extended compares, if
1034: ; the compare is unsigned. Just see: if both operands are <65536 they are the
1035: ; same in both cases. If both are >=65536 the you effectively compare x+D
1036: ; with y+D, where D=2**32-2**16, so the result is the same. if x<65536 and
1037: ; y>=65536 then you compare x with y+D, and in both cases the result is x<y.
1038:
1039: (define_insn ""
1040: [(set (cc0)
1041: (compare (zero_extend:SI (match_operand:HI 0 "memory_operand" "m"))
1042: (zero_extend:SI (match_operand:HI 1 "memory_operand" "m"))))]
1043: "tahoe_cmp_check (insn, operands[0], 0)"
1044: "cmpw %0,%1")
1045:
1046: (define_insn ""
1047: [(set (cc0)
1048: (compare (zero_extend:SI (match_operand:HI 0 "memory_operand" "m"))
1049: (match_operand:SI 1 "immediate_operand" "i")))]
1050: "tahoe_cmp_check(insn, operands[1], 65535)"
1051: "*
1052: {
1053: if (INTVAL (operands[1]) > 32767)
1054: operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) + 0xffff0000);
1055: return \"cmpw %0,%1\";
1056: }")
1057:
1058:
1059: (define_insn ""
1060: [(set (cc0)
1061: (compare (sign_extend:SI (match_operand:QI 0 "memory_operand" "m"))
1062: (sign_extend:SI (match_operand:QI 1 "memory_operand" "m"))))]
1063: ""
1064: "cmpb %0,%1")
1065:
1066: (define_insn ""
1067: [(set (cc0)
1068: (compare (match_operand:SI 0 "nonmemory_operand" "ri")
1069: (sign_extend:SI (match_operand:QI 1 "memory_operand" "m"))))]
1070: ""
1071: "cmpb %0,%1")
1072:
1073: (define_insn ""
1074: [(set (cc0)
1075: (compare (sign_extend:SI (match_operand:QI 0 "memory_operand" "m"))
1076: (match_operand:SI 1 "nonmemory_operand" "ri")))]
1077: ""
1078: "cmpb %0,%1")
1079:
1080: ; zero-extended compares give the same result as sign-extended compares, if
1081: ; the compare is unsigned. Just see: if both operands are <128 they are the
1082: ; same in both cases. If both are >=128 the you effectively compare x+D
1083: ; with y+D, where D=2**32-2**8, so the result is the same. if x<128 and
1084: ; y>=128 then you compare x with y+D, and in both cases the result is x<y.
1085:
1086: (define_insn ""
1087: [(set (cc0)
1088: (compare (zero_extend:SI (match_operand:QI 0 "memory_operand" "m"))
1089: (zero_extend:SI (match_operand:QI 1 "memory_operand" "m"))))]
1090: "tahoe_cmp_check (insn, operands[0], 0)"
1091: "cmpb %0,%1")
1092:
1093: (define_insn ""
1094: [(set (cc0)
1095: (compare (zero_extend:SI (match_operand:QI 0 "memory_operand" "m"))
1096: (match_operand:SI 1 "immediate_operand" "i")))]
1097: "tahoe_cmp_check(insn, operands[1], 255)"
1098: "*
1099: {
1100: if (INTVAL (operands[1]) > 127)
1101: operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) + 0xffffff00);
1102: return \"cmpb %0,%1\";
1103: }")
1104:
1105:
1106: (define_insn "cmpsi"
1107: [(set (cc0)
1108: (compare (match_operand:SI 0 "nonimmediate_operand" "g")
1109: (match_operand:SI 1 "general_operand" "g")))]
1110: ""
1111: "cmpl %0,%1")
1112:
1113:
1114: ; cmpsf similar to vax, but first operand is expected to be in the
1115: ; fpp accumulator.
1116:
1117: (define_insn "cmpsf"
1118: [(set (cc0)
1119: (compare (match_operand:SF 0 "general_operand" "a,g")
1120: (match_operand:SF 1 "general_operand" "g,g")))]
1121: ""
1122: "*
1123: {
1124: switch (which_alternative)
1125: {
1126: case 0: return \"cmpf %1\";
1127: case 1: return \"cmpf2 %0,%1\";
1128: }
1129: }")
1130:
1131:
1132: ; cmpdf similar to vax, but first operand is expected to be in the
1133: ; fpp accumulator. Immediate doubles not allowed.
1134:
1135: (define_insn "cmpdf"
1136: [(set (cc0)
1137: (compare (match_operand:DF 0 "general_operand" "a,rm")
1138: (match_operand:DF 1 "general_operand" "rm,rm")))]
1139: ""
1140: "*
1141: {
1142: switch (which_alternative)
1143: {
1144: case 0: return \"cmpd %1\";
1145: case 1: return \"cmpd2 %0,%1\";
1146: }
1147: }")
1148:
1149: ;; We don't want to allow a constant operand for test insns because
1150: ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
1151: ;; be folded while optimizing anyway.
1152:
1153: (define_insn "tstsi"
1154: [(set (cc0)
1155: (match_operand:SI 0 "nonimmediate_operand" "g"))]
1156: ""
1157: "tstl %0")
1158:
1159:
1160: ; small tests from memory are normal, but testing from registers doesn't
1161: ; expand the data properly. So test in this case does a convert and tests
1162: ; the new register data from the stack.
1163:
1164: ; First some special cases that do work
1165:
1166:
1167: (define_insn ""
1168: [(set (cc0)
1169: (sign_extend:SI (match_operand:HI 0 "memory_operand" "m")))]
1170: ""
1171: "tstw %0")
1172:
1173: (define_insn ""
1174: [(set (cc0)
1175: (zero_extend:SI (match_operand:HI 0 "memory_operand" "m")))]
1176: "tahoe_cmp_check (insn, operands[0], 0)"
1177: "tstw %0")
1178:
1179:
1180: (define_insn "tsthi"
1181: [(set (cc0)
1182: (match_operand:HI 0 "extendable_operand" "m,!r"))]
1183: "GET_MODE (operands[0]) != VOIDmode"
1184: "*
1185: {
1186: rtx xoperands[2];
1187: extern rtx tahoe_reg_conversion_loc;
1188: switch (which_alternative)
1189: {
1190: case 0:
1191: return \"tstw %0\";
1192: case 1:
1193: xoperands[0] = operands[0];
1194: xoperands[1] = tahoe_reg_conversion_loc;
1195: output_asm_insn (\"movl %0,%1\", xoperands);
1196: xoperands[1] = plus_constant (XEXP (tahoe_reg_conversion_loc, 0), 2);
1197: output_asm_insn (\"tstw %a1\", xoperands);
1198: return \"\";
1199: }
1200: }")
1201:
1202:
1203: (define_insn ""
1204: [(set (cc0)
1205: (sign_extend:SI (match_operand:QI 0 "memory_operand" "m")))]
1206: ""
1207: "tstb %0")
1208:
1209: (define_insn ""
1210: [(set (cc0)
1211: (zero_extend:SI (match_operand:QI 0 "memory_operand" "m")))]
1212: "tahoe_cmp_check (insn, operands[0], 0)"
1213: "tstb %0")
1214:
1215:
1216: (define_insn "tstqi"
1217: [(set (cc0)
1218: (match_operand:QI 0 "extendable_operand" "m,!r"))]
1219: "GET_MODE (operands[0]) != VOIDmode"
1220: "*
1221: {
1222: rtx xoperands[2];
1223: extern rtx tahoe_reg_conversion_loc;
1224: switch (which_alternative)
1225: {
1226: case 0:
1227: return \"tstb %0\";
1228: case 1:
1229: xoperands[0] = operands[0];
1230: xoperands[1] = tahoe_reg_conversion_loc;
1231: output_asm_insn (\"movl %0,%1\", xoperands);
1232: xoperands[1] = plus_constant (XEXP (tahoe_reg_conversion_loc, 0), 3);
1233: output_asm_insn (\"tstb %a1\", xoperands);
1234: return \"\";
1235: }
1236: }")
1237:
1238: ; tstsf compares a given value to a value already in the fpp accumulator.
1239: ; No flags are set by this so ignore them.
1240:
1241: (define_insn "tstsf"
1242: [(set (cc0)
1243: (match_operand:SF 0 "register_operand" "a"))]
1244: ""
1245: "tstf")
1246:
1247:
1248: ; tstdf compares a given value to a value already in the fpp accumulator.
1249: ; immediate doubles not allowed. Flags are ignored after this.
1250:
1251: (define_insn "tstdf"
1252: [(set (cc0)
1253: (match_operand:DF 0 "register_operand" "a"))]
1254: ""
1255: "tstd")
1256:
1257:
1258:
1259: ; movstrhi tahoe instruction does not load registers by itself like
1260: ; the vax counterpart does. registers 0-2 must be primed by hand.
1261: ; we have loaded the registers in the order: dst, src, count.
1262:
1263: (define_insn "movstrhi"
1264: [(set (match_operand:BLK 0 "general_operand" "p")
1265: (match_operand:BLK 1 "general_operand" "p"))
1266: (use (match_operand:HI 2 "general_operand" "g"))
1267: (clobber (reg:SI 0))
1268: (clobber (reg:SI 1))
1269: (clobber (reg:SI 2))]
1270: ""
1271: "movab %0,r1\;movab %1,r0\;movl %2,r2\;movblk")
1272:
1273:
1274: ; floatsisf2 on tahoe converts the long from reg/mem into the fpp
1275: ; accumulator. There are no hi and qi counterparts. Flags are not
1276: ; set correctly here.
1277:
1278: (define_insn "floatsisf2"
1279: [(set (match_operand:SF 0 "register_operand" "=a")
1280: (float:SF (match_operand:SI 1 "general_operand" "g")))]
1281: ""
1282: "*
1283: {
1284: CC_STATUS_INIT;
1285: return \"cvlf %1\";
1286: }")
1287:
1288:
1289: ; floatsidf2 on tahoe converts the long from reg/mem into the fpp
1290: ; accumulator. There are no hi and qi counterparts. Flags are not
1291: ; set correctly here.
1292:
1293: (define_insn "floatsidf2"
1294: [(set (match_operand:DF 0 "register_operand" "=a")
1295: (float:DF (match_operand:SI 1 "general_operand" "g")))]
1296: ""
1297: "*
1298: {
1299: CC_STATUS_INIT;
1300: return \"cvld %1\";
1301: }")
1302:
1303:
1304: ; fix_truncsfsi2 to convert a float to long, tahoe must have the float
1305: ; in the fpp accumulator. Flags are not set here.
1306:
1307: (define_insn "fix_truncsfsi2"
1308: [(set (match_operand:SI 0 "general_operand" "=g")
1309: (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "a"))))]
1310: ""
1311: "*
1312: {
1313: CC_STATUS_INIT;
1314: return \"cvfl %0\";
1315: }")
1316:
1317:
1318: ; fix_truncsfsi2 to convert a double to long, tahoe must have the double
1319: ; in the fpp accumulator. Flags are not set here.
1320:
1321: (define_insn "fix_truncdfsi2"
1322: [(set (match_operand:SI 0 "general_operand" "=g")
1323: (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "a"))))]
1324: ""
1325: "*
1326: {
1327: CC_STATUS_INIT;
1328: return \"cvdl %0\";
1329: }")
1330:
1331:
1332: (define_insn "truncsihi2"
1333: [(set (match_operand:HI 0 "general_operand" "=g")
1334: (truncate:HI (match_operand:SI 1 "general_operand" "g")))]
1335: ""
1336: "cvtlw %1,%0")
1337:
1338:
1339: (define_insn "truncsiqi2"
1340: [(set (match_operand:QI 0 "general_operand" "=g")
1341: (truncate:QI (match_operand:SI 1 "general_operand" "g")))]
1342: ""
1343: "cvtlb %1,%0")
1344:
1345:
1346: (define_insn "trunchiqi2"
1347: [(set (match_operand:QI 0 "general_operand" "=g")
1348: (truncate:QI (match_operand:HI 1 "general_operand" "g")))]
1349: ""
1350: "cvtwb %1,%0")
1351:
1352:
1353: ; The fpp related instructions don't set flags, so ignore them
1354: ; after this instruction.
1355:
1356: (define_insn "truncdfsf2"
1357: [(set (match_operand:SF 0 "register_operand" "=a")
1358: (float_truncate:SF (match_operand:DF 1 "register_operand" "0")))]
1359: ""
1360: "*
1361: {
1362: CC_STATUS_INIT;
1363: return \"cvdf\";
1364: }")
1365:
1366:
1367: ; This monster is to cover for the Tahoe's nasty habit of not extending
1368: ; a number if the source is in a register. (It just moves it!) Case 0 is
1369: ; a normal extend from memory. Case 1 does the extension from the top of
1370: ; the stack. Extension from the stack doesn't set the flags right since
1371: ; the moval changes them.
1372:
1373: (define_insn "extendhisi2"
1374: [(set (match_operand:SI 0 "general_operand" "=g,?=g")
1375: (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
1376: ""
1377: "*
1378: {
1379: switch (which_alternative)
1380: {
1381: case 0:
1382: return \"cvtwl %1,%0\";
1383: case 1:
1384: if (push_operand (operands[0], SImode))
1385: return \"pushl %1\;cvtwl 2(sp),(sp)\";
1386: else
1387: {
1388: CC_STATUS_INIT;
1389: return \"pushl %1\;cvtwl 2(sp),%0\;moval 4(sp),sp\";
1390: }
1391: }
1392: }")
1393:
1394: ; This monster is to cover for the Tahoe's nasty habit of not extending
1395: ; a number if the source is in a register. (It just moves it!) Case 0 is
1396: ; a normal extend from memory. Case 1 does the extension from the top of
1397: ; the stack. Extension from the stack doesn't set the flags right since
1398: ; the moval changes them.
1399:
1400: (define_insn "extendqisi2"
1401: [(set (match_operand:SI 0 "general_operand" "=g,?=g")
1402: (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m,r")))]
1403: ""
1404: "*
1405: {
1406: switch (which_alternative)
1407: {
1408: case 0:
1409: return \"cvtbl %1,%0\";
1410: case 1:
1411: if (push_operand (operands[0], SImode))
1412: return \"pushl %1\;cvtbl 3(sp),(sp)\";
1413: else
1414: {
1415: CC_STATUS_INIT;
1416: return \"pushl %1\;cvtbl 3(sp),%0\;moval 4(sp),sp\";
1417: }
1418: }
1419: }")
1420:
1421:
1422: ; This monster is to cover for the Tahoe's nasty habit of not extending
1423: ; a number if the source is in a register. (It just moves it!) Case 0 is
1424: ; a normal extend from memory. Case 1 does the extension from the top of
1425: ; the stack. Extension from the stack doesn't set the flags right since
1426: ; the moval changes them.
1427:
1428: (define_insn "extendqihi2"
1429: [(set (match_operand:HI 0 "general_operand" "=g,?=g")
1430: (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m,r")))]
1431: ""
1432: "*
1433: {
1434: switch (which_alternative)
1435: {
1436: case 0:
1437: return \"cvtbw %1,%0\";
1438: case 1:
1439: if (push_operand (operands[0], SImode))
1440: return \"pushl %1\;cvtbw 3(sp),(sp)\";
1441: else
1442: {
1443: CC_STATUS_INIT;
1444: return \"pushl %1\;cvtbw 3(sp),%0\;moval 4(sp),sp\";
1445: }
1446: }
1447: }")
1448:
1449:
1450: ; extendsfdf2 tahoe uses the fpp accumulator to do the extension.
1451: ; It takes a float and loads it up directly as a double.
1452:
1453: (define_insn "extendsfdf2"
1454: [(set (match_operand:DF 0 "register_operand" "=a")
1455: (float_extend:DF (match_operand:SF 1 "general_operand" "g")))]
1456: ""
1457: "*
1458: {
1459: CC_STATUS_INIT;
1460: return \"ldfd %1\";
1461: }")
1462:
1463:
1464: ; movz works fine from memory but not from register for the same reasons
1465: ; the cvt instructions don't work right. So we use the normal instruction
1466: ; from memory and we use an and to simulate it from register. This is faster
1467: ; than pulling it off the stack.
1468:
1469:
1470: (define_insn "zero_extendhisi2"
1471: [(set (match_operand:SI 0 "general_operand" "=g,?=g")
1472: (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
1473: ""
1474: "*
1475: {
1476: switch (which_alternative)
1477: {
1478: case 0: return \"movzwl %1,%0\";
1479: case 1: return \"andl3 $0xffff,%1,%0\";
1480: }
1481: }")
1482:
1483: ; movz works fine from memory but not from register for the same reasons
1484: ; the cvt instructions don't work right. So we use the normal instruction
1485: ; from memory and we use an and to simulate it from register. This is faster
1486: ; than pulling it off the stack.
1487:
1488: (define_insn "zero_extendqihi2"
1489: [(set (match_operand:HI 0 "general_operand" "=g,?=g")
1490: (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m,r")))]
1491: ""
1492: "*
1493: {
1494: switch (which_alternative)
1495: {
1496: case 0: return \"movzbw %1,%0\";
1497: case 1: return \"andw3 $0xff,%1,%0\";
1498: }
1499: }")
1500:
1501:
1502: ; movz works fine from memory but not from register for the same reasons
1503: ; the cvt instructions don't work right. So we use the normal instruction
1504: ; from memory and we use an and to simulate it from register. This is faster
1505: ; than pulling it off the stack.
1506:
1507: (define_insn "zero_extendqisi2"
1508: [(set (match_operand:SI 0 "general_operand" "=g,?=g")
1509: (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m,r")))]
1510: ""
1511: "*
1512: {
1513: switch (which_alternative)
1514: {
1515: case 0: return \"movzbl %1,%0\";
1516: case 1: return \"andl3 $0xff,%1,%0\";
1517: }
1518: }")
1519:
1520:
1521: (define_insn "beq"
1522: [(set (pc)
1523: (if_then_else (eq (cc0)
1524: (const_int 0))
1525: (label_ref (match_operand 0 "" ""))
1526: (pc)))]
1527: ""
1528: "jeql %l0")
1529:
1530:
1531: (define_insn "bne"
1532: [(set (pc)
1533: (if_then_else (ne (cc0)
1534: (const_int 0))
1535: (label_ref (match_operand 0 "" ""))
1536: (pc)))]
1537: ""
1538: "jneq %l0")
1539:
1540:
1541: (define_insn "bgt"
1542: [(set (pc)
1543: (if_then_else (gt (cc0)
1544: (const_int 0))
1545: (label_ref (match_operand 0 "" ""))
1546: (pc)))]
1547: ""
1548: "jgtr %l0")
1549:
1550:
1551: (define_insn "bgtu"
1552: [(set (pc)
1553: (if_then_else (gtu (cc0)
1554: (const_int 0))
1555: (label_ref (match_operand 0 "" ""))
1556: (pc)))]
1557: ""
1558: "jgtru %l0")
1559:
1560:
1561: (define_insn "blt"
1562: [(set (pc)
1563: (if_then_else (lt (cc0)
1564: (const_int 0))
1565: (label_ref (match_operand 0 "" ""))
1566: (pc)))]
1567: ""
1568: "jlss %l0")
1569:
1570:
1571: (define_insn "bltu"
1572: [(set (pc)
1573: (if_then_else (ltu (cc0)
1574: (const_int 0))
1575: (label_ref (match_operand 0 "" ""))
1576: (pc)))]
1577: ""
1578: "jlssu %l0")
1579:
1580:
1581: (define_insn "bge"
1582: [(set (pc)
1583: (if_then_else (ge (cc0)
1584: (const_int 0))
1585: (label_ref (match_operand 0 "" ""))
1586: (pc)))]
1587: ""
1588: "jgeq %l0")
1589:
1590:
1591: (define_insn "bgeu"
1592: [(set (pc)
1593: (if_then_else (geu (cc0)
1594: (const_int 0))
1595: (label_ref (match_operand 0 "" ""))
1596: (pc)))]
1597: ""
1598: "jgequ %l0")
1599:
1600:
1601: (define_insn "ble"
1602: [(set (pc)
1603: (if_then_else (le (cc0)
1604: (const_int 0))
1605: (label_ref (match_operand 0 "" ""))
1606: (pc)))]
1607: ""
1608: "jleq %l0")
1609:
1610:
1611: (define_insn "bleu"
1612: [(set (pc)
1613: (if_then_else (leu (cc0)
1614: (const_int 0))
1615: (label_ref (match_operand 0 "" ""))
1616: (pc)))]
1617: ""
1618: "jlequ %l0")
1619:
1620:
1621: ; gcc does not account for register mask/argc longword. Thus the number
1622: ; for the call = number bytes for args + 4
1623:
1624: (define_insn "call"
1625: [(call (match_operand:QI 0 "memory_operand" "m")
1626: (match_operand:QI 1 "general_operand" "g"))]
1627: ""
1628: "*
1629: {
1630: operands[1] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[1]) + 4));
1631: if (GET_CODE(operands[0]) == MEM
1632: && CONSTANT_ADDRESS_P (XEXP(operands[0], 0))
1633: && INTVAL (operands[1]) < 64)
1634: return \"callf %1,%0\"; /* this is much faster */
1635: return \"calls %1,%0\";
1636: }")
1637:
1638: ; gcc does not account for register mask/argc longword. Thus the number
1639: ; for the call = number bytes for args + 4
1640:
1641: (define_insn "call_value"
1642: [(set (match_operand 0 "" "=g")
1643: (call (match_operand:QI 1 "memory_operand" "m")
1644: (match_operand:QI 2 "general_operand" "g")))]
1645: ""
1646: "*
1647: {
1648: operands[2] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[2]) + 4));
1649: if (GET_CODE(operands[1]) == MEM
1650: && CONSTANT_ADDRESS_P (XEXP(operands[1], 0))
1651: && INTVAL (operands[2]) < 64)
1652: return \"callf %2,%1\"; /* this is much faster */
1653: return \"calls %2,%1\";
1654: }")
1655:
1656:
1657: (define_insn "return"
1658: [(return)]
1659: ""
1660: "ret")
1661:
1662: (define_insn "nop"
1663: [(const_int 0)]
1664: ""
1665: "nop")
1666:
1667: ; casesi this code extracted from the vax code. The instructions are
1668: ; very similar. Tahoe requires that the table be word aligned. GCC
1669: ; places the table immediately after, thus the alignment directive.
1670:
1671: (define_insn "casesi"
1672: [(set (pc)
1673: (if_then_else (le (minus:SI (match_operand:SI 0 "general_operand" "g")
1674: (match_operand:SI 1 "general_operand" "g"))
1675: (match_operand:SI 2 "general_operand" "g"))
1676: (plus:SI (sign_extend:SI
1677: (mem:HI (plus:SI (pc)
1678: (minus:SI (match_dup 0)
1679: (match_dup 1)))))
1680: (label_ref:SI (match_operand 3 "" "")))
1681: (pc)))]
1682: ""
1683: "casel %0,%1,%2\;.align %@")
1684:
1685:
1686: (define_insn "jump"
1687: [(set (pc)
1688: (label_ref (match_operand 0 "" "")))]
1689: ""
1690: "jbr %l0")
1691:
1692:
1693: ;; This is the list of all the non-standard insn patterns
1694:
1695:
1696: ; This is used to access the address of a byte. This is similar to
1697: ; movqi, but the second operand had to be "address_operand" type, so
1698: ; it had to be an unnamed one.
1699:
1700: (define_insn ""
1701: [(set (match_operand:SI 0 "general_operand" "=g")
1702: (match_operand:QI 1 "address_operand" "p"))]
1703: ""
1704: "*
1705: {
1706: if (push_operand (operands[0], SImode))
1707: return \"pushab %a1\";
1708: return \"movab %a1,%0\";
1709: }")
1710:
1711: ; This is used to access the address of a word. This is similar to
1712: ; movhi, but the second operand had to be "address_operand" type, so
1713: ; it had to be an unnamed one.
1714:
1715: (define_insn ""
1716: [(set (match_operand:SI 0 "general_operand" "=g")
1717: (match_operand:HI 1 "address_operand" "p"))]
1718: ""
1719: "*
1720: {
1721: if (push_operand (operands[0], SImode))
1722: return \"pushaw %a1\";
1723: return \"movaw %a1,%0\";
1724: }")
1725:
1726: ; This is used to access the address of a long. This is similar to
1727: ; movsi, but the second operand had to be "address_operand" type, so
1728: ; it had to be an unnamed one.
1729:
1730: (define_insn ""
1731: [(set (match_operand:SI 0 "general_operand" "=g")
1732: (match_operand:SI 1 "address_operand" "p"))]
1733: ""
1734: "*
1735: {
1736: if (push_operand (operands[0], SImode))
1737: return \"pushal %a1\";
1738: return \"moval %a1,%0\";
1739: }")
1740:
1741:
1742: ; bit test longword instruction, same as vax
1743:
1744: (define_insn ""
1745: [(set (cc0)
1746: (and:SI (match_operand:SI 0 "general_operand" "g")
1747: (match_operand:SI 1 "general_operand" "g")))]
1748: ""
1749: "bitl %0,%1")
1750:
1751:
1752: ; bit test word instructions, same as vax
1753:
1754: (define_insn ""
1755: [(set (cc0)
1756: (and:HI (match_operand:HI 0 "general_operand" "g")
1757: (match_operand:HI 1 "general_operand" "g")))]
1758: ""
1759: "bitw %0,%1")
1760:
1761:
1762: ; bit test instructions, same as vax
1763:
1764: (define_insn ""
1765: [(set (cc0)
1766: (and:QI (match_operand:QI 0 "general_operand" "g")
1767: (match_operand:QI 1 "general_operand" "g")))]
1768: ""
1769: "bitb %0,%1")
1770:
1771:
1772: ; bne counterpart. in case gcc reverses the conditional.
1773:
1774: (define_insn ""
1775: [(set (pc)
1776: (if_then_else (eq (cc0)
1777: (const_int 0))
1778: (pc)
1779: (label_ref (match_operand 0 "" ""))))]
1780: ""
1781: "jneq %l0")
1782:
1783:
1784: ; beq counterpart. in case gcc reverses the conditional.
1785:
1786: (define_insn ""
1787: [(set (pc)
1788: (if_then_else (ne (cc0)
1789: (const_int 0))
1790: (pc)
1791: (label_ref (match_operand 0 "" ""))))]
1792: ""
1793: "jeql %l0")
1794:
1795:
1796: ; ble counterpart. in case gcc reverses the conditional.
1797:
1798: (define_insn ""
1799: [(set (pc)
1800: (if_then_else (gt (cc0)
1801: (const_int 0))
1802: (pc)
1803: (label_ref (match_operand 0 "" ""))))]
1804: ""
1805: "jleq %l0")
1806:
1807:
1808: ; bleu counterpart. in case gcc reverses the conditional.
1809:
1810: (define_insn ""
1811: [(set (pc)
1812: (if_then_else (gtu (cc0)
1813: (const_int 0))
1814: (pc)
1815: (label_ref (match_operand 0 "" ""))))]
1816: ""
1817: "jlequ %l0")
1818:
1819:
1820: ; bge counterpart. in case gcc reverses the conditional.
1821:
1822: (define_insn ""
1823: [(set (pc)
1824: (if_then_else (lt (cc0)
1825: (const_int 0))
1826: (pc)
1827: (label_ref (match_operand 0 "" ""))))]
1828: ""
1829: "jgeq %l0")
1830:
1831:
1832: ; bgeu counterpart. in case gcc reverses the conditional.
1833:
1834: (define_insn ""
1835: [(set (pc)
1836: (if_then_else (ltu (cc0)
1837: (const_int 0))
1838: (pc)
1839: (label_ref (match_operand 0 "" ""))))]
1840: ""
1841: "jgequ %l0")
1842:
1843:
1844: ; blt counterpart. in case gcc reverses the conditional.
1845:
1846: (define_insn ""
1847: [(set (pc)
1848: (if_then_else (ge (cc0)
1849: (const_int 0))
1850: (pc)
1851: (label_ref (match_operand 0 "" ""))))]
1852: ""
1853: "jlss %l0")
1854:
1855:
1856: ; bltu counterpart. in case gcc reverses the conditional.
1857:
1858: (define_insn ""
1859: [(set (pc)
1860: (if_then_else (geu (cc0)
1861: (const_int 0))
1862: (pc)
1863: (label_ref (match_operand 0 "" ""))))]
1864: ""
1865: "jlssu %l0")
1866:
1867:
1868: ; bgt counterpart. in case gcc reverses the conditional.
1869:
1870: (define_insn ""
1871: [(set (pc)
1872: (if_then_else (le (cc0)
1873: (const_int 0))
1874: (pc)
1875: (label_ref (match_operand 0 "" ""))))]
1876: ""
1877: "jgtr %l0")
1878:
1879:
1880: ; bgtu counterpart. in case gcc reverses the conditional.
1881:
1882: (define_insn ""
1883: [(set (pc)
1884: (if_then_else (leu (cc0)
1885: (const_int 0))
1886: (pc)
1887: (label_ref (match_operand 0 "" ""))))]
1888: ""
1889: "jgtru %l0")
1890:
1891:
1892: ; casesi alternate form as found in vax code. this form is to
1893: ; compensate for the table's offset being no distance (0 displacement)
1894:
1895: (define_insn ""
1896: [(set (pc)
1897: (if_then_else (le (match_operand:SI 0 "general_operand" "g")
1898: (match_operand:SI 1 "general_operand" "g"))
1899: (plus:SI (sign_extend:SI
1900: (mem:HI (plus:SI (pc)
1901: (minus:SI (match_dup 0)
1902: (const_int 0)))))
1903: (label_ref:SI (match_operand 3 "" "")))
1904: (pc)))]
1905: ""
1906: "casel %0,$0,%1\;.align %@")
1907:
1908:
1909: ; casesi alternate form as found in vax code. another form to
1910: ; compensate for the table's offset being no distance (0 displacement)
1911:
1912: (define_insn ""
1913: [(set (pc)
1914: (if_then_else (le (match_operand:SI 0 "general_operand" "g")
1915: (match_operand:SI 1 "general_operand" "g"))
1916: (plus:SI (sign_extend:SI
1917: (mem:HI (plus:SI (pc)
1918: (match_dup 0))))
1919: (label_ref:SI (match_operand 3 "" "")))
1920: (pc)))]
1921: ""
1922: "casel %0,$0,%1 \;.align %@")
1923:
1924: (define_insn ""
1925: [(set (pc)
1926: (if_then_else
1927: (lt (plus:SI (match_operand:SI 0 "general_operand" "+g")
1928: (const_int 1))
1929: (match_operand:SI 1 "general_operand" "g"))
1930: (label_ref (match_operand 2 "" ""))
1931: (pc)))
1932: (set (match_dup 0)
1933: (plus:SI (match_dup 0)
1934: (const_int 1)))]
1935: ""
1936: "aoblss %1,%0,%l2")
1937:
1938: (define_insn ""
1939: [(set (pc)
1940: (if_then_else
1941: (le (plus:SI (match_operand:SI 0 "general_operand" "+g")
1942: (const_int 1))
1943: (match_operand:SI 1 "general_operand" "g"))
1944: (label_ref (match_operand 2 "" ""))
1945: (pc)))
1946: (set (match_dup 0)
1947: (plus:SI (match_dup 0)
1948: (const_int 1)))]
1949: ""
1950: "aobleq %1,%0,%l2")
1951:
1952: (define_insn ""
1953: [(set (pc)
1954: (if_then_else
1955: (ge (plus:SI (match_operand:SI 0 "general_operand" "+g")
1956: (const_int 1))
1957: (match_operand:SI 1 "general_operand" "g"))
1958: (pc)
1959: (label_ref (match_operand 2 "" ""))))
1960: (set (match_dup 0)
1961: (plus:SI (match_dup 0)
1962: (const_int 1)))]
1963: ""
1964: "aoblss %1,%0,%l2")
1965:
1966: (define_insn ""
1967: [(set (pc)
1968: (if_then_else
1969: (gt (plus:SI (match_operand:SI 0 "general_operand" "+g")
1970: (const_int 1))
1971: (match_operand:SI 1 "general_operand" "g"))
1972: (pc)
1973: (label_ref (match_operand 2 "" ""))))
1974: (set (match_dup 0)
1975: (plus:SI (match_dup 0)
1976: (const_int 1)))]
1977: ""
1978: "aobleq %1,%0,%l2")
1979:
1980: ; bbs/bbc
1981:
1982: (define_insn ""
1983: [(set (pc)
1984: (if_then_else
1985: (ne (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "rm")
1986: (const_int 1)
1987: (subreg:QI (match_operand:SI 1 "general_operand" "g") 0))
1988: (const_int 0))
1989: (label_ref (match_operand 2 "" ""))
1990: (pc)))]
1991: ""
1992: "bbs %1,%0,%l2")
1993:
1994: (define_insn ""
1995: [(set (pc)
1996: (if_then_else
1997: (eq (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "rm")
1998: (const_int 1)
1999: (subreg:QI (match_operand:SI 1 "general_operand" "g") 0))
2000: (const_int 0))
2001: (label_ref (match_operand 2 "" ""))
2002: (pc)))]
2003: ""
2004: "bbc %1,%0,%l2")
2005:
2006: (define_insn ""
2007: [(set (pc)
2008: (if_then_else
2009: (ne (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "rm")
2010: (const_int 1)
2011: (subreg:QI (match_operand:SI 1 "general_operand" "g") 0))
2012: (const_int 0))
2013: (pc)
2014: (label_ref (match_operand 2 "" ""))))]
2015: ""
2016: "bbc %1,%0,%l2")
2017:
2018: (define_insn ""
2019: [(set (pc)
2020: (if_then_else
2021: (eq (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "rm")
2022: (const_int 1)
2023: (subreg:QI (match_operand:SI 1 "general_operand" "g") 0))
2024: (const_int 0))
2025: (pc)
2026: (label_ref (match_operand 2 "" ""))))]
2027: ""
2028: "bbs %1,%0,%l2")
2029:
2030: ; if the shift count is a byte in a register we can use it as a long
2031:
2032: (define_insn ""
2033: [(set (pc)
2034: (if_then_else
2035: (ne (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "rm")
2036: (const_int 1)
2037: (match_operand:QI 1 "register_operand" "r"))
2038: (const_int 0))
2039: (label_ref (match_operand 2 "" ""))
2040: (pc)))]
2041: ""
2042: "bbs %1,%0,%l2")
2043:
2044: (define_insn ""
2045: [(set (pc)
2046: (if_then_else
2047: (eq (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "rm")
2048: (const_int 1)
2049: (match_operand:QI 1 "register_operand" "r"))
2050: (const_int 0))
2051: (label_ref (match_operand 2 "" ""))
2052: (pc)))]
2053: ""
2054: "bbc %1,%0,%l2")
2055:
2056: (define_insn ""
2057: [(set (pc)
2058: (if_then_else
2059: (ne (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "rm")
2060: (const_int 1)
2061: (match_operand:QI 1 "register_operand" "r"))
2062: (const_int 0))
2063: (pc)
2064: (label_ref (match_operand 2 "" ""))))]
2065: ""
2066: "bbc %1,%0,%l2")
2067:
2068: (define_insn ""
2069: [(set (pc)
2070: (if_then_else
2071: (eq (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "rm")
2072: (const_int 1)
2073: (match_operand:QI 1 "register_operand" "r"))
2074: (const_int 0))
2075: (pc)
2076: (label_ref (match_operand 2 "" ""))))]
2077: ""
2078: "bbs %1,%0,%l2")
2079:
2080: ; special case for 1 << constant. We don't do these because they are slower
2081: ; than the bitl instruction
2082:
2083: ;(define_insn ""
2084: ; [(set (pc)
2085: ; (if_then_else
2086: ; (ne (and:SI (match_operand:SI 0 "nonimmediate_operand" "%rm")
2087: ; (match_operand:SI 1 "immediate_operand" "i"))
2088: ; (const_int 0))
2089: ; (label_ref (match_operand 2 "" ""))
2090: ; (pc)))]
2091: ; "GET_CODE (operands[1]) == CONST_INT
2092: ; && exact_log2 (INTVAL (operands[1])) >= 0"
2093: ; "*
2094: ;{
2095: ; operands[1]
2096: ; = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
2097: ; return \"bbs %1,%0,%l2\";
2098: ;}")
2099: ;
2100: ;(define_insn ""
2101: ; [(set (pc)
2102: ; (if_then_else
2103: ; (eq (and:SI (match_operand:SI 0 "nonimmediate_operand" "%rm")
2104: ; (match_operand:SI 1 "immediate_operand" "i"))
2105: ; (const_int 0))
2106: ; (label_ref (match_operand 2 "" ""))
2107: ; (pc)))]
2108: ; "GET_CODE (operands[1]) == CONST_INT
2109: ; && exact_log2 (INTVAL (operands[1])) >= 0"
2110: ; "*
2111: ;{
2112: ; operands[1]
2113: ; = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
2114: ; return \"bbc %1,%0,%l2\";
2115: ;}")
2116: ;
2117: ;(define_insn ""
2118: ; [(set (pc)
2119: ; (if_then_else
2120: ; (ne (and:SI (match_operand:SI 0 "nonimmediate_operand" "%rm")
2121: ; (match_operand:SI 1 "immediate_operand" "i"))
2122: ; (const_int 0))
2123: ; (pc)
2124: ; (label_ref (match_operand 2 "" ""))))]
2125: ; "GET_CODE (operands[1]) == CONST_INT
2126: ; && exact_log2 (INTVAL (operands[1])) >= 0"
2127: ; "*
2128: ;{
2129: ; operands[1]
2130: ; = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
2131: ; return \"bbc %1,%0,%l2\";
2132: ;}")
2133: ;
2134: ;(define_insn ""
2135: ; [(set (pc)
2136: ; (if_then_else
2137: ; (eq (and:SI (match_operand:SI 0 "nonimmediate_operand" "%rm")
2138: ; (match_operand:SI 1 "immediate_operand" "i"))
2139: ; (const_int 0))
2140: ; (pc)
2141: ; (label_ref (match_operand 2 "" ""))))]
2142: ; "GET_CODE (operands[1]) == CONST_INT
2143: ; && exact_log2 (INTVAL (operands[1])) >= 0"
2144: ; "*
2145: ;{
2146: ; operands[1]
2147: ; = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
2148: ; return \"bbs %1,%0,%l2\";
2149: ;}")
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