![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to expmed.diff CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Apple XNU] / GNUtools / cc|
Return to expmed.diff CVS log | Up to [Apple XNU] / GNUtools / cc |
1.1 root 1: *** expmed.c Fri Apr 8 10:07:44 1994
2: --- expmed.c.next Fri Apr 1 12:53:32 1994
3: ***************
4: *** 421,429 ****
5: /* If xop0 is a register, we need it in MAXMODE
6: to make it acceptable to the format of insv. */
7: if (GET_CODE (xop0) == SUBREG)
8: ! /* We can't just change the mode, because this might clobber op0,
9: ! and we will need the original value of op0 if insv fails. */
10: ! xop0 = gen_rtx (SUBREG, maxmode, SUBREG_REG (xop0), SUBREG_WORD (xop0));
11: if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode)
12: xop0 = gen_rtx (SUBREG, maxmode, xop0, 0);
13:
14: --- 421,427 ----
15: /* If xop0 is a register, we need it in MAXMODE
16: to make it acceptable to the format of insv. */
17: if (GET_CODE (xop0) == SUBREG)
18: ! PUT_MODE (xop0, maxmode);
19: if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode)
20: xop0 = gen_rtx (SUBREG, maxmode, xop0, 0);
21:
22: ***************
23: *** 517,533 ****
24: int all_zero = 0;
25: int all_one = 0;
26:
27: - /* If VALUE is a floating-point mode, access it as an integer of the
28: - corresponding size. This can occur on a machine with 64 bit registers
29: - that uses SFmode for float. This can also occur for unaligned float
30: - structure fields. */
31: - if (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT)
32: - {
33: - if (GET_CODE (value) != REG)
34: - value = copy_to_reg (value);
35: - value = gen_rtx (SUBREG, word_mode, value, 0);
36: - }
37: -
38: /* There is a case not handled here:
39: a structure with a known alignment of just a halfword
40: and a field split across two aligned halfwords within the structure.
41: --- 515,520 ----
42: ***************
43: *** 569,584 ****
44:
45: total_bits = GET_MODE_BITSIZE (mode);
46:
47: - /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
48: - be be in the range 0 to total_bits-1, and put any excess bytes in
49: - OFFSET. */
50: - if (bitpos >= total_bits)
51: - {
52: - offset += (bitpos / total_bits) * (total_bits / BITS_PER_UNIT);
53: - bitpos -= ((bitpos / total_bits) * (total_bits / BITS_PER_UNIT)
54: - * BITS_PER_UNIT);
55: - }
56: -
57: /* Get ref to an aligned byte, halfword, or word containing the field.
58: Adjust BITPOS to be position within a word,
59: and OFFSET to be the offset of that word.
60: --- 556,561 ----
61: ***************
62: *** 633,638 ****
63: --- 610,626 ----
64:
65: if (GET_MODE (value) != mode)
66: {
67: + /* If VALUE is a floating-point mode, access it as an integer
68: + of the corresponding size, then convert it. This can occur on
69: + a machine with 64 bit registers that uses SFmode for float. */
70: + if (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT)
71: + {
72: + if (GET_CODE (value) != REG)
73: + value = copy_to_reg (value);
74: + value
75: + = gen_rtx (SUBREG, word_mode, value, 0);
76: + }
77: +
78: if ((GET_CODE (value) == REG || GET_CODE (value) == SUBREG)
79: && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (value)))
80: value = gen_lowpart (mode, value);
81: ***************
82: *** 703,709 ****
83: {
84: rtx word = gen_lowpart_common (word_mode, value);
85:
86: ! if (word && (value != word))
87: value = word;
88: else
89: value = gen_lowpart_common (word_mode,
90: --- 691,697 ----
91: {
92: rtx word = gen_lowpart_common (word_mode, value);
93:
94: ! if (word)
95: value = word;
96: else
97: value = gen_lowpart_common (word_mode,
98: ***************
99: *** 733,751 ****
100: >> (bitsize - bitsdone - thissize))
101: & (((HOST_WIDE_INT) 1 << thissize) - 1));
102: else
103: ! {
104: ! /* The args are chosen so that the last part
105: ! includes the lsb. */
106: ! int bit_offset = 0;
107: ! /* If the value isn't in memory, then it must be right aligned
108: ! if a register, so skip past the padding on the left. If it
109: ! is in memory, then there is no padding on the left. */
110: ! if (GET_CODE (value) != MEM)
111: ! bit_offset = BITS_PER_WORD - bitsize;
112: ! part = extract_fixed_bit_field (word_mode, value, 0, thissize,
113: ! bit_offset + bitsdone,
114: ! NULL_RTX, 1, align);
115: ! }
116: #else
117: /* Fetch successively more significant portions. */
118: if (GET_CODE (value) == CONST_INT)
119: --- 721,731 ----
120: >> (bitsize - bitsdone - thissize))
121: & (((HOST_WIDE_INT) 1 << thissize) - 1));
122: else
123: ! /* The args are chosen so that the last part
124: ! includes the lsb. */
125: ! part = extract_fixed_bit_field (word_mode, value, 0, thissize,
126: ! BITS_PER_WORD - bitsize + bitsdone,
127: ! NULL_RTX, 1, align);
128: #else
129: /* Fetch successively more significant portions. */
130: if (GET_CODE (value) == CONST_INT)
131: ***************
132: *** 757,776 ****
133: #endif
134:
135: /* If OP0 is a register, then handle OFFSET here.
136: !
137: ! When handling multiword bitfields, extract_bit_field may pass
138: ! down a word_mode SUBREG of a larger REG for a bitfield that actually
139: ! crosses a word boundary. Thus, for a SUBREG, we must find
140: ! the current word starting from the base register. */
141: ! if (GET_CODE (op0) == SUBREG)
142: {
143: - word = operand_subword (SUBREG_REG (op0),
144: - SUBREG_WORD (op0) + offset, 1,
145: - GET_MODE (SUBREG_REG (op0)));
146: - offset = 0;
147: - }
148: - else if (GET_CODE (op0) == REG)
149: - {
150: word = operand_subword (op0, offset, 1, GET_MODE (op0));
151: offset = 0;
152: }
153: --- 737,745 ----
154: #endif
155:
156: /* If OP0 is a register, then handle OFFSET here.
157: ! In the register case, UNIT must be a whole word. */
158: ! if (GET_CODE (op0) == SUBREG || GET_CODE (op0) == REG)
159: {
160: word = operand_subword (op0, offset, 1, GET_MODE (op0));
161: offset = 0;
162: }
163: ***************
164: *** 928,942 ****
165: emit_move_insn (target_part, result_part);
166: }
167:
168: ! if (unsignedp)
169: ! return target;
170: ! /* Signed bit field: sign-extend with two arithmetic shifts. */
171: ! target = expand_shift (LSHIFT_EXPR, mode, target,
172: ! build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0),
173: ! NULL_RTX, 0);
174: ! return expand_shift (RSHIFT_EXPR, mode, target,
175: ! build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0),
176: ! NULL_RTX, 0);
177: }
178:
179: /* From here on we know the desired field is smaller than a word
180: --- 897,903 ----
181: emit_move_insn (target_part, result_part);
182: }
183:
184: ! return target;
185: }
186:
187: /* From here on we know the desired field is smaller than a word
188: ***************
189: *** 1524,1543 ****
190: thissize = MIN (thissize, unit - thispos);
191:
192: /* If OP0 is a register, then handle OFFSET here.
193: !
194: ! When handling multiword bitfields, extract_bit_field may pass
195: ! down a word_mode SUBREG of a larger REG for a bitfield that actually
196: ! crosses a word boundary. Thus, for a SUBREG, we must find
197: ! the current word starting from the base register. */
198: ! if (GET_CODE (op0) == SUBREG)
199: {
200: - word = operand_subword_force (SUBREG_REG (op0),
201: - SUBREG_WORD (op0) + offset,
202: - GET_MODE (SUBREG_REG (op0)));
203: - offset = 0;
204: - }
205: - else if (GET_CODE (op0) == REG)
206: - {
207: word = operand_subword_force (op0, offset, GET_MODE (op0));
208: offset = 0;
209: }
210: --- 1485,1493 ----
211: thissize = MIN (thissize, unit - thispos);
212:
213: /* If OP0 is a register, then handle OFFSET here.
214: ! In the register case, UNIT must be a whole word. */
215: ! if (GET_CODE (op0) == SUBREG || GET_CODE (op0) == REG)
216: {
217: word = operand_subword_force (op0, offset, GET_MODE (op0));
218: offset = 0;
219: }
220: ***************
221: *** 1642,1655 ****
222:
223: op1 = expand_expr (amount, NULL_RTX, VOIDmode, 0);
224:
225: - #if SHIFT_COUNT_TRUNCATED
226: - if (SHIFT_COUNT_TRUNCATED
227: - && GET_CODE (op1) == CONST_INT
228: - && (unsigned HOST_WIDE_INT) INTVAL (op1) >= GET_MODE_BITSIZE (mode))
229: - op1 = GEN_INT ((unsigned HOST_WIDE_INT) INTVAL (op1)
230: - % GET_MODE_BITSIZE (mode));
231: - #endif
232: -
233: if (op1 == const0_rtx)
234: return shifted;
235:
236: --- 1592,1597 ----
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.