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1.1 root 1: /* Reload pseudo regs into hard regs for insns that require hard regs.
2: Copyright (C) 1987, 1988, 1989, 1992, 1993 Free Software Foundation, Inc.
3:
4: This file is part of GNU CC.
5:
6: GNU CC is free software; you can redistribute it and/or modify
7: it under the terms of the GNU General Public License as published by
8: the Free Software Foundation; either version 2, or (at your option)
9: any later version.
10:
11: GNU CC is distributed in the hope that it will be useful,
12: but WITHOUT ANY WARRANTY; without even the implied warranty of
13: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14: GNU General Public License for more details.
15:
16: You should have received a copy of the GNU General Public License
17: along with GNU CC; see the file COPYING. If not, write to
18: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
19:
20:
21: #include <stdio.h>
22: #include "config.h"
23: #include "rtl.h"
24: #include "obstack.h"
25: #include "insn-config.h"
26: #include "insn-flags.h"
27: #include "insn-codes.h"
28: #include "flags.h"
29: #include "expr.h"
30: #include "regs.h"
31: #include "hard-reg-set.h"
32: #include "reload.h"
33: #include "recog.h"
34: #include "basic-block.h"
35: #include "output.h"
36:
37: /* This file contains the reload pass of the compiler, which is
38: run after register allocation has been done. It checks that
39: each insn is valid (operands required to be in registers really
40: are in registers of the proper class) and fixes up invalid ones
41: by copying values temporarily into registers for the insns
42: that need them.
43:
44: The results of register allocation are described by the vector
45: reg_renumber; the insns still contain pseudo regs, but reg_renumber
46: can be used to find which hard reg, if any, a pseudo reg is in.
47:
48: The technique we always use is to free up a few hard regs that are
49: called ``reload regs'', and for each place where a pseudo reg
50: must be in a hard reg, copy it temporarily into one of the reload regs.
51:
52: All the pseudos that were formerly allocated to the hard regs that
53: are now in use as reload regs must be ``spilled''. This means
54: that they go to other hard regs, or to stack slots if no other
55: available hard regs can be found. Spilling can invalidate more
56: insns, requiring additional need for reloads, so we must keep checking
57: until the process stabilizes.
58:
59: For machines with different classes of registers, we must keep track
60: of the register class needed for each reload, and make sure that
61: we allocate enough reload registers of each class.
62:
63: The file reload.c contains the code that checks one insn for
64: validity and reports the reloads that it needs. This file
65: is in charge of scanning the entire rtl code, accumulating the
66: reload needs, spilling, assigning reload registers to use for
67: fixing up each insn, and generating the new insns to copy values
68: into the reload registers. */
69:
70:
71: #ifndef REGISTER_MOVE_COST
72: #define REGISTER_MOVE_COST(x, y) 2
73: #endif
74:
75: #ifndef MEMORY_MOVE_COST
76: #define MEMORY_MOVE_COST(x) 4
77: #endif
78:
79: /* During reload_as_needed, element N contains a REG rtx for the hard reg
80: into which reg N has been reloaded (perhaps for a previous insn). */
81: static rtx *reg_last_reload_reg;
82:
83: /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
84: for an output reload that stores into reg N. */
85: static char *reg_has_output_reload;
86:
87: /* Indicates which hard regs are reload-registers for an output reload
88: in the current insn. */
89: static HARD_REG_SET reg_is_output_reload;
90:
91: /* Element N is the constant value to which pseudo reg N is equivalent,
92: or zero if pseudo reg N is not equivalent to a constant.
93: find_reloads looks at this in order to replace pseudo reg N
94: with the constant it stands for. */
95: rtx *reg_equiv_constant;
96:
97: /* Element N is a memory location to which pseudo reg N is equivalent,
98: prior to any register elimination (such as frame pointer to stack
99: pointer). Depending on whether or not it is a valid address, this value
100: is transferred to either reg_equiv_address or reg_equiv_mem. */
101: rtx *reg_equiv_memory_loc;
102:
103: /* Element N is the address of stack slot to which pseudo reg N is equivalent.
104: This is used when the address is not valid as a memory address
105: (because its displacement is too big for the machine.) */
106: rtx *reg_equiv_address;
107:
108: /* Element N is the memory slot to which pseudo reg N is equivalent,
109: or zero if pseudo reg N is not equivalent to a memory slot. */
110: rtx *reg_equiv_mem;
111:
112: /* Widest width in which each pseudo reg is referred to (via subreg). */
113: static int *reg_max_ref_width;
114:
115: /* Element N is the insn that initialized reg N from its equivalent
116: constant or memory slot. */
117: static rtx *reg_equiv_init;
118:
119: /* During reload_as_needed, element N contains the last pseudo regno
120: reloaded into the Nth reload register. This vector is in parallel
121: with spill_regs. If that pseudo reg occupied more than one register,
122: reg_reloaded_contents points to that pseudo for each spill register in
123: use; all of these must remain set for an inheritance to occur. */
124: static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
125:
126: /* During reload_as_needed, element N contains the insn for which
127: the Nth reload register was last used. This vector is in parallel
128: with spill_regs, and its contents are significant only when
129: reg_reloaded_contents is significant. */
130: static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
131:
132: /* Number of spill-regs so far; number of valid elements of spill_regs. */
133: static int n_spills;
134:
135: /* In parallel with spill_regs, contains REG rtx's for those regs.
136: Holds the last rtx used for any given reg, or 0 if it has never
137: been used for spilling yet. This rtx is reused, provided it has
138: the proper mode. */
139: static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
140:
141: /* In parallel with spill_regs, contains nonzero for a spill reg
142: that was stored after the last time it was used.
143: The precise value is the insn generated to do the store. */
144: static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
145:
146: /* This table is the inverse mapping of spill_regs:
147: indexed by hard reg number,
148: it contains the position of that reg in spill_regs,
149: or -1 for something that is not in spill_regs. */
150: static short spill_reg_order[FIRST_PSEUDO_REGISTER];
151:
152: /* This reg set indicates registers that may not be used for retrying global
153: allocation. The registers that may not be used include all spill registers
154: and the frame pointer (if we are using one). */
155: HARD_REG_SET forbidden_regs;
156:
157: /* This reg set indicates registers that are not good for spill registers.
158: They will not be used to complete groups of spill registers. This includes
159: all fixed registers, registers that may be eliminated, and, if
160: SMALL_REGISTER_CLASSES is not defined, registers explicitly used in the rtl.
161:
162: (spill_reg_order prevents these registers from being used to start a
163: group.) */
164: static HARD_REG_SET bad_spill_regs;
165:
166: /* Describes order of use of registers for reloading
167: of spilled pseudo-registers. `spills' is the number of
168: elements that are actually valid; new ones are added at the end. */
169: static short spill_regs[FIRST_PSEUDO_REGISTER];
170:
171: /* Describes order of preference for putting regs into spill_regs.
172: Contains the numbers of all the hard regs, in order most preferred first.
173: This order is different for each function.
174: It is set up by order_regs_for_reload.
175: Empty elements at the end contain -1. */
176: static short potential_reload_regs[FIRST_PSEUDO_REGISTER];
177:
178: /* 1 for a hard register that appears explicitly in the rtl
179: (for example, function value registers, special registers
180: used by insns, structure value pointer registers). */
181: static char regs_explicitly_used[FIRST_PSEUDO_REGISTER];
182:
183: /* Indicates if a register was counted against the need for
184: groups. 0 means it can count against max_nongroup instead. */
185: static HARD_REG_SET counted_for_groups;
186:
187: /* Indicates if a register was counted against the need for
188: non-groups. 0 means it can become part of a new group.
189: During choose_reload_regs, 1 here means don't use this reg
190: as part of a group, even if it seems to be otherwise ok. */
191: static HARD_REG_SET counted_for_nongroups;
192:
193: /* Indexed by pseudo reg number N,
194: says may not delete stores into the real (memory) home of pseudo N.
195: This is set if we already substituted a memory equivalent in some uses,
196: which happens when we have to eliminate the fp from it. */
197: static char *cannot_omit_stores;
198:
199: /* Nonzero if indirect addressing is supported on the machine; this means
200: that spilling (REG n) does not require reloading it into a register in
201: order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
202: value indicates the level of indirect addressing supported, e.g., two
203: means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
204: a hard register. */
205:
206: static char spill_indirect_levels;
207:
208: /* Nonzero if indirect addressing is supported when the innermost MEM is
209: of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
210: which these are valid is the same as spill_indirect_levels, above. */
211:
212: char indirect_symref_ok;
213:
214: /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
215:
216: char double_reg_address_ok;
217:
218: /* Record the stack slot for each spilled hard register. */
219:
220: static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
221:
222: /* Width allocated so far for that stack slot. */
223:
224: static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
225:
226: /* Indexed by register class and basic block number, nonzero if there is
227: any need for a spill register of that class in that basic block.
228: The pointer is 0 if we did stupid allocation and don't know
229: the structure of basic blocks. */
230:
231: char *basic_block_needs[N_REG_CLASSES];
232:
233: /* First uid used by insns created by reload in this function.
234: Used in find_equiv_reg. */
235: int reload_first_uid;
236:
237: /* Flag set by local-alloc or global-alloc if anything is live in
238: a call-clobbered reg across calls. */
239:
240: int caller_save_needed;
241:
242: /* Set to 1 while reload_as_needed is operating.
243: Required by some machines to handle any generated moves differently. */
244:
245: int reload_in_progress = 0;
246:
247: /* These arrays record the insn_code of insns that may be needed to
248: perform input and output reloads of special objects. They provide a
249: place to pass a scratch register. */
250:
251: enum insn_code reload_in_optab[NUM_MACHINE_MODES];
252: enum insn_code reload_out_optab[NUM_MACHINE_MODES];
253:
254: /* This obstack is used for allocation of rtl during register elimination.
255: The allocated storage can be freed once find_reloads has processed the
256: insn. */
257:
258: struct obstack reload_obstack;
259: char *reload_firstobj;
260:
261: #define obstack_chunk_alloc xmalloc
262: #define obstack_chunk_free free
263:
264: /* List of labels that must never be deleted. */
265: extern rtx forced_labels;
266:
267: /* This structure is used to record information about register eliminations.
268: Each array entry describes one possible way of eliminating a register
269: in favor of another. If there is more than one way of eliminating a
270: particular register, the most preferred should be specified first. */
271:
272: static struct elim_table
273: {
274: int from; /* Register number to be eliminated. */
275: int to; /* Register number used as replacement. */
276: int initial_offset; /* Initial difference between values. */
277: int can_eliminate; /* Non-zero if this elimination can be done. */
278: int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
279: insns made by reload. */
280: int offset; /* Current offset between the two regs. */
281: int max_offset; /* Maximum offset between the two regs. */
282: int previous_offset; /* Offset at end of previous insn. */
283: int ref_outside_mem; /* "to" has been referenced outside a MEM. */
284: rtx from_rtx; /* REG rtx for the register to be eliminated.
285: We cannot simply compare the number since
286: we might then spuriously replace a hard
287: register corresponding to a pseudo
288: assigned to the reg to be eliminated. */
289: rtx to_rtx; /* REG rtx for the replacement. */
290: } reg_eliminate[] =
291:
292: /* If a set of eliminable registers was specified, define the table from it.
293: Otherwise, default to the normal case of the frame pointer being
294: replaced by the stack pointer. */
295:
296: #ifdef ELIMINABLE_REGS
297: ELIMINABLE_REGS;
298: #else
299: {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
300: #endif
301:
302: #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate / sizeof reg_eliminate[0])
303:
304: /* Record the number of pending eliminations that have an offset not equal
305: to their initial offset. If non-zero, we use a new copy of each
306: replacement result in any insns encountered. */
307: static int num_not_at_initial_offset;
308:
309: /* Count the number of registers that we may be able to eliminate. */
310: static int num_eliminable;
311:
312: /* For each label, we record the offset of each elimination. If we reach
313: a label by more than one path and an offset differs, we cannot do the
314: elimination. This information is indexed by the number of the label.
315: The first table is an array of flags that records whether we have yet
316: encountered a label and the second table is an array of arrays, one
317: entry in the latter array for each elimination. */
318:
319: static char *offsets_known_at;
320: static int (*offsets_at)[NUM_ELIMINABLE_REGS];
321:
322: /* Number of labels in the current function. */
323:
324: static int num_labels;
325:
326: struct hard_reg_n_uses { int regno; int uses; };
327:
328: static int possible_group_p PROTO((int, int *));
329: static void count_possible_groups PROTO((int *, enum machine_mode *,
330: int *));
331: static int modes_equiv_for_class_p PROTO((enum machine_mode,
332: enum machine_mode,
333: enum reg_class));
334: static void spill_failure PROTO((rtx));
335: static int new_spill_reg PROTO((int, int, int *, int *, int,
336: FILE *));
337: static void delete_dead_insn PROTO((rtx));
338: static void alter_reg PROTO((int, int));
339: static void mark_scratch_live PROTO((rtx));
340: static void set_label_offsets PROTO((rtx, rtx, int));
341: static int eliminate_regs_in_insn PROTO((rtx, int));
342: static void mark_not_eliminable PROTO((rtx, rtx));
343: static int spill_hard_reg PROTO((int, int, FILE *, int));
344: static void scan_paradoxical_subregs PROTO((rtx));
345: static int hard_reg_use_compare PROTO((struct hard_reg_n_uses *,
346: struct hard_reg_n_uses *));
347: static void order_regs_for_reload PROTO((void));
348: static void reload_as_needed PROTO((rtx, int));
349: static void forget_old_reloads_1 PROTO((rtx, rtx));
350: static int reload_reg_class_lower PROTO((short *, short *));
351: static void mark_reload_reg_in_use PROTO((int, int, enum reload_type,
352: enum machine_mode));
353: static void clear_reload_reg_in_use PROTO((int, int, enum reload_type,
354: enum machine_mode));
355: static int reload_reg_free_p PROTO((int, int, enum reload_type));
356: static int reload_reg_free_before_p PROTO((int, int, enum reload_type));
357: static int reload_reg_reaches_end_p PROTO((int, int, enum reload_type));
358: static int allocate_reload_reg PROTO((int, rtx, int, int));
359: static void choose_reload_regs PROTO((rtx, rtx));
360: static void merge_assigned_reloads PROTO((rtx));
361: static void emit_reload_insns PROTO((rtx));
362: static void delete_output_reload PROTO((rtx, int, rtx));
363: static void inc_for_reload PROTO((rtx, rtx, int));
364: static int constraint_accepts_reg_p PROTO((char *, rtx));
365: static int count_occurrences PROTO((rtx, rtx));
366:
367: /* Initialize the reload pass once per compilation. */
368:
369: void
370: init_reload ()
371: {
372: register int i;
373:
374: /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
375: Set spill_indirect_levels to the number of levels such addressing is
376: permitted, zero if it is not permitted at all. */
377:
378: register rtx tem
379: = gen_rtx (MEM, Pmode,
380: gen_rtx (PLUS, Pmode,
381: gen_rtx (REG, Pmode, LAST_VIRTUAL_REGISTER + 1),
382: GEN_INT (4)));
383: spill_indirect_levels = 0;
384:
385: while (memory_address_p (QImode, tem))
386: {
387: spill_indirect_levels++;
388: tem = gen_rtx (MEM, Pmode, tem);
389: }
390:
391: /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
392:
393: tem = gen_rtx (MEM, Pmode, gen_rtx (SYMBOL_REF, Pmode, "foo"));
394: indirect_symref_ok = memory_address_p (QImode, tem);
395:
396: /* See if reg+reg is a valid (and offsettable) address. */
397:
398: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
399: {
400: tem = gen_rtx (PLUS, Pmode,
401: gen_rtx (REG, Pmode, HARD_FRAME_POINTER_REGNUM),
402: gen_rtx (REG, Pmode, i));
403: /* This way, we make sure that reg+reg is an offsettable address. */
404: tem = plus_constant (tem, 4);
405:
406: if (memory_address_p (QImode, tem))
407: {
408: double_reg_address_ok = 1;
409: break;
410: }
411: }
412:
413: /* Initialize obstack for our rtl allocation. */
414: gcc_obstack_init (&reload_obstack);
415: reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
416: }
417:
418: /* Main entry point for the reload pass.
419:
420: FIRST is the first insn of the function being compiled.
421:
422: GLOBAL nonzero means we were called from global_alloc
423: and should attempt to reallocate any pseudoregs that we
424: displace from hard regs we will use for reloads.
425: If GLOBAL is zero, we do not have enough information to do that,
426: so any pseudo reg that is spilled must go to the stack.
427:
428: DUMPFILE is the global-reg debugging dump file stream, or 0.
429: If it is nonzero, messages are written to it to describe
430: which registers are seized as reload regs, which pseudo regs
431: are spilled from them, and where the pseudo regs are reallocated to.
432:
433: Return value is nonzero if reload failed
434: and we must not do any more for this function. */
435:
436: int
437: reload (first, global, dumpfile)
438: rtx first;
439: int global;
440: FILE *dumpfile;
441: {
442: register int class;
443: register int i, j;
444: register rtx insn;
445: register struct elim_table *ep;
446:
447: int something_changed;
448: int something_needs_reloads;
449: int something_needs_elimination;
450: int new_basic_block_needs;
451: enum reg_class caller_save_spill_class = NO_REGS;
452: int caller_save_group_size = 1;
453:
454: /* Nonzero means we couldn't get enough spill regs. */
455: int failure = 0;
456:
457: /* The basic block number currently being processed for INSN. */
458: int this_block;
459:
460: /* Make sure even insns with volatile mem refs are recognizable. */
461: init_recog ();
462:
463: /* Enable find_equiv_reg to distinguish insns made by reload. */
464: reload_first_uid = get_max_uid ();
465:
466: for (i = 0; i < N_REG_CLASSES; i++)
467: basic_block_needs[i] = 0;
468:
469: #ifdef SECONDARY_MEMORY_NEEDED
470: /* Initialize the secondary memory table. */
471: clear_secondary_mem ();
472: #endif
473:
474: /* Remember which hard regs appear explicitly
475: before we merge into `regs_ever_live' the ones in which
476: pseudo regs have been allocated. */
477: bcopy (regs_ever_live, regs_explicitly_used, sizeof regs_ever_live);
478:
479: /* We don't have a stack slot for any spill reg yet. */
480: bzero (spill_stack_slot, sizeof spill_stack_slot);
481: bzero (spill_stack_slot_width, sizeof spill_stack_slot_width);
482:
483: /* Initialize the save area information for caller-save, in case some
484: are needed. */
485: init_save_areas ();
486:
487: /* Compute which hard registers are now in use
488: as homes for pseudo registers.
489: This is done here rather than (eg) in global_alloc
490: because this point is reached even if not optimizing. */
491:
492: for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
493: mark_home_live (i);
494:
495: for (i = 0; i < scratch_list_length; i++)
496: if (scratch_list[i])
497: mark_scratch_live (scratch_list[i]);
498:
499: /* Make sure that the last insn in the chain
500: is not something that needs reloading. */
501: emit_note (NULL_PTR, NOTE_INSN_DELETED);
502:
503: /* Find all the pseudo registers that didn't get hard regs
504: but do have known equivalent constants or memory slots.
505: These include parameters (known equivalent to parameter slots)
506: and cse'd or loop-moved constant memory addresses.
507:
508: Record constant equivalents in reg_equiv_constant
509: so they will be substituted by find_reloads.
510: Record memory equivalents in reg_mem_equiv so they can
511: be substituted eventually by altering the REG-rtx's. */
512:
513: reg_equiv_constant = (rtx *) alloca (max_regno * sizeof (rtx));
514: bzero (reg_equiv_constant, max_regno * sizeof (rtx));
515: reg_equiv_memory_loc = (rtx *) alloca (max_regno * sizeof (rtx));
516: bzero (reg_equiv_memory_loc, max_regno * sizeof (rtx));
517: reg_equiv_mem = (rtx *) alloca (max_regno * sizeof (rtx));
518: bzero (reg_equiv_mem, max_regno * sizeof (rtx));
519: reg_equiv_init = (rtx *) alloca (max_regno * sizeof (rtx));
520: bzero (reg_equiv_init, max_regno * sizeof (rtx));
521: reg_equiv_address = (rtx *) alloca (max_regno * sizeof (rtx));
522: bzero (reg_equiv_address, max_regno * sizeof (rtx));
523: reg_max_ref_width = (int *) alloca (max_regno * sizeof (int));
524: bzero (reg_max_ref_width, max_regno * sizeof (int));
525: cannot_omit_stores = (char *) alloca (max_regno);
526: bzero (cannot_omit_stores, max_regno);
527:
528: /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
529: Also find all paradoxical subregs
530: and find largest such for each pseudo. */
531:
532: for (insn = first; insn; insn = NEXT_INSN (insn))
533: {
534: rtx set = single_set (insn);
535:
536: if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
537: {
538: rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
539: if (note
540: #ifdef LEGITIMATE_PIC_OPERAND_P
541: && (! CONSTANT_P (XEXP (note, 0)) || ! flag_pic
542: || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
543: #endif
544: )
545: {
546: rtx x = XEXP (note, 0);
547: i = REGNO (SET_DEST (set));
548: if (i > LAST_VIRTUAL_REGISTER)
549: {
550: if (GET_CODE (x) == MEM)
551: reg_equiv_memory_loc[i] = x;
552: else if (CONSTANT_P (x))
553: {
554: if (LEGITIMATE_CONSTANT_P (x))
555: reg_equiv_constant[i] = x;
556: else
557: reg_equiv_memory_loc[i]
558: = force_const_mem (GET_MODE (SET_DEST (set)), x);
559: }
560: else
561: continue;
562:
563: /* If this register is being made equivalent to a MEM
564: and the MEM is not SET_SRC, the equivalencing insn
565: is one with the MEM as a SET_DEST and it occurs later.
566: So don't mark this insn now. */
567: if (GET_CODE (x) != MEM
568: || rtx_equal_p (SET_SRC (set), x))
569: reg_equiv_init[i] = insn;
570: }
571: }
572: }
573:
574: /* If this insn is setting a MEM from a register equivalent to it,
575: this is the equivalencing insn. */
576: else if (set && GET_CODE (SET_DEST (set)) == MEM
577: && GET_CODE (SET_SRC (set)) == REG
578: && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
579: && rtx_equal_p (SET_DEST (set),
580: reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
581: reg_equiv_init[REGNO (SET_SRC (set))] = insn;
582:
583: if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
584: scan_paradoxical_subregs (PATTERN (insn));
585: }
586:
587: /* Does this function require a frame pointer? */
588:
589: frame_pointer_needed = (! flag_omit_frame_pointer
590: #ifdef EXIT_IGNORE_STACK
591: /* ?? If EXIT_IGNORE_STACK is set, we will not save
592: and restore sp for alloca. So we can't eliminate
593: the frame pointer in that case. At some point,
594: we should improve this by emitting the
595: sp-adjusting insns for this case. */
596: || (current_function_calls_alloca
597: && EXIT_IGNORE_STACK)
598: #endif
599: || FRAME_POINTER_REQUIRED);
600:
601: num_eliminable = 0;
602:
603: /* Initialize the table of registers to eliminate. The way we do this
604: depends on how the eliminable registers were defined. */
605: #ifdef ELIMINABLE_REGS
606: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
607: {
608: ep->can_eliminate = ep->can_eliminate_previous
609: = (CAN_ELIMINATE (ep->from, ep->to)
610: && (ep->from != HARD_FRAME_POINTER_REGNUM
611: || ! frame_pointer_needed));
612: }
613: #else
614: reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
615: = ! frame_pointer_needed;
616: #endif
617:
618: /* Count the number of eliminable registers and build the FROM and TO
619: REG rtx's. Note that code in gen_rtx will cause, e.g.,
620: gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
621: We depend on this. */
622: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
623: {
624: num_eliminable += ep->can_eliminate;
625: ep->from_rtx = gen_rtx (REG, Pmode, ep->from);
626: ep->to_rtx = gen_rtx (REG, Pmode, ep->to);
627: }
628:
629: num_labels = max_label_num () - get_first_label_num ();
630:
631: /* Allocate the tables used to store offset information at labels. */
632: offsets_known_at = (char *) alloca (num_labels);
633: offsets_at
634: = (int (*)[NUM_ELIMINABLE_REGS])
635: alloca (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
636:
637: offsets_known_at -= get_first_label_num ();
638: offsets_at -= get_first_label_num ();
639:
640: /* Alter each pseudo-reg rtx to contain its hard reg number.
641: Assign stack slots to the pseudos that lack hard regs or equivalents.
642: Do not touch virtual registers. */
643:
644: for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
645: alter_reg (i, -1);
646:
647: /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done here
648: because the stack size may be a part of the offset computation for
649: register elimination. */
650: assign_stack_local (BLKmode, 0, 0);
651:
652: /* If we have some registers we think can be eliminated, scan all insns to
653: see if there is an insn that sets one of these registers to something
654: other than itself plus a constant. If so, the register cannot be
655: eliminated. Doing this scan here eliminates an extra pass through the
656: main reload loop in the most common case where register elimination
657: cannot be done. */
658: for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
659: if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
660: || GET_CODE (insn) == CALL_INSN)
661: note_stores (PATTERN (insn), mark_not_eliminable);
662:
663: #ifndef REGISTER_CONSTRAINTS
664: /* If all the pseudo regs have hard regs,
665: except for those that are never referenced,
666: we know that no reloads are needed. */
667: /* But that is not true if there are register constraints, since
668: in that case some pseudos might be in the wrong kind of hard reg. */
669:
670: for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
671: if (reg_renumber[i] == -1 && reg_n_refs[i] != 0)
672: break;
673:
674: if (i == max_regno && num_eliminable == 0 && ! caller_save_needed)
675: return;
676: #endif
677:
678: /* Compute the order of preference for hard registers to spill.
679: Store them by decreasing preference in potential_reload_regs. */
680:
681: order_regs_for_reload ();
682:
683: /* So far, no hard regs have been spilled. */
684: n_spills = 0;
685: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
686: spill_reg_order[i] = -1;
687:
688: /* On most machines, we can't use any register explicitly used in the
689: rtl as a spill register. But on some, we have to. Those will have
690: taken care to keep the life of hard regs as short as possible. */
691:
692: #ifdef SMALL_REGISTER_CLASSES
693: CLEAR_HARD_REG_SET (forbidden_regs);
694: #else
695: COPY_HARD_REG_SET (forbidden_regs, bad_spill_regs);
696: #endif
697:
698: /* Spill any hard regs that we know we can't eliminate. */
699: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
700: if (! ep->can_eliminate)
701: {
702: spill_hard_reg (ep->from, global, dumpfile, 1);
703: regs_ever_live[ep->from] = 1;
704: }
705:
706: if (global)
707: for (i = 0; i < N_REG_CLASSES; i++)
708: {
709: basic_block_needs[i] = (char *)alloca (n_basic_blocks);
710: bzero (basic_block_needs[i], n_basic_blocks);
711: }
712:
713: /* From now on, we need to emit any moves without making new pseudos. */
714: reload_in_progress = 1;
715:
716: /* This loop scans the entire function each go-round
717: and repeats until one repetition spills no additional hard regs. */
718:
719: /* This flag is set when a pseudo reg is spilled,
720: to require another pass. Note that getting an additional reload
721: reg does not necessarily imply any pseudo reg was spilled;
722: sometimes we find a reload reg that no pseudo reg was allocated in. */
723: something_changed = 1;
724: /* This flag is set if there are any insns that require reloading. */
725: something_needs_reloads = 0;
726: /* This flag is set if there are any insns that require register
727: eliminations. */
728: something_needs_elimination = 0;
729: while (something_changed)
730: {
731: rtx after_call = 0;
732:
733: /* For each class, number of reload regs needed in that class.
734: This is the maximum over all insns of the needs in that class
735: of the individual insn. */
736: int max_needs[N_REG_CLASSES];
737: /* For each class, size of group of consecutive regs
738: that is needed for the reloads of this class. */
739: int group_size[N_REG_CLASSES];
740: /* For each class, max number of consecutive groups needed.
741: (Each group contains group_size[CLASS] consecutive registers.) */
742: int max_groups[N_REG_CLASSES];
743: /* For each class, max number needed of regs that don't belong
744: to any of the groups. */
745: int max_nongroups[N_REG_CLASSES];
746: /* For each class, the machine mode which requires consecutive
747: groups of regs of that class.
748: If two different modes ever require groups of one class,
749: they must be the same size and equally restrictive for that class,
750: otherwise we can't handle the complexity. */
751: enum machine_mode group_mode[N_REG_CLASSES];
752: /* Record the insn where each maximum need is first found. */
753: rtx max_needs_insn[N_REG_CLASSES];
754: rtx max_groups_insn[N_REG_CLASSES];
755: rtx max_nongroups_insn[N_REG_CLASSES];
756: rtx x;
757: int starting_frame_size = get_frame_size ();
758: static char *reg_class_names[] = REG_CLASS_NAMES;
759:
760: something_changed = 0;
761: bzero (max_needs, sizeof max_needs);
762: bzero (max_groups, sizeof max_groups);
763: bzero (max_nongroups, sizeof max_nongroups);
764: bzero (max_needs_insn, sizeof max_needs_insn);
765: bzero (max_groups_insn, sizeof max_groups_insn);
766: bzero (max_nongroups_insn, sizeof max_nongroups_insn);
767: bzero (group_size, sizeof group_size);
768: for (i = 0; i < N_REG_CLASSES; i++)
769: group_mode[i] = VOIDmode;
770:
771: /* Keep track of which basic blocks are needing the reloads. */
772: this_block = 0;
773:
774: /* Remember whether any element of basic_block_needs
775: changes from 0 to 1 in this pass. */
776: new_basic_block_needs = 0;
777:
778: /* Reset all offsets on eliminable registers to their initial values. */
779: #ifdef ELIMINABLE_REGS
780: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
781: {
782: INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
783: ep->previous_offset = ep->offset
784: = ep->max_offset = ep->initial_offset;
785: }
786: #else
787: #ifdef INITIAL_FRAME_POINTER_OFFSET
788: INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
789: #else
790: if (!FRAME_POINTER_REQUIRED)
791: abort ();
792: reg_eliminate[0].initial_offset = 0;
793: #endif
794: reg_eliminate[0].previous_offset = reg_eliminate[0].max_offset
795: = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
796: #endif
797:
798: num_not_at_initial_offset = 0;
799:
800: bzero (&offsets_known_at[get_first_label_num ()], num_labels);
801:
802: /* Set a known offset for each forced label to be at the initial offset
803: of each elimination. We do this because we assume that all
804: computed jumps occur from a location where each elimination is
805: at its initial offset. */
806:
807: for (x = forced_labels; x; x = XEXP (x, 1))
808: if (XEXP (x, 0))
809: set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
810:
811: /* For each pseudo register that has an equivalent location defined,
812: try to eliminate any eliminable registers (such as the frame pointer)
813: assuming initial offsets for the replacement register, which
814: is the normal case.
815:
816: If the resulting location is directly addressable, substitute
817: the MEM we just got directly for the old REG.
818:
819: If it is not addressable but is a constant or the sum of a hard reg
820: and constant, it is probably not addressable because the constant is
821: out of range, in that case record the address; we will generate
822: hairy code to compute the address in a register each time it is
823: needed. Similarly if it is a hard register, but one that is not
824: valid as an address register.
825:
826: If the location is not addressable, but does not have one of the
827: above forms, assign a stack slot. We have to do this to avoid the
828: potential of producing lots of reloads if, e.g., a location involves
829: a pseudo that didn't get a hard register and has an equivalent memory
830: location that also involves a pseudo that didn't get a hard register.
831:
832: Perhaps at some point we will improve reload_when_needed handling
833: so this problem goes away. But that's very hairy. */
834:
835: for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
836: if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
837: {
838: rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
839:
840: if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
841: XEXP (x, 0)))
842: reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
843: else if (CONSTANT_P (XEXP (x, 0))
844: || (GET_CODE (XEXP (x, 0)) == REG
845: && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
846: || (GET_CODE (XEXP (x, 0)) == PLUS
847: && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
848: && (REGNO (XEXP (XEXP (x, 0), 0))
849: < FIRST_PSEUDO_REGISTER)
850: && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
851: reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
852: else
853: {
854: /* Make a new stack slot. Then indicate that something
855: changed so we go back and recompute offsets for
856: eliminable registers because the allocation of memory
857: below might change some offset. reg_equiv_{mem,address}
858: will be set up for this pseudo on the next pass around
859: the loop. */
860: reg_equiv_memory_loc[i] = 0;
861: reg_equiv_init[i] = 0;
862: alter_reg (i, -1);
863: something_changed = 1;
864: }
865: }
866:
867: /* If we allocated another pseudo to the stack, redo elimination
868: bookkeeping. */
869: if (something_changed)
870: continue;
871:
872: /* If caller-saves needs a group, initialize the group to include
873: the size and mode required for caller-saves. */
874:
875: if (caller_save_group_size > 1)
876: {
877: group_mode[(int) caller_save_spill_class] = Pmode;
878: group_size[(int) caller_save_spill_class] = caller_save_group_size;
879: }
880:
881: /* Compute the most additional registers needed by any instruction.
882: Collect information separately for each class of regs. */
883:
884: for (insn = first; insn; insn = NEXT_INSN (insn))
885: {
886: if (global && this_block + 1 < n_basic_blocks
887: && insn == basic_block_head[this_block+1])
888: ++this_block;
889:
890: /* If this is a label, a JUMP_INSN, or has REG_NOTES (which
891: might include REG_LABEL), we need to see what effects this
892: has on the known offsets at labels. */
893:
894: if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
895: || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
896: && REG_NOTES (insn) != 0))
897: set_label_offsets (insn, insn, 0);
898:
899: if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
900: {
901: /* Nonzero means don't use a reload reg that overlaps
902: the place where a function value can be returned. */
903: rtx avoid_return_reg = 0;
904:
905: rtx old_body = PATTERN (insn);
906: int old_code = INSN_CODE (insn);
907: rtx old_notes = REG_NOTES (insn);
908: int did_elimination = 0;
909: int max_total_input_groups = 0, max_total_output_groups = 0;
910:
911: /* To compute the number of reload registers of each class
912: needed for an insn, we must similate what choose_reload_regs
913: can do. We do this by splitting an insn into an "input" and
914: an "output" part. RELOAD_OTHER reloads are used in both.
915: The input part uses those reloads, RELOAD_FOR_INPUT reloads,
916: which must be live over the entire input section of reloads,
917: and the maximum of all the RELOAD_FOR_INPUT_ADDRESS and
918: RELOAD_FOR_OPERAND_ADDRESS reloads, which conflict with the
919: inputs.
920:
921: The registers needed for output are RELOAD_OTHER and
922: RELOAD_FOR_OUTPUT, which are live for the entire output
923: portion, and the maximum of all the RELOAD_FOR_OUTPUT_ADDRESS
924: reloads for each operand.
925:
926: The total number of registers needed is the maximum of the
927: inputs and outputs. */
928:
929: /* These just count RELOAD_OTHER. */
930: int insn_needs[N_REG_CLASSES];
931: int insn_groups[N_REG_CLASSES];
932: int insn_total_groups = 0;
933:
934: /* Count RELOAD_FOR_INPUT reloads. */
935: int insn_needs_for_inputs[N_REG_CLASSES];
936: int insn_groups_for_inputs[N_REG_CLASSES];
937: int insn_total_groups_for_inputs = 0;
938:
939: /* Count RELOAD_FOR_OUTPUT reloads. */
940: int insn_needs_for_outputs[N_REG_CLASSES];
941: int insn_groups_for_outputs[N_REG_CLASSES];
942: int insn_total_groups_for_outputs = 0;
943:
944: /* Count RELOAD_FOR_INSN reloads. */
945: int insn_needs_for_insn[N_REG_CLASSES];
946: int insn_groups_for_insn[N_REG_CLASSES];
947: int insn_total_groups_for_insn = 0;
948:
949: /* Count RELOAD_FOR_OTHER_ADDRESS reloads. */
950: int insn_needs_for_other_addr[N_REG_CLASSES];
951: int insn_groups_for_other_addr[N_REG_CLASSES];
952: int insn_total_groups_for_other_addr = 0;
953:
954: /* Count RELOAD_FOR_INPUT_ADDRESS reloads. */
955: int insn_needs_for_in_addr[MAX_RECOG_OPERANDS][N_REG_CLASSES];
956: int insn_groups_for_in_addr[MAX_RECOG_OPERANDS][N_REG_CLASSES];
957: int insn_total_groups_for_in_addr[MAX_RECOG_OPERANDS];
958:
959: /* Count RELOAD_FOR_OUTPUT_ADDRESS reloads. */
960: int insn_needs_for_out_addr[MAX_RECOG_OPERANDS][N_REG_CLASSES];
961: int insn_groups_for_out_addr[MAX_RECOG_OPERANDS][N_REG_CLASSES];
962: int insn_total_groups_for_out_addr[MAX_RECOG_OPERANDS];
963:
964: /* Count RELOAD_FOR_OPERAND_ADDRESS reloads. */
965: int insn_needs_for_op_addr[N_REG_CLASSES];
966: int insn_groups_for_op_addr[N_REG_CLASSES];
967: int insn_total_groups_for_op_addr = 0;
968:
969: #if 0 /* This wouldn't work nowadays, since optimize_bit_field
970: looks for non-strict memory addresses. */
971: /* Optimization: a bit-field instruction whose field
972: happens to be a byte or halfword in memory
973: can be changed to a move instruction. */
974:
975: if (GET_CODE (PATTERN (insn)) == SET)
976: {
977: rtx dest = SET_DEST (PATTERN (insn));
978: rtx src = SET_SRC (PATTERN (insn));
979:
980: if (GET_CODE (dest) == ZERO_EXTRACT
981: || GET_CODE (dest) == SIGN_EXTRACT)
982: optimize_bit_field (PATTERN (insn), insn, reg_equiv_mem);
983: if (GET_CODE (src) == ZERO_EXTRACT
984: || GET_CODE (src) == SIGN_EXTRACT)
985: optimize_bit_field (PATTERN (insn), insn, reg_equiv_mem);
986: }
987: #endif
988:
989: /* If needed, eliminate any eliminable registers. */
990: if (num_eliminable)
991: did_elimination = eliminate_regs_in_insn (insn, 0);
992:
993: #ifdef SMALL_REGISTER_CLASSES
994: /* Set avoid_return_reg if this is an insn
995: that might use the value of a function call. */
996: if (GET_CODE (insn) == CALL_INSN)
997: {
998: if (GET_CODE (PATTERN (insn)) == SET)
999: after_call = SET_DEST (PATTERN (insn));
1000: else if (GET_CODE (PATTERN (insn)) == PARALLEL
1001: && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1002: after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
1003: else
1004: after_call = 0;
1005: }
1006: else if (after_call != 0
1007: && !(GET_CODE (PATTERN (insn)) == SET
1008: && SET_DEST (PATTERN (insn)) == stack_pointer_rtx))
1009: {
1010: if (reg_mentioned_p (after_call, PATTERN (insn)))
1011: avoid_return_reg = after_call;
1012: after_call = 0;
1013: }
1014: #endif /* SMALL_REGISTER_CLASSES */
1015:
1016: /* Analyze the instruction. */
1017: find_reloads (insn, 0, spill_indirect_levels, global,
1018: spill_reg_order);
1019:
1020: /* Remember for later shortcuts which insns had any reloads or
1021: register eliminations.
1022:
1023: One might think that it would be worthwhile to mark insns
1024: that need register replacements but not reloads, but this is
1025: not safe because find_reloads may do some manipulation of
1026: the insn (such as swapping commutative operands), which would
1027: be lost when we restore the old pattern after register
1028: replacement. So the actions of find_reloads must be redone in
1029: subsequent passes or in reload_as_needed.
1030:
1031: However, it is safe to mark insns that need reloads
1032: but not register replacement. */
1033:
1034: PUT_MODE (insn, (did_elimination ? QImode
1035: : n_reloads ? HImode
1036: : GET_MODE (insn) == DImode ? DImode
1037: : VOIDmode));
1038:
1039: /* Discard any register replacements done. */
1040: if (did_elimination)
1041: {
1042: obstack_free (&reload_obstack, reload_firstobj);
1043: PATTERN (insn) = old_body;
1044: INSN_CODE (insn) = old_code;
1045: REG_NOTES (insn) = old_notes;
1046: something_needs_elimination = 1;
1047: }
1048:
1049: /* If this insn has no reloads, we need not do anything except
1050: in the case of a CALL_INSN when we have caller-saves and
1051: caller-save needs reloads. */
1052:
1053: if (n_reloads == 0
1054: && ! (GET_CODE (insn) == CALL_INSN
1055: && caller_save_spill_class != NO_REGS))
1056: continue;
1057:
1058: something_needs_reloads = 1;
1059:
1060: for (i = 0; i < N_REG_CLASSES; i++)
1061: {
1062: insn_needs[i] = 0, insn_groups[i] = 0;
1063: insn_needs_for_inputs[i] = 0, insn_groups_for_inputs[i] = 0;
1064: insn_needs_for_outputs[i] = 0, insn_groups_for_outputs[i] = 0;
1065: insn_needs_for_insn[i] = 0, insn_groups_for_insn[i] = 0;
1066: insn_needs_for_op_addr[i] = 0, insn_groups_for_op_addr[i] = 0;
1067: insn_needs_for_other_addr[i] = 0;
1068: insn_groups_for_other_addr[i] = 0;
1069: }
1070:
1071: for (i = 0; i < reload_n_operands; i++)
1072: {
1073: insn_total_groups_for_in_addr[i] = 0;
1074: insn_total_groups_for_out_addr[i] = 0;
1075:
1076: for (j = 0; j < N_REG_CLASSES; j++)
1077: {
1078: insn_needs_for_in_addr[i][j] = 0;
1079: insn_needs_for_out_addr[i][j] = 0;
1080: insn_groups_for_in_addr[i][j] = 0;
1081: insn_groups_for_out_addr[i][j] = 0;
1082: }
1083: }
1084:
1085: /* Count each reload once in every class
1086: containing the reload's own class. */
1087:
1088: for (i = 0; i < n_reloads; i++)
1089: {
1090: register enum reg_class *p;
1091: enum reg_class class = reload_reg_class[i];
1092: int size;
1093: enum machine_mode mode;
1094: int *this_groups;
1095: int *this_needs;
1096: int *this_total_groups;
1097:
1098: /* Don't count the dummy reloads, for which one of the
1099: regs mentioned in the insn can be used for reloading.
1100: Don't count optional reloads.
1101: Don't count reloads that got combined with others. */
1102: if (reload_reg_rtx[i] != 0
1103: || reload_optional[i] != 0
1104: || (reload_out[i] == 0 && reload_in[i] == 0
1105: && ! reload_secondary_p[i]))
1106: continue;
1107:
1108: /* Show that a reload register of this class is needed
1109: in this basic block. We do not use insn_needs and
1110: insn_groups because they are overly conservative for
1111: this purpose. */
1112: if (global && ! basic_block_needs[(int) class][this_block])
1113: {
1114: basic_block_needs[(int) class][this_block] = 1;
1115: new_basic_block_needs = 1;
1116: }
1117:
1118: /* Decide which time-of-use to count this reload for. */
1119: switch (reload_when_needed[i])
1120: {
1121: case RELOAD_OTHER:
1122: this_needs = insn_needs;
1123: this_groups = insn_groups;
1124: this_total_groups = &insn_total_groups;
1125: break;
1126:
1127: case RELOAD_FOR_INPUT:
1128: this_needs = insn_needs_for_inputs;
1129: this_groups = insn_groups_for_inputs;
1130: this_total_groups = &insn_total_groups_for_inputs;
1131: break;
1132:
1133: case RELOAD_FOR_OUTPUT:
1134: this_needs = insn_needs_for_outputs;
1135: this_groups = insn_groups_for_outputs;
1136: this_total_groups = &insn_total_groups_for_outputs;
1137: break;
1138:
1139: case RELOAD_FOR_INSN:
1140: this_needs = insn_needs_for_insn;
1141: this_groups = insn_groups_for_insn;
1142: this_total_groups = &insn_total_groups_for_insn;
1143: break;
1144:
1145: case RELOAD_FOR_OTHER_ADDRESS:
1146: this_needs = insn_needs_for_other_addr;
1147: this_groups = insn_groups_for_other_addr;
1148: this_total_groups = &insn_total_groups_for_other_addr;
1149: break;
1150:
1151: case RELOAD_FOR_INPUT_ADDRESS:
1152: this_needs = insn_needs_for_in_addr[reload_opnum[i]];
1153: this_groups = insn_groups_for_in_addr[reload_opnum[i]];
1154: this_total_groups
1155: = &insn_total_groups_for_in_addr[reload_opnum[i]];
1156: break;
1157:
1158: case RELOAD_FOR_OUTPUT_ADDRESS:
1159: this_needs = insn_needs_for_out_addr[reload_opnum[i]];
1160: this_groups = insn_groups_for_out_addr[reload_opnum[i]];
1161: this_total_groups
1162: = &insn_total_groups_for_out_addr[reload_opnum[i]];
1163: break;
1164:
1165: case RELOAD_FOR_OPERAND_ADDRESS:
1166: this_needs = insn_needs_for_op_addr;
1167: this_groups = insn_groups_for_op_addr;
1168: this_total_groups = &insn_total_groups_for_op_addr;
1169: break;
1170: }
1171:
1172: mode = reload_inmode[i];
1173: if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode))
1174: mode = reload_outmode[i];
1175: size = CLASS_MAX_NREGS (class, mode);
1176: if (size > 1)
1177: {
1178: enum machine_mode other_mode, allocate_mode;
1179:
1180: /* Count number of groups needed separately from
1181: number of individual regs needed. */
1182: this_groups[(int) class]++;
1183: p = reg_class_superclasses[(int) class];
1184: while (*p != LIM_REG_CLASSES)
1185: this_groups[(int) *p++]++;
1186: (*this_total_groups)++;
1187:
1188: /* Record size and mode of a group of this class. */
1189: /* If more than one size group is needed,
1190: make all groups the largest needed size. */
1191: if (group_size[(int) class] < size)
1192: {
1193: other_mode = group_mode[(int) class];
1194: allocate_mode = mode;
1195:
1196: group_size[(int) class] = size;
1197: group_mode[(int) class] = mode;
1198: }
1199: else
1200: {
1201: other_mode = mode;
1202: allocate_mode = group_mode[(int) class];
1203: }
1204:
1205: /* Crash if two dissimilar machine modes both need
1206: groups of consecutive regs of the same class. */
1207:
1208: if (other_mode != VOIDmode
1209: && other_mode != allocate_mode
1210: && ! modes_equiv_for_class_p (allocate_mode,
1211: other_mode,
1212: class))
1213: abort ();
1214: }
1215: else if (size == 1)
1216: {
1217: this_needs[(int) class] += 1;
1218: p = reg_class_superclasses[(int) class];
1219: while (*p != LIM_REG_CLASSES)
1220: this_needs[(int) *p++] += 1;
1221: }
1222: else
1223: abort ();
1224: }
1225:
1226: /* All reloads have been counted for this insn;
1227: now merge the various times of use.
1228: This sets insn_needs, etc., to the maximum total number
1229: of registers needed at any point in this insn. */
1230:
1231: for (i = 0; i < N_REG_CLASSES; i++)
1232: {
1233: int in_max, out_max;
1234:
1235: for (in_max = 0, out_max = 0, j = 0;
1236: j < reload_n_operands; j++)
1237: {
1238: in_max = MAX (in_max, insn_needs_for_in_addr[j][i]);
1239: out_max = MAX (out_max, insn_needs_for_out_addr[j][i]);
1240: }
1241:
1242: /* RELOAD_FOR_INSN reloads conflict with inputs, outputs,
1243: and operand addresses but not things used to reload them.
1244: Similarly, RELOAD_FOR_OPERAND_ADDRESS reloads don't
1245: conflict with things needed to reload inputs or
1246: outputs. */
1247:
1248: in_max = MAX (in_max, insn_needs_for_op_addr[i]);
1249: out_max = MAX (out_max, insn_needs_for_insn[i]);
1250:
1251: insn_needs_for_inputs[i]
1252: = MAX (insn_needs_for_inputs[i]
1253: + insn_needs_for_op_addr[i]
1254: + insn_needs_for_insn[i],
1255: in_max + insn_needs_for_inputs[i]);
1256:
1257: insn_needs_for_outputs[i] += out_max;
1258: insn_needs[i] += MAX (MAX (insn_needs_for_inputs[i],
1259: insn_needs_for_outputs[i]),
1260: insn_needs_for_other_addr[i]);
1261:
1262: for (in_max = 0, out_max = 0, j = 0;
1263: j < reload_n_operands; j++)
1264: {
1265: in_max = MAX (in_max, insn_groups_for_in_addr[j][i]);
1266: out_max = MAX (out_max, insn_groups_for_out_addr[j][i]);
1267: }
1268:
1269: in_max = MAX (in_max, insn_groups_for_op_addr[i]);
1270: out_max = MAX (out_max, insn_groups_for_insn[i]);
1271:
1272: insn_groups_for_inputs[i]
1273: = MAX (insn_groups_for_inputs[i]
1274: + insn_groups_for_op_addr[i]
1275: + insn_groups_for_insn[i],
1276: in_max + insn_groups_for_inputs[i]);
1277:
1278: insn_groups_for_outputs[i] += out_max;
1279: insn_groups[i] += MAX (MAX (insn_groups_for_inputs[i],
1280: insn_groups_for_outputs[i]),
1281: insn_groups_for_other_addr[i]);
1282: }
1283:
1284: for (i = 0; i < reload_n_operands; i++)
1285: {
1286: max_total_input_groups
1287: = MAX (max_total_input_groups,
1288: insn_total_groups_for_in_addr[i]);
1289: max_total_output_groups
1290: = MAX (max_total_output_groups,
1291: insn_total_groups_for_out_addr[i]);
1292: }
1293:
1294: max_total_input_groups = MAX (max_total_input_groups,
1295: insn_total_groups_for_op_addr);
1296: max_total_output_groups = MAX (max_total_output_groups,
1297: insn_total_groups_for_insn);
1298:
1299: insn_total_groups_for_inputs
1300: = MAX (max_total_input_groups + insn_total_groups_for_op_addr
1301: + insn_total_groups_for_insn,
1302: max_total_input_groups + insn_total_groups_for_inputs);
1303:
1304: insn_total_groups_for_outputs += max_total_output_groups;
1305:
1306: insn_total_groups += MAX (MAX (insn_total_groups_for_outputs,
1307: insn_total_groups_for_inputs),
1308: insn_total_groups_for_other_addr);
1309:
1310: /* If this is a CALL_INSN and caller-saves will need
1311: a spill register, act as if the spill register is
1312: needed for this insn. However, the spill register
1313: can be used by any reload of this insn, so we only
1314: need do something if no need for that class has
1315: been recorded.
1316:
1317: The assumption that every CALL_INSN will trigger a
1318: caller-save is highly conservative, however, the number
1319: of cases where caller-saves will need a spill register but
1320: a block containing a CALL_INSN won't need a spill register
1321: of that class should be quite rare.
1322:
1323: If a group is needed, the size and mode of the group will
1324: have been set up at the beginning of this loop. */
1325:
1326: if (GET_CODE (insn) == CALL_INSN
1327: && caller_save_spill_class != NO_REGS)
1328: {
1329: int *caller_save_needs
1330: = (caller_save_group_size > 1 ? insn_groups : insn_needs);
1331:
1332: if (caller_save_needs[(int) caller_save_spill_class] == 0)
1333: {
1334: register enum reg_class *p
1335: = reg_class_superclasses[(int) caller_save_spill_class];
1336:
1337: caller_save_needs[(int) caller_save_spill_class]++;
1338:
1339: while (*p != LIM_REG_CLASSES)
1340: caller_save_needs[(int) *p++] += 1;
1341: }
1342:
1343: if (caller_save_group_size > 1)
1344: insn_total_groups = MAX (insn_total_groups, 1);
1345:
1346:
1347: /* Show that this basic block will need a register of
1348: this class. */
1349:
1350: if (global
1351: && ! (basic_block_needs[(int) caller_save_spill_class]
1352: [this_block]))
1353: {
1354: basic_block_needs[(int) caller_save_spill_class]
1355: [this_block] = 1;
1356: new_basic_block_needs = 1;
1357: }
1358: }
1359:
1360: #ifdef SMALL_REGISTER_CLASSES
1361: /* If this insn stores the value of a function call,
1362: and that value is in a register that has been spilled,
1363: and if the insn needs a reload in a class
1364: that might use that register as the reload register,
1365: then add add an extra need in that class.
1366: This makes sure we have a register available that does
1367: not overlap the return value. */
1368: if (avoid_return_reg)
1369: {
1370: int regno = REGNO (avoid_return_reg);
1371: int nregs
1372: = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
1373: int r;
1374: int basic_needs[N_REG_CLASSES], basic_groups[N_REG_CLASSES];
1375:
1376: /* First compute the "basic needs", which counts a
1377: need only in the smallest class in which it
1378: is required. */
1379:
1380: bcopy (insn_needs, basic_needs, sizeof basic_needs);
1381: bcopy (insn_groups, basic_groups, sizeof basic_groups);
1382:
1383: for (i = 0; i < N_REG_CLASSES; i++)
1384: {
1385: enum reg_class *p;
1386:
1387: if (basic_needs[i] >= 0)
1388: for (p = reg_class_superclasses[i];
1389: *p != LIM_REG_CLASSES; p++)
1390: basic_needs[(int) *p] -= basic_needs[i];
1391:
1392: if (basic_groups[i] >= 0)
1393: for (p = reg_class_superclasses[i];
1394: *p != LIM_REG_CLASSES; p++)
1395: basic_groups[(int) *p] -= basic_groups[i];
1396: }
1397:
1398: /* Now count extra regs if there might be a conflict with
1399: the return value register.
1400:
1401: ??? This is not quite correct because we don't properly
1402: handle the case of groups, but if we end up doing
1403: something wrong, it either will end up not mattering or
1404: we will abort elsewhere. */
1405:
1406: for (r = regno; r < regno + nregs; r++)
1407: if (spill_reg_order[r] >= 0)
1408: for (i = 0; i < N_REG_CLASSES; i++)
1409: if (TEST_HARD_REG_BIT (reg_class_contents[i], r))
1410: {
1411: if (basic_needs[i] > 0 || basic_groups[i] > 0)
1412: {
1413: enum reg_class *p;
1414:
1415: insn_needs[i]++;
1416: p = reg_class_superclasses[i];
1417: while (*p != LIM_REG_CLASSES)
1418: insn_needs[(int) *p++]++;
1419: }
1420: }
1421: }
1422: #endif /* SMALL_REGISTER_CLASSES */
1423:
1424: /* For each class, collect maximum need of any insn. */
1425:
1426: for (i = 0; i < N_REG_CLASSES; i++)
1427: {
1428: if (max_needs[i] < insn_needs[i])
1429: {
1430: max_needs[i] = insn_needs[i];
1431: max_needs_insn[i] = insn;
1432: }
1433: if (max_groups[i] < insn_groups[i])
1434: {
1435: max_groups[i] = insn_groups[i];
1436: max_groups_insn[i] = insn;
1437: }
1438: if (insn_total_groups > 0)
1439: if (max_nongroups[i] < insn_needs[i])
1440: {
1441: max_nongroups[i] = insn_needs[i];
1442: max_nongroups_insn[i] = insn;
1443: }
1444: }
1445: }
1446: /* Note that there is a continue statement above. */
1447: }
1448:
1449: /* If we allocated any new memory locations, make another pass
1450: since it might have changed elimination offsets. */
1451: if (starting_frame_size != get_frame_size ())
1452: something_changed = 1;
1453:
1454: if (dumpfile)
1455: for (i = 0; i < N_REG_CLASSES; i++)
1456: {
1457: if (max_needs[i] > 0)
1458: fprintf (dumpfile,
1459: ";; Need %d reg%s of class %s (for insn %d).\n",
1460: max_needs[i], max_needs[i] == 1 ? "" : "s",
1461: reg_class_names[i], INSN_UID (max_needs_insn[i]));
1462: if (max_nongroups[i] > 0)
1463: fprintf (dumpfile,
1464: ";; Need %d nongroup reg%s of class %s (for insn %d).\n",
1465: max_nongroups[i], max_nongroups[i] == 1 ? "" : "s",
1466: reg_class_names[i], INSN_UID (max_nongroups_insn[i]));
1467: if (max_groups[i] > 0)
1468: fprintf (dumpfile,
1469: ";; Need %d group%s (%smode) of class %s (for insn %d).\n",
1470: max_groups[i], max_groups[i] == 1 ? "" : "s",
1471: mode_name[(int) group_mode[i]],
1472: reg_class_names[i], INSN_UID (max_groups_insn[i]));
1473: }
1474:
1475: /* If we have caller-saves, set up the save areas and see if caller-save
1476: will need a spill register. */
1477:
1478: if (caller_save_needed
1479: && ! setup_save_areas (&something_changed)
1480: && caller_save_spill_class == NO_REGS)
1481: {
1482: /* The class we will need depends on whether the machine
1483: supports the sum of two registers for an address; see
1484: find_address_reloads for details. */
1485:
1486: caller_save_spill_class
1487: = double_reg_address_ok ? INDEX_REG_CLASS : BASE_REG_CLASS;
1488: caller_save_group_size
1489: = CLASS_MAX_NREGS (caller_save_spill_class, Pmode);
1490: something_changed = 1;
1491: }
1492:
1493: /* See if anything that happened changes which eliminations are valid.
1494: For example, on the Sparc, whether or not the frame pointer can
1495: be eliminated can depend on what registers have been used. We need
1496: not check some conditions again (such as flag_omit_frame_pointer)
1497: since they can't have changed. */
1498:
1499: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1500: if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
1501: #ifdef ELIMINABLE_REGS
1502: || ! CAN_ELIMINATE (ep->from, ep->to)
1503: #endif
1504: )
1505: ep->can_eliminate = 0;
1506:
1507: /* Look for the case where we have discovered that we can't replace
1508: register A with register B and that means that we will now be
1509: trying to replace register A with register C. This means we can
1510: no longer replace register C with register B and we need to disable
1511: such an elimination, if it exists. This occurs often with A == ap,
1512: B == sp, and C == fp. */
1513:
1514: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1515: {
1516: struct elim_table *op;
1517: register int new_to = -1;
1518:
1519: if (! ep->can_eliminate && ep->can_eliminate_previous)
1520: {
1521: /* Find the current elimination for ep->from, if there is a
1522: new one. */
1523: for (op = reg_eliminate;
1524: op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1525: if (op->from == ep->from && op->can_eliminate)
1526: {
1527: new_to = op->to;
1528: break;
1529: }
1530:
1531: /* See if there is an elimination of NEW_TO -> EP->TO. If so,
1532: disable it. */
1533: for (op = reg_eliminate;
1534: op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1535: if (op->from == new_to && op->to == ep->to)
1536: op->can_eliminate = 0;
1537: }
1538: }
1539:
1540: /* See if any registers that we thought we could eliminate the previous
1541: time are no longer eliminable. If so, something has changed and we
1542: must spill the register. Also, recompute the number of eliminable
1543: registers and see if the frame pointer is needed; it is if there is
1544: no elimination of the frame pointer that we can perform. */
1545:
1546: frame_pointer_needed = 1;
1547: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1548: {
1549: if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
1550: && ep->to != HARD_FRAME_POINTER_REGNUM)
1551: frame_pointer_needed = 0;
1552:
1553: if (! ep->can_eliminate && ep->can_eliminate_previous)
1554: {
1555: ep->can_eliminate_previous = 0;
1556: spill_hard_reg (ep->from, global, dumpfile, 1);
1557: regs_ever_live[ep->from] = 1;
1558: something_changed = 1;
1559: num_eliminable--;
1560: }
1561: }
1562:
1563: /* If all needs are met, we win. */
1564:
1565: for (i = 0; i < N_REG_CLASSES; i++)
1566: if (max_needs[i] > 0 || max_groups[i] > 0 || max_nongroups[i] > 0)
1567: break;
1568: if (i == N_REG_CLASSES && !new_basic_block_needs && ! something_changed)
1569: break;
1570:
1571: /* Not all needs are met; must spill some hard regs. */
1572:
1573: /* Put all registers spilled so far back in potential_reload_regs, but
1574: put them at the front, since we've already spilled most of the
1575: psuedos in them (we might have left some pseudos unspilled if they
1576: were in a block that didn't need any spill registers of a conflicting
1577: class. We used to try to mark off the need for those registers,
1578: but doing so properly is very complex and reallocating them is the
1579: simpler approach. First, "pack" potential_reload_regs by pushing
1580: any nonnegative entries towards the end. That will leave room
1581: for the registers we already spilled.
1582:
1583: Also, undo the marking of the spill registers from the last time
1584: around in FORBIDDEN_REGS since we will be probably be allocating
1585: them again below.
1586:
1587: ??? It is theoretically possible that we might end up not using one
1588: of our previously-spilled registers in this allocation, even though
1589: they are at the head of the list. It's not clear what to do about
1590: this, but it was no better before, when we marked off the needs met
1591: by the previously-spilled registers. With the current code, globals
1592: can be allocated into these registers, but locals cannot. */
1593:
1594: if (n_spills)
1595: {
1596: for (i = j = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
1597: if (potential_reload_regs[i] != -1)
1598: potential_reload_regs[j--] = potential_reload_regs[i];
1599:
1600: for (i = 0; i < n_spills; i++)
1601: {
1602: potential_reload_regs[i] = spill_regs[i];
1603: spill_reg_order[spill_regs[i]] = -1;
1604: CLEAR_HARD_REG_BIT (forbidden_regs, spill_regs[i]);
1605: }
1606:
1607: n_spills = 0;
1608: }
1609:
1610: /* Now find more reload regs to satisfy the remaining need
1611: Do it by ascending class number, since otherwise a reg
1612: might be spilled for a big class and might fail to count
1613: for a smaller class even though it belongs to that class.
1614:
1615: Count spilled regs in `spills', and add entries to
1616: `spill_regs' and `spill_reg_order'.
1617:
1618: ??? Note there is a problem here.
1619: When there is a need for a group in a high-numbered class,
1620: and also need for non-group regs that come from a lower class,
1621: the non-group regs are chosen first. If there aren't many regs,
1622: they might leave no room for a group.
1623:
1624: This was happening on the 386. To fix it, we added the code
1625: that calls possible_group_p, so that the lower class won't
1626: break up the last possible group.
1627:
1628: Really fixing the problem would require changes above
1629: in counting the regs already spilled, and in choose_reload_regs.
1630: It might be hard to avoid introducing bugs there. */
1631:
1632: CLEAR_HARD_REG_SET (counted_for_groups);
1633: CLEAR_HARD_REG_SET (counted_for_nongroups);
1634:
1635: for (class = 0; class < N_REG_CLASSES; class++)
1636: {
1637: /* First get the groups of registers.
1638: If we got single registers first, we might fragment
1639: possible groups. */
1640: while (max_groups[class] > 0)
1641: {
1642: /* If any single spilled regs happen to form groups,
1643: count them now. Maybe we don't really need
1644: to spill another group. */
1645: count_possible_groups (group_size, group_mode, max_groups);
1646:
1647: if (max_groups[class] <= 0)
1648: break;
1649:
1650: /* Groups of size 2 (the only groups used on most machines)
1651: are treated specially. */
1652: if (group_size[class] == 2)
1653: {
1654: /* First, look for a register that will complete a group. */
1655: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1656: {
1657: int other;
1658:
1659: j = potential_reload_regs[i];
1660: if (j >= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs, j)
1661: &&
1662: ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0)
1663: && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1664: && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1665: && HARD_REGNO_MODE_OK (other, group_mode[class])
1666: && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1667: other)
1668: /* We don't want one part of another group.
1669: We could get "two groups" that overlap! */
1670: && ! TEST_HARD_REG_BIT (counted_for_groups, other))
1671: ||
1672: (j < FIRST_PSEUDO_REGISTER - 1
1673: && (other = j + 1, spill_reg_order[other] >= 0)
1674: && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1675: && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1676: && HARD_REGNO_MODE_OK (j, group_mode[class])
1677: && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1678: other)
1679: && ! TEST_HARD_REG_BIT (counted_for_groups,
1680: other))))
1681: {
1682: register enum reg_class *p;
1683:
1684: /* We have found one that will complete a group,
1685: so count off one group as provided. */
1686: max_groups[class]--;
1687: p = reg_class_superclasses[class];
1688: while (*p != LIM_REG_CLASSES)
1689: max_groups[(int) *p++]--;
1690:
1691: /* Indicate both these regs are part of a group. */
1692: SET_HARD_REG_BIT (counted_for_groups, j);
1693: SET_HARD_REG_BIT (counted_for_groups, other);
1694: break;
1695: }
1696: }
1697: /* We can't complete a group, so start one. */
1698: #ifdef SMALL_REGISTER_CLASSES
1699: /* Look for a pair neither of which is explicitly used. */
1700: if (i == FIRST_PSEUDO_REGISTER)
1701: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1702: {
1703: int k;
1704: j = potential_reload_regs[i];
1705: /* Verify that J+1 is a potential reload reg. */
1706: for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1707: if (potential_reload_regs[k] == j + 1)
1708: break;
1709: if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1710: && k < FIRST_PSEUDO_REGISTER
1711: && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1712: && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1713: && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1714: && HARD_REGNO_MODE_OK (j, group_mode[class])
1715: && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1716: j + 1)
1717: && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1)
1718: /* Reject J at this stage
1719: if J+1 was explicitly used. */
1720: && ! regs_explicitly_used[j + 1])
1721: break;
1722: }
1723: #endif
1724: /* Now try any group at all
1725: whose registers are not in bad_spill_regs. */
1726: if (i == FIRST_PSEUDO_REGISTER)
1727: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1728: {
1729: int k;
1730: j = potential_reload_regs[i];
1731: /* Verify that J+1 is a potential reload reg. */
1732: for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1733: if (potential_reload_regs[k] == j + 1)
1734: break;
1735: if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1736: && k < FIRST_PSEUDO_REGISTER
1737: && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1738: && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1739: && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1740: && HARD_REGNO_MODE_OK (j, group_mode[class])
1741: && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1742: j + 1)
1743: && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1))
1744: break;
1745: }
1746:
1747: /* I should be the index in potential_reload_regs
1748: of the new reload reg we have found. */
1749:
1750: if (i >= FIRST_PSEUDO_REGISTER)
1751: {
1752: /* There are no groups left to spill. */
1753: spill_failure (max_groups_insn[class]);
1754: failure = 1;
1755: goto failed;
1756: }
1757: else
1758: something_changed
1759: |= new_spill_reg (i, class, max_needs, NULL_PTR,
1760: global, dumpfile);
1761: }
1762: else
1763: {
1764: /* For groups of more than 2 registers,
1765: look for a sufficient sequence of unspilled registers,
1766: and spill them all at once. */
1767: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1768: {
1769: int k;
1770:
1771: j = potential_reload_regs[i];
1772: if (j >= 0
1773: && j + group_size[class] <= FIRST_PSEUDO_REGISTER
1774: && HARD_REGNO_MODE_OK (j, group_mode[class]))
1775: {
1776: /* Check each reg in the sequence. */
1777: for (k = 0; k < group_size[class]; k++)
1778: if (! (spill_reg_order[j + k] < 0
1779: && ! TEST_HARD_REG_BIT (bad_spill_regs, j + k)
1780: && TEST_HARD_REG_BIT (reg_class_contents[class], j + k)))
1781: break;
1782: /* We got a full sequence, so spill them all. */
1783: if (k == group_size[class])
1784: {
1785: register enum reg_class *p;
1786: for (k = 0; k < group_size[class]; k++)
1787: {
1788: int idx;
1789: SET_HARD_REG_BIT (counted_for_groups, j + k);
1790: for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
1791: if (potential_reload_regs[idx] == j + k)
1792: break;
1793: something_changed
1794: |= new_spill_reg (idx, class,
1795: max_needs, NULL_PTR,
1796: global, dumpfile);
1797: }
1798:
1799: /* We have found one that will complete a group,
1800: so count off one group as provided. */
1801: max_groups[class]--;
1802: p = reg_class_superclasses[class];
1803: while (*p != LIM_REG_CLASSES)
1804: max_groups[(int) *p++]--;
1805:
1806: break;
1807: }
1808: }
1809: }
1810: /* We couldn't find any registers for this reload.
1811: Avoid going into an infinite loop. */
1812: if (i >= FIRST_PSEUDO_REGISTER)
1813: {
1814: /* There are no groups left. */
1815: spill_failure (max_groups_insn[class]);
1816: failure = 1;
1817: goto failed;
1818: }
1819: }
1820: }
1821:
1822: /* Now similarly satisfy all need for single registers. */
1823:
1824: while (max_needs[class] > 0 || max_nongroups[class] > 0)
1825: {
1826: #ifdef SMALL_REGISTER_CLASSES
1827: /* This should be right for all machines, but only the 386
1828: is known to need it, so this conditional plays safe.
1829: ??? For 2.5, try making this unconditional. */
1830: /* If we spilled enough regs, but they weren't counted
1831: against the non-group need, see if we can count them now.
1832: If so, we can avoid some actual spilling. */
1833: if (max_needs[class] <= 0 && max_nongroups[class] > 0)
1834: for (i = 0; i < n_spills; i++)
1835: if (TEST_HARD_REG_BIT (reg_class_contents[class],
1836: spill_regs[i])
1837: && !TEST_HARD_REG_BIT (counted_for_groups,
1838: spill_regs[i])
1839: && !TEST_HARD_REG_BIT (counted_for_nongroups,
1840: spill_regs[i])
1841: && max_nongroups[class] > 0)
1842: {
1843: register enum reg_class *p;
1844:
1845: SET_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]);
1846: max_nongroups[class]--;
1847: p = reg_class_superclasses[class];
1848: while (*p != LIM_REG_CLASSES)
1849: max_nongroups[(int) *p++]--;
1850: }
1851: if (max_needs[class] <= 0 && max_nongroups[class] <= 0)
1852: break;
1853: #endif
1854:
1855: /* Consider the potential reload regs that aren't
1856: yet in use as reload regs, in order of preference.
1857: Find the most preferred one that's in this class. */
1858:
1859: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1860: if (potential_reload_regs[i] >= 0
1861: && TEST_HARD_REG_BIT (reg_class_contents[class],
1862: potential_reload_regs[i])
1863: /* If this reg will not be available for groups,
1864: pick one that does not foreclose possible groups.
1865: This is a kludge, and not very general,
1866: but it should be sufficient to make the 386 work,
1867: and the problem should not occur on machines with
1868: more registers. */
1869: && (max_nongroups[class] == 0
1870: || possible_group_p (potential_reload_regs[i], max_groups)))
1871: break;
1872:
1873: /* If we couldn't get a register, try to get one even if we
1874: might foreclose possible groups. This may cause problems
1875: later, but that's better than aborting now, since it is
1876: possible that we will, in fact, be able to form the needed
1877: group even with this allocation. */
1878:
1879: if (i >= FIRST_PSEUDO_REGISTER
1880: && (asm_noperands (max_needs[class] > 0
1881: ? max_needs_insn[class]
1882: : max_nongroups_insn[class])
1883: < 0))
1884: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1885: if (potential_reload_regs[i] >= 0
1886: && TEST_HARD_REG_BIT (reg_class_contents[class],
1887: potential_reload_regs[i]))
1888: break;
1889:
1890: /* I should be the index in potential_reload_regs
1891: of the new reload reg we have found. */
1892:
1893: if (i >= FIRST_PSEUDO_REGISTER)
1894: {
1895: /* There are no possible registers left to spill. */
1896: spill_failure (max_needs[class] > 0 ? max_needs_insn[class]
1897: : max_nongroups_insn[class]);
1898: failure = 1;
1899: goto failed;
1900: }
1901: else
1902: something_changed
1903: |= new_spill_reg (i, class, max_needs, max_nongroups,
1904: global, dumpfile);
1905: }
1906: }
1907: }
1908:
1909: /* If global-alloc was run, notify it of any register eliminations we have
1910: done. */
1911: if (global)
1912: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1913: if (ep->can_eliminate)
1914: mark_elimination (ep->from, ep->to);
1915:
1916: /* Insert code to save and restore call-clobbered hard regs
1917: around calls. Tell if what mode to use so that we will process
1918: those insns in reload_as_needed if we have to. */
1919:
1920: if (caller_save_needed)
1921: save_call_clobbered_regs (num_eliminable ? QImode
1922: : caller_save_spill_class != NO_REGS ? HImode
1923: : VOIDmode);
1924:
1925: /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1926: If that insn didn't set the register (i.e., it copied the register to
1927: memory), just delete that insn instead of the equivalencing insn plus
1928: anything now dead. If we call delete_dead_insn on that insn, we may
1929: delete the insn that actually sets the register if the register die
1930: there and that is incorrect. */
1931:
1932: for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1933: if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0
1934: && GET_CODE (reg_equiv_init[i]) != NOTE)
1935: {
1936: if (reg_set_p (regno_reg_rtx[i], PATTERN (reg_equiv_init[i])))
1937: delete_dead_insn (reg_equiv_init[i]);
1938: else
1939: {
1940: PUT_CODE (reg_equiv_init[i], NOTE);
1941: NOTE_SOURCE_FILE (reg_equiv_init[i]) = 0;
1942: NOTE_LINE_NUMBER (reg_equiv_init[i]) = NOTE_INSN_DELETED;
1943: }
1944: }
1945:
1946: /* Use the reload registers where necessary
1947: by generating move instructions to move the must-be-register
1948: values into or out of the reload registers. */
1949:
1950: if (something_needs_reloads || something_needs_elimination
1951: || (caller_save_needed && num_eliminable)
1952: || caller_save_spill_class != NO_REGS)
1953: reload_as_needed (first, global);
1954:
1955: /* If we were able to eliminate the frame pointer, show that it is no
1956: longer live at the start of any basic block. If it ls live by
1957: virtue of being in a pseudo, that pseudo will be marked live
1958: and hence the frame pointer will be known to be live via that
1959: pseudo. */
1960:
1961: if (! frame_pointer_needed)
1962: for (i = 0; i < n_basic_blocks; i++)
1963: basic_block_live_at_start[i][HARD_FRAME_POINTER_REGNUM / REGSET_ELT_BITS]
1964: &= ~ ((REGSET_ELT_TYPE) 1 << (HARD_FRAME_POINTER_REGNUM
1965: % REGSET_ELT_BITS));
1966:
1967: /* Come here (with failure set nonzero) if we can't get enough spill regs
1968: and we decide not to abort about it. */
1969: failed:
1970:
1971: reload_in_progress = 0;
1972:
1973: /* Now eliminate all pseudo regs by modifying them into
1974: their equivalent memory references.
1975: The REG-rtx's for the pseudos are modified in place,
1976: so all insns that used to refer to them now refer to memory.
1977:
1978: For a reg that has a reg_equiv_address, all those insns
1979: were changed by reloading so that no insns refer to it any longer;
1980: but the DECL_RTL of a variable decl may refer to it,
1981: and if so this causes the debugging info to mention the variable. */
1982:
1983: for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1984: {
1985: rtx addr = 0;
1986: int in_struct = 0;
1987: if (reg_equiv_mem[i])
1988: {
1989: addr = XEXP (reg_equiv_mem[i], 0);
1990: in_struct = MEM_IN_STRUCT_P (reg_equiv_mem[i]);
1991: }
1992: if (reg_equiv_address[i])
1993: addr = reg_equiv_address[i];
1994: if (addr)
1995: {
1996: if (reg_renumber[i] < 0)
1997: {
1998: rtx reg = regno_reg_rtx[i];
1999: XEXP (reg, 0) = addr;
2000: REG_USERVAR_P (reg) = 0;
2001: MEM_IN_STRUCT_P (reg) = in_struct;
2002: PUT_CODE (reg, MEM);
2003: }
2004: else if (reg_equiv_mem[i])
2005: XEXP (reg_equiv_mem[i], 0) = addr;
2006: }
2007: }
2008:
2009: #ifdef PRESERVE_DEATH_INFO_REGNO_P
2010: /* Make a pass over all the insns and remove death notes for things that
2011: are no longer registers or no longer die in the insn (e.g., an input
2012: and output pseudo being tied). */
2013:
2014: for (insn = first; insn; insn = NEXT_INSN (insn))
2015: if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
2016: {
2017: rtx note, next;
2018:
2019: for (note = REG_NOTES (insn); note; note = next)
2020: {
2021: next = XEXP (note, 1);
2022: if (REG_NOTE_KIND (note) == REG_DEAD
2023: && (GET_CODE (XEXP (note, 0)) != REG
2024: || reg_set_p (XEXP (note, 0), PATTERN (insn))))
2025: remove_note (insn, note);
2026: }
2027: }
2028: #endif
2029:
2030: /* Indicate that we no longer have known memory locations or constants. */
2031: reg_equiv_constant = 0;
2032: reg_equiv_memory_loc = 0;
2033:
2034: if (scratch_list)
2035: free (scratch_list);
2036: scratch_list = 0;
2037: scratch_list_length = 0;
2038: if (scratch_block)
2039: free (scratch_block);
2040: scratch_block = 0;
2041:
2042: return failure;
2043: }
2044:
2045: /* Nonzero if, after spilling reg REGNO for non-groups,
2046: it will still be possible to find a group if we still need one. */
2047:
2048: static int
2049: possible_group_p (regno, max_groups)
2050: int regno;
2051: int *max_groups;
2052: {
2053: int i;
2054: int class = (int) NO_REGS;
2055:
2056: for (i = 0; i < (int) N_REG_CLASSES; i++)
2057: if (max_groups[i] > 0)
2058: {
2059: class = i;
2060: break;
2061: }
2062:
2063: if (class == (int) NO_REGS)
2064: return 1;
2065:
2066: /* Consider each pair of consecutive registers. */
2067: for (i = 0; i < FIRST_PSEUDO_REGISTER - 1; i++)
2068: {
2069: /* Ignore pairs that include reg REGNO. */
2070: if (i == regno || i + 1 == regno)
2071: continue;
2072:
2073: /* Ignore pairs that are outside the class that needs the group.
2074: ??? Here we fail to handle the case where two different classes
2075: independently need groups. But this never happens with our
2076: current machine descriptions. */
2077: if (! (TEST_HARD_REG_BIT (reg_class_contents[class], i)
2078: && TEST_HARD_REG_BIT (reg_class_contents[class], i + 1)))
2079: continue;
2080:
2081: /* A pair of consecutive regs we can still spill does the trick. */
2082: if (spill_reg_order[i] < 0 && spill_reg_order[i + 1] < 0
2083: && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2084: && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1))
2085: return 1;
2086:
2087: /* A pair of one already spilled and one we can spill does it
2088: provided the one already spilled is not otherwise reserved. */
2089: if (spill_reg_order[i] < 0
2090: && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2091: && spill_reg_order[i + 1] >= 0
2092: && ! TEST_HARD_REG_BIT (counted_for_groups, i + 1)
2093: && ! TEST_HARD_REG_BIT (counted_for_nongroups, i + 1))
2094: return 1;
2095: if (spill_reg_order[i + 1] < 0
2096: && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1)
2097: && spill_reg_order[i] >= 0
2098: && ! TEST_HARD_REG_BIT (counted_for_groups, i)
2099: && ! TEST_HARD_REG_BIT (counted_for_nongroups, i))
2100: return 1;
2101: }
2102:
2103: return 0;
2104: }
2105:
2106: /* Count any groups that can be formed from the registers recently spilled.
2107: This is done class by class, in order of ascending class number. */
2108:
2109: static void
2110: count_possible_groups (group_size, group_mode, max_groups)
2111: int *group_size;
2112: enum machine_mode *group_mode;
2113: int *max_groups;
2114: {
2115: int i;
2116: /* Now find all consecutive groups of spilled registers
2117: and mark each group off against the need for such groups.
2118: But don't count them against ordinary need, yet. */
2119:
2120: for (i = 0; i < N_REG_CLASSES; i++)
2121: if (group_size[i] > 1)
2122: {
2123: HARD_REG_SET new;
2124: int j;
2125:
2126: CLEAR_HARD_REG_SET (new);
2127:
2128: /* Make a mask of all the regs that are spill regs in class I. */
2129: for (j = 0; j < n_spills; j++)
2130: if (TEST_HARD_REG_BIT (reg_class_contents[i], spill_regs[j])
2131: && ! TEST_HARD_REG_BIT (counted_for_groups, spill_regs[j])
2132: && ! TEST_HARD_REG_BIT (counted_for_nongroups,
2133: spill_regs[j]))
2134: SET_HARD_REG_BIT (new, spill_regs[j]);
2135:
2136: /* Find each consecutive group of them. */
2137: for (j = 0; j < FIRST_PSEUDO_REGISTER && max_groups[i] > 0; j++)
2138: if (TEST_HARD_REG_BIT (new, j)
2139: && j + group_size[i] <= FIRST_PSEUDO_REGISTER
2140: /* Next line in case group-mode for this class
2141: demands an even-odd pair. */
2142: && HARD_REGNO_MODE_OK (j, group_mode[i]))
2143: {
2144: int k;
2145: for (k = 1; k < group_size[i]; k++)
2146: if (! TEST_HARD_REG_BIT (new, j + k))
2147: break;
2148: if (k == group_size[i])
2149: {
2150: /* We found a group. Mark it off against this class's
2151: need for groups, and against each superclass too. */
2152: register enum reg_class *p;
2153: max_groups[i]--;
2154: p = reg_class_superclasses[i];
2155: while (*p != LIM_REG_CLASSES)
2156: max_groups[(int) *p++]--;
2157: /* Don't count these registers again. */
2158: for (k = 0; k < group_size[i]; k++)
2159: SET_HARD_REG_BIT (counted_for_groups, j + k);
2160: }
2161: /* Skip to the last reg in this group. When j is incremented
2162: above, it will then point to the first reg of the next
2163: possible group. */
2164: j += k - 1;
2165: }
2166: }
2167:
2168: }
2169:
2170: /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
2171: another mode that needs to be reloaded for the same register class CLASS.
2172: If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
2173: ALLOCATE_MODE will never be smaller than OTHER_MODE.
2174:
2175: This code used to also fail if any reg in CLASS allows OTHER_MODE but not
2176: ALLOCATE_MODE. This test is unnecessary, because we will never try to put
2177: something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
2178: causes unnecessary failures on machines requiring alignment of register
2179: groups when the two modes are different sizes, because the larger mode has
2180: more strict alignment rules than the smaller mode. */
2181:
2182: static int
2183: modes_equiv_for_class_p (allocate_mode, other_mode, class)
2184: enum machine_mode allocate_mode, other_mode;
2185: enum reg_class class;
2186: {
2187: register int regno;
2188: for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2189: {
2190: if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)
2191: && HARD_REGNO_MODE_OK (regno, allocate_mode)
2192: && ! HARD_REGNO_MODE_OK (regno, other_mode))
2193: return 0;
2194: }
2195: return 1;
2196: }
2197:
2198: /* Handle the failure to find a register to spill.
2199: INSN should be one of the insns which needed this particular spill reg. */
2200:
2201: static void
2202: spill_failure (insn)
2203: rtx insn;
2204: {
2205: if (asm_noperands (PATTERN (insn)) >= 0)
2206: error_for_asm (insn, "`asm' needs too many reloads");
2207: else
2208: abort ();
2209: }
2210:
2211: /* Add a new register to the tables of available spill-registers
2212: (as well as spilling all pseudos allocated to the register).
2213: I is the index of this register in potential_reload_regs.
2214: CLASS is the regclass whose need is being satisfied.
2215: MAX_NEEDS and MAX_NONGROUPS are the vectors of needs,
2216: so that this register can count off against them.
2217: MAX_NONGROUPS is 0 if this register is part of a group.
2218: GLOBAL and DUMPFILE are the same as the args that `reload' got. */
2219:
2220: static int
2221: new_spill_reg (i, class, max_needs, max_nongroups, global, dumpfile)
2222: int i;
2223: int class;
2224: int *max_needs;
2225: int *max_nongroups;
2226: int global;
2227: FILE *dumpfile;
2228: {
2229: register enum reg_class *p;
2230: int val;
2231: int regno = potential_reload_regs[i];
2232:
2233: if (i >= FIRST_PSEUDO_REGISTER)
2234: abort (); /* Caller failed to find any register. */
2235:
2236: #ifdef HI_SUM_TARGET_REGNO
2237: if (regno != HI_SUM_TARGET_REGNO)
2238: #endif
2239: if (fixed_regs[regno] || TEST_HARD_REG_BIT (forbidden_regs, regno))
2240: fatal ("fixed or forbidden register was spilled.\n\
2241: This may be due to a compiler bug or to impossible asm statements.");
2242:
2243: /* Make reg REGNO an additional reload reg. */
2244:
2245: potential_reload_regs[i] = -1;
2246: spill_regs[n_spills] = regno;
2247: spill_reg_order[regno] = n_spills;
2248: if (dumpfile)
2249: fprintf (dumpfile, "Spilling reg %d.\n", spill_regs[n_spills]);
2250:
2251: /* Clear off the needs we just satisfied. */
2252:
2253: max_needs[class]--;
2254: p = reg_class_superclasses[class];
2255: while (*p != LIM_REG_CLASSES)
2256: max_needs[(int) *p++]--;
2257:
2258: if (max_nongroups && max_nongroups[class] > 0)
2259: {
2260: SET_HARD_REG_BIT (counted_for_nongroups, regno);
2261: max_nongroups[class]--;
2262: p = reg_class_superclasses[class];
2263: while (*p != LIM_REG_CLASSES)
2264: max_nongroups[(int) *p++]--;
2265: }
2266:
2267: /* Spill every pseudo reg that was allocated to this reg
2268: or to something that overlaps this reg. */
2269:
2270: val = spill_hard_reg (spill_regs[n_spills], global, dumpfile, 0);
2271:
2272: /* If there are some registers still to eliminate and this register
2273: wasn't ever used before, additional stack space may have to be
2274: allocated to store this register. Thus, we may have changed the offset
2275: between the stack and frame pointers, so mark that something has changed.
2276: (If new pseudos were spilled, thus requiring more space, VAL would have
2277: been set non-zero by the call to spill_hard_reg above since additional
2278: reloads may be needed in that case.
2279:
2280: One might think that we need only set VAL to 1 if this is a call-used
2281: register. However, the set of registers that must be saved by the
2282: prologue is not identical to the call-used set. For example, the
2283: register used by the call insn for the return PC is a call-used register,
2284: but must be saved by the prologue. */
2285: if (num_eliminable && ! regs_ever_live[spill_regs[n_spills]])
2286: val = 1;
2287:
2288: regs_ever_live[spill_regs[n_spills]] = 1;
2289: n_spills++;
2290:
2291: return val;
2292: }
2293:
2294: /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2295: data that is dead in INSN. */
2296:
2297: static void
2298: delete_dead_insn (insn)
2299: rtx insn;
2300: {
2301: rtx prev = prev_real_insn (insn);
2302: rtx prev_dest;
2303:
2304: /* If the previous insn sets a register that dies in our insn, delete it
2305: too. */
2306: if (prev && GET_CODE (PATTERN (prev)) == SET
2307: && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
2308: && reg_mentioned_p (prev_dest, PATTERN (insn))
2309: && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)))
2310: delete_dead_insn (prev);
2311:
2312: PUT_CODE (insn, NOTE);
2313: NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2314: NOTE_SOURCE_FILE (insn) = 0;
2315: }
2316:
2317: /* Modify the home of pseudo-reg I.
2318: The new home is present in reg_renumber[I].
2319:
2320: FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2321: or it may be -1, meaning there is none or it is not relevant.
2322: This is used so that all pseudos spilled from a given hard reg
2323: can share one stack slot. */
2324:
2325: static void
2326: alter_reg (i, from_reg)
2327: register int i;
2328: int from_reg;
2329: {
2330: /* When outputting an inline function, this can happen
2331: for a reg that isn't actually used. */
2332: if (regno_reg_rtx[i] == 0)
2333: return;
2334:
2335: /* If the reg got changed to a MEM at rtl-generation time,
2336: ignore it. */
2337: if (GET_CODE (regno_reg_rtx[i]) != REG)
2338: return;
2339:
2340: /* Modify the reg-rtx to contain the new hard reg
2341: number or else to contain its pseudo reg number. */
2342: REGNO (regno_reg_rtx[i])
2343: = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
2344:
2345: /* If we have a pseudo that is needed but has no hard reg or equivalent,
2346: allocate a stack slot for it. */
2347:
2348: if (reg_renumber[i] < 0
2349: && reg_n_refs[i] > 0
2350: && reg_equiv_constant[i] == 0
2351: && reg_equiv_memory_loc[i] == 0)
2352: {
2353: register rtx x;
2354: int inherent_size = PSEUDO_REGNO_BYTES (i);
2355: int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2356: int adjust = 0;
2357:
2358: /* Each pseudo reg has an inherent size which comes from its own mode,
2359: and a total size which provides room for paradoxical subregs
2360: which refer to the pseudo reg in wider modes.
2361:
2362: We can use a slot already allocated if it provides both
2363: enough inherent space and enough total space.
2364: Otherwise, we allocate a new slot, making sure that it has no less
2365: inherent space, and no less total space, then the previous slot. */
2366: if (from_reg == -1)
2367: {
2368: /* No known place to spill from => no slot to reuse. */
2369: x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size, -1);
2370: #if BYTES_BIG_ENDIAN
2371: /* Cancel the big-endian correction done in assign_stack_local.
2372: Get the address of the beginning of the slot.
2373: This is so we can do a big-endian correction unconditionally
2374: below. */
2375: adjust = inherent_size - total_size;
2376: #endif
2377: }
2378: /* Reuse a stack slot if possible. */
2379: else if (spill_stack_slot[from_reg] != 0
2380: && spill_stack_slot_width[from_reg] >= total_size
2381: && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2382: >= inherent_size))
2383: x = spill_stack_slot[from_reg];
2384: /* Allocate a bigger slot. */
2385: else
2386: {
2387: /* Compute maximum size needed, both for inherent size
2388: and for total size. */
2389: enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2390: if (spill_stack_slot[from_reg])
2391: {
2392: if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2393: > inherent_size)
2394: mode = GET_MODE (spill_stack_slot[from_reg]);
2395: if (spill_stack_slot_width[from_reg] > total_size)
2396: total_size = spill_stack_slot_width[from_reg];
2397: }
2398: /* Make a slot with that size. */
2399: x = assign_stack_local (mode, total_size, -1);
2400: #if BYTES_BIG_ENDIAN
2401: /* Cancel the big-endian correction done in assign_stack_local.
2402: Get the address of the beginning of the slot.
2403: This is so we can do a big-endian correction unconditionally
2404: below. */
2405: adjust = GET_MODE_SIZE (mode) - total_size;
2406: #endif
2407: spill_stack_slot[from_reg] = x;
2408: spill_stack_slot_width[from_reg] = total_size;
2409: }
2410:
2411: #if BYTES_BIG_ENDIAN
2412: /* On a big endian machine, the "address" of the slot
2413: is the address of the low part that fits its inherent mode. */
2414: if (inherent_size < total_size)
2415: adjust += (total_size - inherent_size);
2416: #endif /* BYTES_BIG_ENDIAN */
2417:
2418: /* If we have any adjustment to make, or if the stack slot is the
2419: wrong mode, make a new stack slot. */
2420: if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2421: {
2422: x = gen_rtx (MEM, GET_MODE (regno_reg_rtx[i]),
2423: plus_constant (XEXP (x, 0), adjust));
2424: RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2425: }
2426:
2427: /* Save the stack slot for later. */
2428: reg_equiv_memory_loc[i] = x;
2429: }
2430: }
2431:
2432: /* Mark the slots in regs_ever_live for the hard regs
2433: used by pseudo-reg number REGNO. */
2434:
2435: void
2436: mark_home_live (regno)
2437: int regno;
2438: {
2439: register int i, lim;
2440: i = reg_renumber[regno];
2441: if (i < 0)
2442: return;
2443: lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2444: while (i < lim)
2445: regs_ever_live[i++] = 1;
2446: }
2447:
2448: /* Mark the registers used in SCRATCH as being live. */
2449:
2450: static void
2451: mark_scratch_live (scratch)
2452: rtx scratch;
2453: {
2454: register int i;
2455: int regno = REGNO (scratch);
2456: int lim = regno + HARD_REGNO_NREGS (regno, GET_MODE (scratch));
2457:
2458: for (i = regno; i < lim; i++)
2459: regs_ever_live[i] = 1;
2460: }
2461:
2462: /* This function handles the tracking of elimination offsets around branches.
2463:
2464: X is a piece of RTL being scanned.
2465:
2466: INSN is the insn that it came from, if any.
2467:
2468: INITIAL_P is non-zero if we are to set the offset to be the initial
2469: offset and zero if we are setting the offset of the label to be the
2470: current offset. */
2471:
2472: static void
2473: set_label_offsets (x, insn, initial_p)
2474: rtx x;
2475: rtx insn;
2476: int initial_p;
2477: {
2478: enum rtx_code code = GET_CODE (x);
2479: rtx tem;
2480: int i;
2481: struct elim_table *p;
2482:
2483: switch (code)
2484: {
2485: case LABEL_REF:
2486: if (LABEL_REF_NONLOCAL_P (x))
2487: return;
2488:
2489: x = XEXP (x, 0);
2490:
2491: /* ... fall through ... */
2492:
2493: case CODE_LABEL:
2494: /* If we know nothing about this label, set the desired offsets. Note
2495: that this sets the offset at a label to be the offset before a label
2496: if we don't know anything about the label. This is not correct for
2497: the label after a BARRIER, but is the best guess we can make. If
2498: we guessed wrong, we will suppress an elimination that might have
2499: been possible had we been able to guess correctly. */
2500:
2501: if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2502: {
2503: for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2504: offsets_at[CODE_LABEL_NUMBER (x)][i]
2505: = (initial_p ? reg_eliminate[i].initial_offset
2506: : reg_eliminate[i].offset);
2507: offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2508: }
2509:
2510: /* Otherwise, if this is the definition of a label and it is
2511: preceded by a BARRIER, set our offsets to the known offset of
2512: that label. */
2513:
2514: else if (x == insn
2515: && (tem = prev_nonnote_insn (insn)) != 0
2516: && GET_CODE (tem) == BARRIER)
2517: {
2518: num_not_at_initial_offset = 0;
2519: for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2520: {
2521: reg_eliminate[i].offset = reg_eliminate[i].previous_offset
2522: = offsets_at[CODE_LABEL_NUMBER (x)][i];
2523: if (reg_eliminate[i].can_eliminate
2524: && (reg_eliminate[i].offset
2525: != reg_eliminate[i].initial_offset))
2526: num_not_at_initial_offset++;
2527: }
2528: }
2529:
2530: else
2531: /* If neither of the above cases is true, compare each offset
2532: with those previously recorded and suppress any eliminations
2533: where the offsets disagree. */
2534:
2535: for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2536: if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2537: != (initial_p ? reg_eliminate[i].initial_offset
2538: : reg_eliminate[i].offset))
2539: reg_eliminate[i].can_eliminate = 0;
2540:
2541: return;
2542:
2543: case JUMP_INSN:
2544: set_label_offsets (PATTERN (insn), insn, initial_p);
2545:
2546: /* ... fall through ... */
2547:
2548: case INSN:
2549: case CALL_INSN:
2550: /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2551: and hence must have all eliminations at their initial offsets. */
2552: for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2553: if (REG_NOTE_KIND (tem) == REG_LABEL)
2554: set_label_offsets (XEXP (tem, 0), insn, 1);
2555: return;
2556:
2557: case ADDR_VEC:
2558: case ADDR_DIFF_VEC:
2559: /* Each of the labels in the address vector must be at their initial
2560: offsets. We want the first first for ADDR_VEC and the second
2561: field for ADDR_DIFF_VEC. */
2562:
2563: for (i = 0; i < XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2564: set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2565: insn, initial_p);
2566: return;
2567:
2568: case SET:
2569: /* We only care about setting PC. If the source is not RETURN,
2570: IF_THEN_ELSE, or a label, disable any eliminations not at
2571: their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2572: isn't one of those possibilities. For branches to a label,
2573: call ourselves recursively.
2574:
2575: Note that this can disable elimination unnecessarily when we have
2576: a non-local goto since it will look like a non-constant jump to
2577: someplace in the current function. This isn't a significant
2578: problem since such jumps will normally be when all elimination
2579: pairs are back to their initial offsets. */
2580:
2581: if (SET_DEST (x) != pc_rtx)
2582: return;
2583:
2584: switch (GET_CODE (SET_SRC (x)))
2585: {
2586: case PC:
2587: case RETURN:
2588: return;
2589:
2590: case LABEL_REF:
2591: set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2592: return;
2593:
2594: case IF_THEN_ELSE:
2595: tem = XEXP (SET_SRC (x), 1);
2596: if (GET_CODE (tem) == LABEL_REF)
2597: set_label_offsets (XEXP (tem, 0), insn, initial_p);
2598: else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2599: break;
2600:
2601: tem = XEXP (SET_SRC (x), 2);
2602: if (GET_CODE (tem) == LABEL_REF)
2603: set_label_offsets (XEXP (tem, 0), insn, initial_p);
2604: else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2605: break;
2606: return;
2607: }
2608:
2609: /* If we reach here, all eliminations must be at their initial
2610: offset because we are doing a jump to a variable address. */
2611: for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2612: if (p->offset != p->initial_offset)
2613: p->can_eliminate = 0;
2614: }
2615: }
2616:
2617: /* Used for communication between the next two function to properly share
2618: the vector for an ASM_OPERANDS. */
2619:
2620: static struct rtvec_def *old_asm_operands_vec, *new_asm_operands_vec;
2621:
2622: /* Scan X and replace any eliminable registers (such as fp) with a
2623: replacement (such as sp), plus an offset.
2624:
2625: MEM_MODE is the mode of an enclosing MEM. We need this to know how
2626: much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2627: MEM, we are allowed to replace a sum of a register and the constant zero
2628: with the register, which we cannot do outside a MEM. In addition, we need
2629: to record the fact that a register is referenced outside a MEM.
2630:
2631: If INSN is an insn, it is the insn containing X. If we replace a REG
2632: in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2633: CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2634: that the REG is being modified.
2635:
2636: Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2637: That's used when we eliminate in expressions stored in notes.
2638: This means, do not set ref_outside_mem even if the reference
2639: is outside of MEMs.
2640:
2641: If we see a modification to a register we know about, take the
2642: appropriate action (see case SET, below).
2643:
2644: REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2645: replacements done assuming all offsets are at their initial values. If
2646: they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2647: encounter, return the actual location so that find_reloads will do
2648: the proper thing. */
2649:
2650: rtx
2651: eliminate_regs (x, mem_mode, insn)
2652: rtx x;
2653: enum machine_mode mem_mode;
2654: rtx insn;
2655: {
2656: enum rtx_code code = GET_CODE (x);
2657: struct elim_table *ep;
2658: int regno;
2659: rtx new;
2660: int i, j;
2661: char *fmt;
2662: int copied = 0;
2663:
2664: switch (code)
2665: {
2666: case CONST_INT:
2667: case CONST_DOUBLE:
2668: case CONST:
2669: case SYMBOL_REF:
2670: case CODE_LABEL:
2671: case PC:
2672: case CC0:
2673: case ASM_INPUT:
2674: case ADDR_VEC:
2675: case ADDR_DIFF_VEC:
2676: case RETURN:
2677: return x;
2678:
2679: case REG:
2680: regno = REGNO (x);
2681:
2682: /* First handle the case where we encounter a bare register that
2683: is eliminable. Replace it with a PLUS. */
2684: if (regno < FIRST_PSEUDO_REGISTER)
2685: {
2686: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2687: ep++)
2688: if (ep->from_rtx == x && ep->can_eliminate)
2689: {
2690: if (! mem_mode
2691: /* Refs inside notes don't count for this purpose. */
2692: && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2693: || GET_CODE (insn) == INSN_LIST)))
2694: ep->ref_outside_mem = 1;
2695: return plus_constant (ep->to_rtx, ep->previous_offset);
2696: }
2697:
2698: }
2699: else if (reg_equiv_memory_loc && reg_equiv_memory_loc[regno]
2700: && (reg_equiv_address[regno] || num_not_at_initial_offset))
2701: {
2702: /* In this case, find_reloads would attempt to either use an
2703: incorrect address (if something is not at its initial offset)
2704: or substitute an replaced address into an insn (which loses
2705: if the offset is changed by some later action). So we simply
2706: return the replaced stack slot (assuming it is changed by
2707: elimination) and ignore the fact that this is actually a
2708: reference to the pseudo. Ensure we make a copy of the
2709: address in case it is shared. */
2710: new = eliminate_regs (reg_equiv_memory_loc[regno],
2711: mem_mode, insn);
2712: if (new != reg_equiv_memory_loc[regno])
2713: {
2714: cannot_omit_stores[regno] = 1;
2715: return copy_rtx (new);
2716: }
2717: }
2718: return x;
2719:
2720: case PLUS:
2721: /* If this is the sum of an eliminable register and a constant, rework
2722: the sum. */
2723: if (GET_CODE (XEXP (x, 0)) == REG
2724: && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2725: && CONSTANT_P (XEXP (x, 1)))
2726: {
2727: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2728: ep++)
2729: if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2730: {
2731: if (! mem_mode
2732: /* Refs inside notes don't count for this purpose. */
2733: && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2734: || GET_CODE (insn) == INSN_LIST)))
2735: ep->ref_outside_mem = 1;
2736:
2737: /* The only time we want to replace a PLUS with a REG (this
2738: occurs when the constant operand of the PLUS is the negative
2739: of the offset) is when we are inside a MEM. We won't want
2740: to do so at other times because that would change the
2741: structure of the insn in a way that reload can't handle.
2742: We special-case the commonest situation in
2743: eliminate_regs_in_insn, so just replace a PLUS with a
2744: PLUS here, unless inside a MEM. */
2745: if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2746: && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2747: return ep->to_rtx;
2748: else
2749: return gen_rtx (PLUS, Pmode, ep->to_rtx,
2750: plus_constant (XEXP (x, 1),
2751: ep->previous_offset));
2752: }
2753:
2754: /* If the register is not eliminable, we are done since the other
2755: operand is a constant. */
2756: return x;
2757: }
2758:
2759: /* If this is part of an address, we want to bring any constant to the
2760: outermost PLUS. We will do this by doing register replacement in
2761: our operands and seeing if a constant shows up in one of them.
2762:
2763: We assume here this is part of an address (or a "load address" insn)
2764: since an eliminable register is not likely to appear in any other
2765: context.
2766:
2767: If we have (plus (eliminable) (reg)), we want to produce
2768: (plus (plus (replacement) (reg) (const))). If this was part of a
2769: normal add insn, (plus (replacement) (reg)) will be pushed as a
2770: reload. This is the desired action. */
2771:
2772: {
2773: rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2774: rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2775:
2776: if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2777: {
2778: /* If one side is a PLUS and the other side is a pseudo that
2779: didn't get a hard register but has a reg_equiv_constant,
2780: we must replace the constant here since it may no longer
2781: be in the position of any operand. */
2782: if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2783: && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2784: && reg_renumber[REGNO (new1)] < 0
2785: && reg_equiv_constant != 0
2786: && reg_equiv_constant[REGNO (new1)] != 0)
2787: new1 = reg_equiv_constant[REGNO (new1)];
2788: else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2789: && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2790: && reg_renumber[REGNO (new0)] < 0
2791: && reg_equiv_constant[REGNO (new0)] != 0)
2792: new0 = reg_equiv_constant[REGNO (new0)];
2793:
2794: new = form_sum (new0, new1);
2795:
2796: /* As above, if we are not inside a MEM we do not want to
2797: turn a PLUS into something else. We might try to do so here
2798: for an addition of 0 if we aren't optimizing. */
2799: if (! mem_mode && GET_CODE (new) != PLUS)
2800: return gen_rtx (PLUS, GET_MODE (x), new, const0_rtx);
2801: else
2802: return new;
2803: }
2804: }
2805: return x;
2806:
2807: case EXPR_LIST:
2808: /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2809: if (XEXP (x, 0))
2810: {
2811: new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2812: if (new != XEXP (x, 0))
2813: x = gen_rtx (EXPR_LIST, REG_NOTE_KIND (x), new, XEXP (x, 1));
2814: }
2815:
2816: /* ... fall through ... */
2817:
2818: case INSN_LIST:
2819: /* Now do eliminations in the rest of the chain. If this was
2820: an EXPR_LIST, this might result in allocating more memory than is
2821: strictly needed, but it simplifies the code. */
2822: if (XEXP (x, 1))
2823: {
2824: new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2825: if (new != XEXP (x, 1))
2826: return gen_rtx (INSN_LIST, GET_MODE (x), XEXP (x, 0), new);
2827: }
2828: return x;
2829:
2830: case CALL:
2831: case COMPARE:
2832: case MINUS:
2833: case MULT:
2834: case DIV: case UDIV:
2835: case MOD: case UMOD:
2836: case AND: case IOR: case XOR:
2837: case LSHIFT: case ASHIFT: case ROTATE:
2838: case ASHIFTRT: case LSHIFTRT: case ROTATERT:
2839: case NE: case EQ:
2840: case GE: case GT: case GEU: case GTU:
2841: case LE: case LT: case LEU: case LTU:
2842: {
2843: rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2844: rtx new1
2845: = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2846:
2847: if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2848: return gen_rtx (code, GET_MODE (x), new0, new1);
2849: }
2850: return x;
2851:
2852: case PRE_INC:
2853: case POST_INC:
2854: case PRE_DEC:
2855: case POST_DEC:
2856: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2857: if (ep->to_rtx == XEXP (x, 0))
2858: {
2859: int size = GET_MODE_SIZE (mem_mode);
2860:
2861: /* If more bytes than MEM_MODE are pushed, account for them. */
2862: #ifdef PUSH_ROUNDING
2863: if (ep->to_rtx == stack_pointer_rtx)
2864: size = PUSH_ROUNDING (size);
2865: #endif
2866: if (code == PRE_DEC || code == POST_DEC)
2867: ep->offset += size;
2868: else
2869: ep->offset -= size;
2870: }
2871:
2872: /* Fall through to generic unary operation case. */
2873: case USE:
2874: case STRICT_LOW_PART:
2875: case NEG: case NOT:
2876: case SIGN_EXTEND: case ZERO_EXTEND:
2877: case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2878: case FLOAT: case FIX:
2879: case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2880: case ABS:
2881: case SQRT:
2882: case FFS:
2883: new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2884: if (new != XEXP (x, 0))
2885: return gen_rtx (code, GET_MODE (x), new);
2886: return x;
2887:
2888: case SUBREG:
2889: /* Similar to above processing, but preserve SUBREG_WORD.
2890: Convert (subreg (mem)) to (mem) if not paradoxical.
2891: Also, if we have a non-paradoxical (subreg (pseudo)) and the
2892: pseudo didn't get a hard reg, we must replace this with the
2893: eliminated version of the memory location because push_reloads
2894: may do the replacement in certain circumstances. */
2895: if (GET_CODE (SUBREG_REG (x)) == REG
2896: && (GET_MODE_SIZE (GET_MODE (x))
2897: <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2898: && reg_equiv_memory_loc != 0
2899: && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2900: {
2901: new = eliminate_regs (reg_equiv_memory_loc[REGNO (SUBREG_REG (x))],
2902: mem_mode, insn);
2903:
2904: /* If we didn't change anything, we must retain the pseudo. */
2905: if (new == reg_equiv_memory_loc[REGNO (SUBREG_REG (x))])
2906: new = XEXP (x, 0);
2907: else
2908: /* Otherwise, ensure NEW isn't shared in case we have to reload
2909: it. */
2910: new = copy_rtx (new);
2911: }
2912: else
2913: new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2914:
2915: if (new != XEXP (x, 0))
2916: {
2917: if (GET_CODE (new) == MEM
2918: && (GET_MODE_SIZE (GET_MODE (x))
2919: <= GET_MODE_SIZE (GET_MODE (new)))
2920: #ifdef LOAD_EXTEND_OP
2921: /* On these machines we will be reloading what is
2922: inside the SUBREG if it originally was a pseudo and
2923: the inner and outer modes are both a word or
2924: smaller. So leave the SUBREG then. */
2925: && ! (GET_CODE (SUBREG_REG (x)) == REG
2926: && GET_MODE_SIZE (GET_MODE (x)) <= UNITS_PER_WORD
2927: && GET_MODE_SIZE (GET_MODE (new)) <= UNITS_PER_WORD)
2928: #endif
2929: )
2930: {
2931: int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
2932: enum machine_mode mode = GET_MODE (x);
2933:
2934: #if BYTES_BIG_ENDIAN
2935: offset += (MIN (UNITS_PER_WORD,
2936: GET_MODE_SIZE (GET_MODE (new)))
2937: - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
2938: #endif
2939:
2940: PUT_MODE (new, mode);
2941: XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2942: return new;
2943: }
2944: else
2945: return gen_rtx (SUBREG, GET_MODE (x), new, SUBREG_WORD (x));
2946: }
2947:
2948: return x;
2949:
2950: case CLOBBER:
2951: /* If clobbering a register that is the replacement register for an
2952: elimination we still think can be performed, note that it cannot
2953: be performed. Otherwise, we need not be concerned about it. */
2954: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2955: if (ep->to_rtx == XEXP (x, 0))
2956: ep->can_eliminate = 0;
2957:
2958: new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2959: if (new != XEXP (x, 0))
2960: return gen_rtx (code, GET_MODE (x), new);
2961: return x;
2962:
2963: case ASM_OPERANDS:
2964: {
2965: rtx *temp_vec;
2966: /* Properly handle sharing input and constraint vectors. */
2967: if (ASM_OPERANDS_INPUT_VEC (x) != old_asm_operands_vec)
2968: {
2969: /* When we come to a new vector not seen before,
2970: scan all its elements; keep the old vector if none
2971: of them changes; otherwise, make a copy. */
2972: old_asm_operands_vec = ASM_OPERANDS_INPUT_VEC (x);
2973: temp_vec = (rtx *) alloca (XVECLEN (x, 3) * sizeof (rtx));
2974: for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
2975: temp_vec[i] = eliminate_regs (ASM_OPERANDS_INPUT (x, i),
2976: mem_mode, insn);
2977:
2978: for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
2979: if (temp_vec[i] != ASM_OPERANDS_INPUT (x, i))
2980: break;
2981:
2982: if (i == ASM_OPERANDS_INPUT_LENGTH (x))
2983: new_asm_operands_vec = old_asm_operands_vec;
2984: else
2985: new_asm_operands_vec
2986: = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x), temp_vec);
2987: }
2988:
2989: /* If we had to copy the vector, copy the entire ASM_OPERANDS. */
2990: if (new_asm_operands_vec == old_asm_operands_vec)
2991: return x;
2992:
2993: new = gen_rtx (ASM_OPERANDS, VOIDmode, ASM_OPERANDS_TEMPLATE (x),
2994: ASM_OPERANDS_OUTPUT_CONSTRAINT (x),
2995: ASM_OPERANDS_OUTPUT_IDX (x), new_asm_operands_vec,
2996: ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x),
2997: ASM_OPERANDS_SOURCE_FILE (x),
2998: ASM_OPERANDS_SOURCE_LINE (x));
2999: new->volatil = x->volatil;
3000: return new;
3001: }
3002:
3003: case SET:
3004: /* Check for setting a register that we know about. */
3005: if (GET_CODE (SET_DEST (x)) == REG)
3006: {
3007: /* See if this is setting the replacement register for an
3008: elimination.
3009:
3010: If DEST is the hard frame pointer, we do nothing because we
3011: assume that all assignments to the frame pointer are for
3012: non-local gotos and are being done at a time when they are valid
3013: and do not disturb anything else. Some machines want to
3014: eliminate a fake argument pointer (or even a fake frame pointer)
3015: with either the real frame or the stack pointer. Assignments to
3016: the hard frame pointer must not prevent this elimination. */
3017:
3018: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3019: ep++)
3020: if (ep->to_rtx == SET_DEST (x)
3021: && SET_DEST (x) != hard_frame_pointer_rtx)
3022: {
3023: /* If it is being incremented, adjust the offset. Otherwise,
3024: this elimination can't be done. */
3025: rtx src = SET_SRC (x);
3026:
3027: if (GET_CODE (src) == PLUS
3028: && XEXP (src, 0) == SET_DEST (x)
3029: && GET_CODE (XEXP (src, 1)) == CONST_INT)
3030: ep->offset -= INTVAL (XEXP (src, 1));
3031: else
3032: ep->can_eliminate = 0;
3033: }
3034:
3035: /* Now check to see we are assigning to a register that can be
3036: eliminated. If so, it must be as part of a PARALLEL, since we
3037: will not have been called if this is a single SET. So indicate
3038: that we can no longer eliminate this reg. */
3039: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3040: ep++)
3041: if (ep->from_rtx == SET_DEST (x) && ep->can_eliminate)
3042: ep->can_eliminate = 0;
3043: }
3044:
3045: /* Now avoid the loop below in this common case. */
3046: {
3047: rtx new0 = eliminate_regs (SET_DEST (x), 0, insn);
3048: rtx new1 = eliminate_regs (SET_SRC (x), 0, insn);
3049:
3050: /* If SET_DEST changed from a REG to a MEM and INSN is an insn,
3051: write a CLOBBER insn. */
3052: if (GET_CODE (SET_DEST (x)) == REG && GET_CODE (new0) == MEM
3053: && insn != 0 && GET_CODE (insn) != EXPR_LIST
3054: && GET_CODE (insn) != INSN_LIST)
3055: emit_insn_after (gen_rtx (CLOBBER, VOIDmode, SET_DEST (x)), insn);
3056:
3057: if (new0 != SET_DEST (x) || new1 != SET_SRC (x))
3058: return gen_rtx (SET, VOIDmode, new0, new1);
3059: }
3060:
3061: return x;
3062:
3063: case MEM:
3064: /* Our only special processing is to pass the mode of the MEM to our
3065: recursive call and copy the flags. While we are here, handle this
3066: case more efficiently. */
3067: new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
3068: if (new != XEXP (x, 0))
3069: {
3070: new = gen_rtx (MEM, GET_MODE (x), new);
3071: new->volatil = x->volatil;
3072: new->unchanging = x->unchanging;
3073: new->in_struct = x->in_struct;
3074: return new;
3075: }
3076: else
3077: return x;
3078: }
3079:
3080: /* Process each of our operands recursively. If any have changed, make a
3081: copy of the rtx. */
3082: fmt = GET_RTX_FORMAT (code);
3083: for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3084: {
3085: if (*fmt == 'e')
3086: {
3087: new = eliminate_regs (XEXP (x, i), mem_mode, insn);
3088: if (new != XEXP (x, i) && ! copied)
3089: {
3090: rtx new_x = rtx_alloc (code);
3091: bcopy (x, new_x, (sizeof (*new_x) - sizeof (new_x->fld)
3092: + (sizeof (new_x->fld[0])
3093: * GET_RTX_LENGTH (code))));
3094: x = new_x;
3095: copied = 1;
3096: }
3097: XEXP (x, i) = new;
3098: }
3099: else if (*fmt == 'E')
3100: {
3101: int copied_vec = 0;
3102: for (j = 0; j < XVECLEN (x, i); j++)
3103: {
3104: new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
3105: if (new != XVECEXP (x, i, j) && ! copied_vec)
3106: {
3107: rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
3108: &XVECEXP (x, i, 0));
3109: if (! copied)
3110: {
3111: rtx new_x = rtx_alloc (code);
3112: bcopy (x, new_x, (sizeof (*new_x) - sizeof (new_x->fld)
3113: + (sizeof (new_x->fld[0])
3114: * GET_RTX_LENGTH (code))));
3115: x = new_x;
3116: copied = 1;
3117: }
3118: XVEC (x, i) = new_v;
3119: copied_vec = 1;
3120: }
3121: XVECEXP (x, i, j) = new;
3122: }
3123: }
3124: }
3125:
3126: return x;
3127: }
3128:
3129: /* Scan INSN and eliminate all eliminable registers in it.
3130:
3131: If REPLACE is nonzero, do the replacement destructively. Also
3132: delete the insn as dead it if it is setting an eliminable register.
3133:
3134: If REPLACE is zero, do all our allocations in reload_obstack.
3135:
3136: If no eliminations were done and this insn doesn't require any elimination
3137: processing (these are not identical conditions: it might be updating sp,
3138: but not referencing fp; this needs to be seen during reload_as_needed so
3139: that the offset between fp and sp can be taken into consideration), zero
3140: is returned. Otherwise, 1 is returned. */
3141:
3142: static int
3143: eliminate_regs_in_insn (insn, replace)
3144: rtx insn;
3145: int replace;
3146: {
3147: rtx old_body = PATTERN (insn);
3148: rtx new_body;
3149: int val = 0;
3150: struct elim_table *ep;
3151:
3152: if (! replace)
3153: push_obstacks (&reload_obstack, &reload_obstack);
3154:
3155: if (GET_CODE (old_body) == SET && GET_CODE (SET_DEST (old_body)) == REG
3156: && REGNO (SET_DEST (old_body)) < FIRST_PSEUDO_REGISTER)
3157: {
3158: /* Check for setting an eliminable register. */
3159: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3160: if (ep->from_rtx == SET_DEST (old_body) && ep->can_eliminate)
3161: {
3162: /* In this case this insn isn't serving a useful purpose. We
3163: will delete it in reload_as_needed once we know that this
3164: elimination is, in fact, being done.
3165:
3166: If REPLACE isn't set, we can't delete this insn, but neededn't
3167: process it since it won't be used unless something changes. */
3168: if (replace)
3169: delete_dead_insn (insn);
3170: val = 1;
3171: goto done;
3172: }
3173:
3174: /* Check for (set (reg) (plus (reg from) (offset))) where the offset
3175: in the insn is the negative of the offset in FROM. Substitute
3176: (set (reg) (reg to)) for the insn and change its code.
3177:
3178: We have to do this here, rather than in eliminate_regs, do that we can
3179: change the insn code. */
3180:
3181: if (GET_CODE (SET_SRC (old_body)) == PLUS
3182: && GET_CODE (XEXP (SET_SRC (old_body), 0)) == REG
3183: && GET_CODE (XEXP (SET_SRC (old_body), 1)) == CONST_INT)
3184: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3185: ep++)
3186: if (ep->from_rtx == XEXP (SET_SRC (old_body), 0)
3187: && ep->can_eliminate)
3188: {
3189: /* We must stop at the first elimination that will be used.
3190: If this one would replace the PLUS with a REG, do it
3191: now. Otherwise, quit the loop and let eliminate_regs
3192: do its normal replacement. */
3193: if (ep->offset == - INTVAL (XEXP (SET_SRC (old_body), 1)))
3194: {
3195: PATTERN (insn) = gen_rtx (SET, VOIDmode,
3196: SET_DEST (old_body), ep->to_rtx);
3197: INSN_CODE (insn) = -1;
3198: val = 1;
3199: goto done;
3200: }
3201:
3202: break;
3203: }
3204: }
3205:
3206: old_asm_operands_vec = 0;
3207:
3208: /* Replace the body of this insn with a substituted form. If we changed
3209: something, return non-zero.
3210:
3211: If we are replacing a body that was a (set X (plus Y Z)), try to
3212: re-recognize the insn. We do this in case we had a simple addition
3213: but now can do this as a load-address. This saves an insn in this
3214: common case. */
3215:
3216: new_body = eliminate_regs (old_body, 0, replace ? insn : NULL_RTX);
3217: if (new_body != old_body)
3218: {
3219: /* If we aren't replacing things permanently and we changed something,
3220: make another copy to ensure that all the RTL is new. Otherwise
3221: things can go wrong if find_reload swaps commutative operands
3222: and one is inside RTL that has been copied while the other is not. */
3223:
3224: /* Don't copy an asm_operands because (1) there's no need and (2)
3225: copy_rtx can't do it properly when there are multiple outputs. */
3226: if (! replace && asm_noperands (old_body) < 0)
3227: new_body = copy_rtx (new_body);
3228:
3229: /* If we had a move insn but now we don't, rerecognize it. */
3230: if ((GET_CODE (old_body) == SET && GET_CODE (SET_SRC (old_body)) == REG
3231: && (GET_CODE (new_body) != SET
3232: || GET_CODE (SET_SRC (new_body)) != REG))
3233: /* If this was a load from or store to memory, compare
3234: the MEM in recog_operand to the one in the insn. If they
3235: are not equal, then rerecognize the insn. */
3236: || (GET_CODE (old_body) == SET
3237: && ((GET_CODE (SET_SRC (old_body)) == MEM
3238: && SET_SRC (old_body) != recog_operand[1])
3239: || (GET_CODE (SET_DEST (old_body)) == MEM
3240: && SET_DEST (old_body) != recog_operand[0])))
3241: /* If this was an add insn before, rerecognize. */
3242: ||
3243: (GET_CODE (old_body) == SET
3244: && GET_CODE (SET_SRC (old_body)) == PLUS))
3245: {
3246: if (! validate_change (insn, &PATTERN (insn), new_body, 0))
3247: /* If recognition fails, store the new body anyway.
3248: It's normal to have recognition failures here
3249: due to bizarre memory addresses; reloading will fix them. */
3250: PATTERN (insn) = new_body;
3251: }
3252: else
3253: PATTERN (insn) = new_body;
3254:
3255: val = 1;
3256: }
3257:
3258: /* Loop through all elimination pairs. See if any have changed and
3259: recalculate the number not at initial offset.
3260:
3261: Compute the maximum offset (minimum offset if the stack does not
3262: grow downward) for each elimination pair.
3263:
3264: We also detect a cases where register elimination cannot be done,
3265: namely, if a register would be both changed and referenced outside a MEM
3266: in the resulting insn since such an insn is often undefined and, even if
3267: not, we cannot know what meaning will be given to it. Note that it is
3268: valid to have a register used in an address in an insn that changes it
3269: (presumably with a pre- or post-increment or decrement).
3270:
3271: If anything changes, return nonzero. */
3272:
3273: num_not_at_initial_offset = 0;
3274: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3275: {
3276: if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3277: ep->can_eliminate = 0;
3278:
3279: ep->ref_outside_mem = 0;
3280:
3281: if (ep->previous_offset != ep->offset)
3282: val = 1;
3283:
3284: ep->previous_offset = ep->offset;
3285: if (ep->can_eliminate && ep->offset != ep->initial_offset)
3286: num_not_at_initial_offset++;
3287:
3288: #ifdef STACK_GROWS_DOWNWARD
3289: ep->max_offset = MAX (ep->max_offset, ep->offset);
3290: #else
3291: ep->max_offset = MIN (ep->max_offset, ep->offset);
3292: #endif
3293: }
3294:
3295: done:
3296: /* If we changed something, perform elmination in REG_NOTES. This is
3297: needed even when REPLACE is zero because a REG_DEAD note might refer
3298: to a register that we eliminate and could cause a different number
3299: of spill registers to be needed in the final reload pass than in
3300: the pre-passes. */
3301: if (val && REG_NOTES (insn) != 0)
3302: REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3303:
3304: if (! replace)
3305: pop_obstacks ();
3306:
3307: return val;
3308: }
3309:
3310: /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3311: replacement we currently believe is valid, mark it as not eliminable if X
3312: modifies DEST in any way other than by adding a constant integer to it.
3313:
3314: If DEST is the frame pointer, we do nothing because we assume that
3315: all assignments to the hard frame pointer are nonlocal gotos and are being
3316: done at a time when they are valid and do not disturb anything else.
3317: Some machines want to eliminate a fake argument pointer with either the
3318: frame or stack pointer. Assignments to the hard frame pointer must not
3319: prevent this elimination.
3320:
3321: Called via note_stores from reload before starting its passes to scan
3322: the insns of the function. */
3323:
3324: static void
3325: mark_not_eliminable (dest, x)
3326: rtx dest;
3327: rtx x;
3328: {
3329: register int i;
3330:
3331: /* A SUBREG of a hard register here is just changing its mode. We should
3332: not see a SUBREG of an eliminable hard register, but check just in
3333: case. */
3334: if (GET_CODE (dest) == SUBREG)
3335: dest = SUBREG_REG (dest);
3336:
3337: if (dest == hard_frame_pointer_rtx)
3338: return;
3339:
3340: for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3341: if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3342: && (GET_CODE (x) != SET
3343: || GET_CODE (SET_SRC (x)) != PLUS
3344: || XEXP (SET_SRC (x), 0) != dest
3345: || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3346: {
3347: reg_eliminate[i].can_eliminate_previous
3348: = reg_eliminate[i].can_eliminate = 0;
3349: num_eliminable--;
3350: }
3351: }
3352:
3353: /* Kick all pseudos out of hard register REGNO.
3354: If GLOBAL is nonzero, try to find someplace else to put them.
3355: If DUMPFILE is nonzero, log actions taken on that file.
3356:
3357: If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3358: because we found we can't eliminate some register. In the case, no pseudos
3359: are allowed to be in the register, even if they are only in a block that
3360: doesn't require spill registers, unlike the case when we are spilling this
3361: hard reg to produce another spill register.
3362:
3363: Return nonzero if any pseudos needed to be kicked out. */
3364:
3365: static int
3366: spill_hard_reg (regno, global, dumpfile, cant_eliminate)
3367: register int regno;
3368: int global;
3369: FILE *dumpfile;
3370: int cant_eliminate;
3371: {
3372: enum reg_class class = REGNO_REG_CLASS (regno);
3373: int something_changed = 0;
3374: register int i;
3375:
3376: SET_HARD_REG_BIT (forbidden_regs, regno);
3377:
3378: /* Spill every pseudo reg that was allocated to this reg
3379: or to something that overlaps this reg. */
3380:
3381: for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3382: if (reg_renumber[i] >= 0
3383: && reg_renumber[i] <= regno
3384: && (reg_renumber[i]
3385: + HARD_REGNO_NREGS (reg_renumber[i],
3386: PSEUDO_REGNO_MODE (i))
3387: > regno))
3388: {
3389: /* If this register belongs solely to a basic block which needed no
3390: spilling of any class that this register is contained in,
3391: leave it be, unless we are spilling this register because
3392: it was a hard register that can't be eliminated. */
3393:
3394: if (! cant_eliminate
3395: && basic_block_needs[0]
3396: && reg_basic_block[i] >= 0
3397: && basic_block_needs[(int) class][reg_basic_block[i]] == 0)
3398: {
3399: enum reg_class *p;
3400:
3401: for (p = reg_class_superclasses[(int) class];
3402: *p != LIM_REG_CLASSES; p++)
3403: if (basic_block_needs[(int) *p][reg_basic_block[i]] > 0)
3404: break;
3405:
3406: if (*p == LIM_REG_CLASSES)
3407: continue;
3408: }
3409:
3410: /* Mark it as no longer having a hard register home. */
3411: reg_renumber[i] = -1;
3412: /* We will need to scan everything again. */
3413: something_changed = 1;
3414: if (global)
3415: retry_global_alloc (i, forbidden_regs);
3416:
3417: alter_reg (i, regno);
3418: if (dumpfile)
3419: {
3420: if (reg_renumber[i] == -1)
3421: fprintf (dumpfile, " Register %d now on stack.\n\n", i);
3422: else
3423: fprintf (dumpfile, " Register %d now in %d.\n\n",
3424: i, reg_renumber[i]);
3425: }
3426: }
3427: for (i = 0; i < scratch_list_length; i++)
3428: {
3429: if (scratch_list[i] && REGNO (scratch_list[i]) == regno)
3430: {
3431: if (! cant_eliminate && basic_block_needs[0]
3432: && ! basic_block_needs[(int) class][scratch_block[i]])
3433: {
3434: enum reg_class *p;
3435:
3436: for (p = reg_class_superclasses[(int) class];
3437: *p != LIM_REG_CLASSES; p++)
3438: if (basic_block_needs[(int) *p][scratch_block[i]] > 0)
3439: break;
3440:
3441: if (*p == LIM_REG_CLASSES)
3442: continue;
3443: }
3444: PUT_CODE (scratch_list[i], SCRATCH);
3445: scratch_list[i] = 0;
3446: something_changed = 1;
3447: continue;
3448: }
3449: }
3450:
3451: return something_changed;
3452: }
3453:
3454: /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3455:
3456: static void
3457: scan_paradoxical_subregs (x)
3458: register rtx x;
3459: {
3460: register int i;
3461: register char *fmt;
3462: register enum rtx_code code = GET_CODE (x);
3463:
3464: switch (code)
3465: {
3466: case CONST_INT:
3467: case CONST:
3468: case SYMBOL_REF:
3469: case LABEL_REF:
3470: case CONST_DOUBLE:
3471: case CC0:
3472: case PC:
3473: case REG:
3474: case USE:
3475: case CLOBBER:
3476: return;
3477:
3478: case SUBREG:
3479: if (GET_CODE (SUBREG_REG (x)) == REG
3480: && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3481: reg_max_ref_width[REGNO (SUBREG_REG (x))]
3482: = GET_MODE_SIZE (GET_MODE (x));
3483: return;
3484: }
3485:
3486: fmt = GET_RTX_FORMAT (code);
3487: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3488: {
3489: if (fmt[i] == 'e')
3490: scan_paradoxical_subregs (XEXP (x, i));
3491: else if (fmt[i] == 'E')
3492: {
3493: register int j;
3494: for (j = XVECLEN (x, i) - 1; j >=0; j--)
3495: scan_paradoxical_subregs (XVECEXP (x, i, j));
3496: }
3497: }
3498: }
3499:
3500: static int
3501: hard_reg_use_compare (p1, p2)
3502: struct hard_reg_n_uses *p1, *p2;
3503: {
3504: int tem = p1->uses - p2->uses;
3505: if (tem != 0) return tem;
3506: /* If regs are equally good, sort by regno,
3507: so that the results of qsort leave nothing to chance. */
3508: return p1->regno - p2->regno;
3509: }
3510:
3511: /* Choose the order to consider regs for use as reload registers
3512: based on how much trouble would be caused by spilling one.
3513: Store them in order of decreasing preference in potential_reload_regs. */
3514:
3515: static void
3516: order_regs_for_reload ()
3517: {
3518: register int i;
3519: register int o = 0;
3520: int large = 0;
3521:
3522: struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER];
3523:
3524: CLEAR_HARD_REG_SET (bad_spill_regs);
3525:
3526: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3527: potential_reload_regs[i] = -1;
3528:
3529: /* Count number of uses of each hard reg by pseudo regs allocated to it
3530: and then order them by decreasing use. */
3531:
3532: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3533: {
3534: hard_reg_n_uses[i].uses = 0;
3535: hard_reg_n_uses[i].regno = i;
3536: }
3537:
3538: for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3539: {
3540: int regno = reg_renumber[i];
3541: if (regno >= 0)
3542: {
3543: int lim = regno + HARD_REGNO_NREGS (regno, PSEUDO_REGNO_MODE (i));
3544: while (regno < lim)
3545: hard_reg_n_uses[regno++].uses += reg_n_refs[i];
3546: }
3547: large += reg_n_refs[i];
3548: }
3549:
3550: /* Now fixed registers (which cannot safely be used for reloading)
3551: get a very high use count so they will be considered least desirable.
3552: Registers used explicitly in the rtl code are almost as bad. */
3553:
3554: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3555: {
3556: if (fixed_regs[i])
3557: {
3558: hard_reg_n_uses[i].uses += 2 * large + 2;
3559: SET_HARD_REG_BIT (bad_spill_regs, i);
3560: }
3561: else if (regs_explicitly_used[i])
3562: {
3563: hard_reg_n_uses[i].uses += large + 1;
3564: #ifndef SMALL_REGISTER_CLASSES
3565: /* ??? We are doing this here because of the potential that
3566: bad code may be generated if a register explicitly used in
3567: an insn was used as a spill register for that insn. But
3568: not using these are spill registers may lose on some machine.
3569: We'll have to see how this works out. */
3570: SET_HARD_REG_BIT (bad_spill_regs, i);
3571: #endif
3572: }
3573: }
3574: hard_reg_n_uses[HARD_FRAME_POINTER_REGNUM].uses += 2 * large + 2;
3575: SET_HARD_REG_BIT (bad_spill_regs, HARD_FRAME_POINTER_REGNUM);
3576:
3577: #ifdef ELIMINABLE_REGS
3578: /* If registers other than the frame pointer are eliminable, mark them as
3579: poor choices. */
3580: for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3581: {
3582: hard_reg_n_uses[reg_eliminate[i].from].uses += 2 * large + 2;
3583: SET_HARD_REG_BIT (bad_spill_regs, reg_eliminate[i].from);
3584: }
3585: #endif
3586:
3587: /* Prefer registers not so far used, for use in temporary loading.
3588: Among them, if REG_ALLOC_ORDER is defined, use that order.
3589: Otherwise, prefer registers not preserved by calls. */
3590:
3591: #ifdef REG_ALLOC_ORDER
3592: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3593: {
3594: int regno = reg_alloc_order[i];
3595:
3596: if (hard_reg_n_uses[regno].uses == 0)
3597: potential_reload_regs[o++] = regno;
3598: }
3599: #else
3600: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3601: {
3602: if (hard_reg_n_uses[i].uses == 0 && call_used_regs[i])
3603: potential_reload_regs[o++] = i;
3604: }
3605: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3606: {
3607: if (hard_reg_n_uses[i].uses == 0 && ! call_used_regs[i])
3608: potential_reload_regs[o++] = i;
3609: }
3610: #endif
3611:
3612: qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER,
3613: sizeof hard_reg_n_uses[0], hard_reg_use_compare);
3614:
3615: /* Now add the regs that are already used,
3616: preferring those used less often. The fixed and otherwise forbidden
3617: registers will be at the end of this list. */
3618:
3619: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3620: if (hard_reg_n_uses[i].uses != 0)
3621: potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
3622: }
3623:
3624: /* Reload pseudo-registers into hard regs around each insn as needed.
3625: Additional register load insns are output before the insn that needs it
3626: and perhaps store insns after insns that modify the reloaded pseudo reg.
3627:
3628: reg_last_reload_reg and reg_reloaded_contents keep track of
3629: which registers are already available in reload registers.
3630: We update these for the reloads that we perform,
3631: as the insns are scanned. */
3632:
3633: static void
3634: reload_as_needed (first, live_known)
3635: rtx first;
3636: int live_known;
3637: {
3638: register rtx insn;
3639: register int i;
3640: int this_block = 0;
3641: rtx x;
3642: rtx after_call = 0;
3643:
3644: bzero (spill_reg_rtx, sizeof spill_reg_rtx);
3645: reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx));
3646: bzero (reg_last_reload_reg, max_regno * sizeof (rtx));
3647: reg_has_output_reload = (char *) alloca (max_regno);
3648: for (i = 0; i < n_spills; i++)
3649: {
3650: reg_reloaded_contents[i] = -1;
3651: reg_reloaded_insn[i] = 0;
3652: }
3653:
3654: /* Reset all offsets on eliminable registers to their initial values. */
3655: #ifdef ELIMINABLE_REGS
3656: for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3657: {
3658: INITIAL_ELIMINATION_OFFSET (reg_eliminate[i].from, reg_eliminate[i].to,
3659: reg_eliminate[i].initial_offset);
3660: reg_eliminate[i].previous_offset
3661: = reg_eliminate[i].offset = reg_eliminate[i].initial_offset;
3662: }
3663: #else
3664: INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
3665: reg_eliminate[0].previous_offset
3666: = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
3667: #endif
3668:
3669: num_not_at_initial_offset = 0;
3670:
3671: for (insn = first; insn;)
3672: {
3673: register rtx next = NEXT_INSN (insn);
3674:
3675: /* Notice when we move to a new basic block. */
3676: if (live_known && this_block + 1 < n_basic_blocks
3677: && insn == basic_block_head[this_block+1])
3678: ++this_block;
3679:
3680: /* If we pass a label, copy the offsets from the label information
3681: into the current offsets of each elimination. */
3682: if (GET_CODE (insn) == CODE_LABEL)
3683: {
3684: num_not_at_initial_offset = 0;
3685: for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3686: {
3687: reg_eliminate[i].offset = reg_eliminate[i].previous_offset
3688: = offsets_at[CODE_LABEL_NUMBER (insn)][i];
3689: if (reg_eliminate[i].can_eliminate
3690: && (reg_eliminate[i].offset
3691: != reg_eliminate[i].initial_offset))
3692: num_not_at_initial_offset++;
3693: }
3694: }
3695:
3696: else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
3697: {
3698: rtx avoid_return_reg = 0;
3699:
3700: #ifdef SMALL_REGISTER_CLASSES
3701: /* Set avoid_return_reg if this is an insn
3702: that might use the value of a function call. */
3703: if (GET_CODE (insn) == CALL_INSN)
3704: {
3705: if (GET_CODE (PATTERN (insn)) == SET)
3706: after_call = SET_DEST (PATTERN (insn));
3707: else if (GET_CODE (PATTERN (insn)) == PARALLEL
3708: && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
3709: after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
3710: else
3711: after_call = 0;
3712: }
3713: else if (after_call != 0
3714: && !(GET_CODE (PATTERN (insn)) == SET
3715: && SET_DEST (PATTERN (insn)) == stack_pointer_rtx))
3716: {
3717: if (reg_mentioned_p (after_call, PATTERN (insn)))
3718: avoid_return_reg = after_call;
3719: after_call = 0;
3720: }
3721: #endif /* SMALL_REGISTER_CLASSES */
3722:
3723: /* If this is a USE and CLOBBER of a MEM, ensure that any
3724: references to eliminable registers have been removed. */
3725:
3726: if ((GET_CODE (PATTERN (insn)) == USE
3727: || GET_CODE (PATTERN (insn)) == CLOBBER)
3728: && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3729: XEXP (XEXP (PATTERN (insn), 0), 0)
3730: = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3731: GET_MODE (XEXP (PATTERN (insn), 0)), NULL_RTX);
3732:
3733: /* If we need to do register elimination processing, do so.
3734: This might delete the insn, in which case we are done. */
3735: if (num_eliminable && GET_MODE (insn) == QImode)
3736: {
3737: eliminate_regs_in_insn (insn, 1);
3738: if (GET_CODE (insn) == NOTE)
3739: {
3740: insn = next;
3741: continue;
3742: }
3743: }
3744:
3745: if (GET_MODE (insn) == VOIDmode)
3746: n_reloads = 0;
3747: /* First find the pseudo regs that must be reloaded for this insn.
3748: This info is returned in the tables reload_... (see reload.h).
3749: Also modify the body of INSN by substituting RELOAD
3750: rtx's for those pseudo regs. */
3751: else
3752: {
3753: bzero (reg_has_output_reload, max_regno);
3754: CLEAR_HARD_REG_SET (reg_is_output_reload);
3755:
3756: find_reloads (insn, 1, spill_indirect_levels, live_known,
3757: spill_reg_order);
3758: }
3759:
3760: if (n_reloads > 0)
3761: {
3762: rtx prev = PREV_INSN (insn), next = NEXT_INSN (insn);
3763: rtx p;
3764: int class;
3765:
3766: /* If this block has not had spilling done for a
3767: particular clas and we have any non-optionals that need a
3768: spill reg in that class, abort. */
3769:
3770: for (class = 0; class < N_REG_CLASSES; class++)
3771: if (basic_block_needs[class] != 0
3772: && basic_block_needs[class][this_block] == 0)
3773: for (i = 0; i < n_reloads; i++)
3774: if (class == (int) reload_reg_class[i]
3775: && reload_reg_rtx[i] == 0
3776: && ! reload_optional[i]
3777: && (reload_in[i] != 0 || reload_out[i] != 0
3778: || reload_secondary_p[i] != 0))
3779: abort ();
3780:
3781: /* Now compute which reload regs to reload them into. Perhaps
3782: reusing reload regs from previous insns, or else output
3783: load insns to reload them. Maybe output store insns too.
3784: Record the choices of reload reg in reload_reg_rtx. */
3785: choose_reload_regs (insn, avoid_return_reg);
3786:
3787: #ifdef SMALL_REGISTER_CLASSES
3788: /* Merge any reloads that we didn't combine for fear of
3789: increasing the number of spill registers needed but now
3790: discover can be safely merged. */
3791: merge_assigned_reloads (insn);
3792: #endif
3793:
3794: /* Generate the insns to reload operands into or out of
3795: their reload regs. */
3796: emit_reload_insns (insn);
3797:
3798: /* Substitute the chosen reload regs from reload_reg_rtx
3799: into the insn's body (or perhaps into the bodies of other
3800: load and store insn that we just made for reloading
3801: and that we moved the structure into). */
3802: subst_reloads ();
3803:
3804: /* If this was an ASM, make sure that all the reload insns
3805: we have generated are valid. If not, give an error
3806: and delete them. */
3807:
3808: if (asm_noperands (PATTERN (insn)) >= 0)
3809: for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3810: if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
3811: && (recog_memoized (p) < 0
3812: || (insn_extract (p),
3813: ! constrain_operands (INSN_CODE (p), 1))))
3814: {
3815: error_for_asm (insn,
3816: "`asm' operand requires impossible reload");
3817: PUT_CODE (p, NOTE);
3818: NOTE_SOURCE_FILE (p) = 0;
3819: NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
3820: }
3821: }
3822: /* Any previously reloaded spilled pseudo reg, stored in this insn,
3823: is no longer validly lying around to save a future reload.
3824: Note that this does not detect pseudos that were reloaded
3825: for this insn in order to be stored in
3826: (obeying register constraints). That is correct; such reload
3827: registers ARE still valid. */
3828: note_stores (PATTERN (insn), forget_old_reloads_1);
3829:
3830: /* There may have been CLOBBER insns placed after INSN. So scan
3831: between INSN and NEXT and use them to forget old reloads. */
3832: for (x = NEXT_INSN (insn); x != next; x = NEXT_INSN (x))
3833: if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3834: note_stores (PATTERN (x), forget_old_reloads_1);
3835:
3836: #ifdef AUTO_INC_DEC
3837: /* Likewise for regs altered by auto-increment in this insn.
3838: But note that the reg-notes are not changed by reloading:
3839: they still contain the pseudo-regs, not the spill regs. */
3840: for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
3841: if (REG_NOTE_KIND (x) == REG_INC)
3842: {
3843: /* See if this pseudo reg was reloaded in this insn.
3844: If so, its last-reload info is still valid
3845: because it is based on this insn's reload. */
3846: for (i = 0; i < n_reloads; i++)
3847: if (reload_out[i] == XEXP (x, 0))
3848: break;
3849:
3850: if (i == n_reloads)
3851: forget_old_reloads_1 (XEXP (x, 0), NULL_RTX);
3852: }
3853: #endif
3854: }
3855: /* A reload reg's contents are unknown after a label. */
3856: if (GET_CODE (insn) == CODE_LABEL)
3857: for (i = 0; i < n_spills; i++)
3858: {
3859: reg_reloaded_contents[i] = -1;
3860: reg_reloaded_insn[i] = 0;
3861: }
3862:
3863: /* Don't assume a reload reg is still good after a call insn
3864: if it is a call-used reg. */
3865: else if (GET_CODE (insn) == CALL_INSN)
3866: for (i = 0; i < n_spills; i++)
3867: if (call_used_regs[spill_regs[i]])
3868: {
3869: reg_reloaded_contents[i] = -1;
3870: reg_reloaded_insn[i] = 0;
3871: }
3872:
3873: /* In case registers overlap, allow certain insns to invalidate
3874: particular hard registers. */
3875:
3876: #ifdef INSN_CLOBBERS_REGNO_P
3877: for (i = 0 ; i < n_spills ; i++)
3878: if (INSN_CLOBBERS_REGNO_P (insn, spill_regs[i]))
3879: {
3880: reg_reloaded_contents[i] = -1;
3881: reg_reloaded_insn[i] = 0;
3882: }
3883: #endif
3884:
3885: insn = next;
3886:
3887: #ifdef USE_C_ALLOCA
3888: alloca (0);
3889: #endif
3890: }
3891: }
3892:
3893: /* Discard all record of any value reloaded from X,
3894: or reloaded in X from someplace else;
3895: unless X is an output reload reg of the current insn.
3896:
3897: X may be a hard reg (the reload reg)
3898: or it may be a pseudo reg that was reloaded from. */
3899:
3900: static void
3901: forget_old_reloads_1 (x, ignored)
3902: rtx x;
3903: rtx ignored;
3904: {
3905: register int regno;
3906: int nr;
3907: int offset = 0;
3908:
3909: /* note_stores does give us subregs of hard regs. */
3910: while (GET_CODE (x) == SUBREG)
3911: {
3912: offset += SUBREG_WORD (x);
3913: x = SUBREG_REG (x);
3914: }
3915:
3916: if (GET_CODE (x) != REG)
3917: return;
3918:
3919: regno = REGNO (x) + offset;
3920:
3921: if (regno >= FIRST_PSEUDO_REGISTER)
3922: nr = 1;
3923: else
3924: {
3925: int i;
3926: nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
3927: /* Storing into a spilled-reg invalidates its contents.
3928: This can happen if a block-local pseudo is allocated to that reg
3929: and it wasn't spilled because this block's total need is 0.
3930: Then some insn might have an optional reload and use this reg. */
3931: for (i = 0; i < nr; i++)
3932: if (spill_reg_order[regno + i] >= 0
3933: /* But don't do this if the reg actually serves as an output
3934: reload reg in the current instruction. */
3935: && (n_reloads == 0
3936: || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i)))
3937: {
3938: reg_reloaded_contents[spill_reg_order[regno + i]] = -1;
3939: reg_reloaded_insn[spill_reg_order[regno + i]] = 0;
3940: }
3941: }
3942:
3943: /* Since value of X has changed,
3944: forget any value previously copied from it. */
3945:
3946: while (nr-- > 0)
3947: /* But don't forget a copy if this is the output reload
3948: that establishes the copy's validity. */
3949: if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
3950: reg_last_reload_reg[regno + nr] = 0;
3951: }
3952:
3953: /* For each reload, the mode of the reload register. */
3954: static enum machine_mode reload_mode[MAX_RELOADS];
3955:
3956: /* For each reload, the largest number of registers it will require. */
3957: static int reload_nregs[MAX_RELOADS];
3958:
3959: /* Comparison function for qsort to decide which of two reloads
3960: should be handled first. *P1 and *P2 are the reload numbers. */
3961:
3962: static int
3963: reload_reg_class_lower (p1, p2)
3964: short *p1, *p2;
3965: {
3966: register int r1 = *p1, r2 = *p2;
3967: register int t;
3968:
3969: /* Consider required reloads before optional ones. */
3970: t = reload_optional[r1] - reload_optional[r2];
3971: if (t != 0)
3972: return t;
3973:
3974: /* Count all solitary classes before non-solitary ones. */
3975: t = ((reg_class_size[(int) reload_reg_class[r2]] == 1)
3976: - (reg_class_size[(int) reload_reg_class[r1]] == 1));
3977: if (t != 0)
3978: return t;
3979:
3980: /* Aside from solitaires, consider all multi-reg groups first. */
3981: t = reload_nregs[r2] - reload_nregs[r1];
3982: if (t != 0)
3983: return t;
3984:
3985: /* Consider reloads in order of increasing reg-class number. */
3986: t = (int) reload_reg_class[r1] - (int) reload_reg_class[r2];
3987: if (t != 0)
3988: return t;
3989:
3990: /* If reloads are equally urgent, sort by reload number,
3991: so that the results of qsort leave nothing to chance. */
3992: return r1 - r2;
3993: }
3994:
3995: /* The following HARD_REG_SETs indicate when each hard register is
3996: used for a reload of various parts of the current insn. */
3997:
3998: /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
3999: static HARD_REG_SET reload_reg_used;
4000: /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4001: static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4002: /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4003: static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4004: /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4005: static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4006: /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4007: static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4008: /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4009: static HARD_REG_SET reload_reg_used_in_op_addr;
4010: /* If reg is in use for a RELOAD_FOR_INSN reload. */
4011: static HARD_REG_SET reload_reg_used_in_insn;
4012: /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4013: static HARD_REG_SET reload_reg_used_in_other_addr;
4014:
4015: /* If reg is in use as a reload reg for any sort of reload. */
4016: static HARD_REG_SET reload_reg_used_at_all;
4017:
4018: /* If reg is use as an inherited reload. We just mark the first register
4019: in the group. */
4020: static HARD_REG_SET reload_reg_used_for_inherit;
4021:
4022: /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4023: TYPE. MODE is used to indicate how many consecutive regs are
4024: actually used. */
4025:
4026: static void
4027: mark_reload_reg_in_use (regno, opnum, type, mode)
4028: int regno;
4029: int opnum;
4030: enum reload_type type;
4031: enum machine_mode mode;
4032: {
4033: int nregs = HARD_REGNO_NREGS (regno, mode);
4034: int i;
4035:
4036: for (i = regno; i < nregs + regno; i++)
4037: {
4038: switch (type)
4039: {
4040: case RELOAD_OTHER:
4041: SET_HARD_REG_BIT (reload_reg_used, i);
4042: break;
4043:
4044: case RELOAD_FOR_INPUT_ADDRESS:
4045: SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4046: break;
4047:
4048: case RELOAD_FOR_OUTPUT_ADDRESS:
4049: SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4050: break;
4051:
4052: case RELOAD_FOR_OPERAND_ADDRESS:
4053: SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4054: break;
4055:
4056: case RELOAD_FOR_OTHER_ADDRESS:
4057: SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4058: break;
4059:
4060: case RELOAD_FOR_INPUT:
4061: SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4062: break;
4063:
4064: case RELOAD_FOR_OUTPUT:
4065: SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4066: break;
4067:
4068: case RELOAD_FOR_INSN:
4069: SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4070: break;
4071: }
4072:
4073: SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4074: }
4075: }
4076:
4077: /* Similarly, but show REGNO is no longer in use for a reload. */
4078:
4079: static void
4080: clear_reload_reg_in_use (regno, opnum, type, mode)
4081: int regno;
4082: int opnum;
4083: enum reload_type type;
4084: enum machine_mode mode;
4085: {
4086: int nregs = HARD_REGNO_NREGS (regno, mode);
4087: int i;
4088:
4089: for (i = regno; i < nregs + regno; i++)
4090: {
4091: switch (type)
4092: {
4093: case RELOAD_OTHER:
4094: CLEAR_HARD_REG_BIT (reload_reg_used, i);
4095: break;
4096:
4097: case RELOAD_FOR_INPUT_ADDRESS:
4098: CLEAR_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4099: break;
4100:
4101: case RELOAD_FOR_OUTPUT_ADDRESS:
4102: CLEAR_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4103: break;
4104:
4105: case RELOAD_FOR_OPERAND_ADDRESS:
4106: CLEAR_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4107: break;
4108:
4109: case RELOAD_FOR_OTHER_ADDRESS:
4110: CLEAR_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4111: break;
4112:
4113: case RELOAD_FOR_INPUT:
4114: CLEAR_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4115: break;
4116:
4117: case RELOAD_FOR_OUTPUT:
4118: CLEAR_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4119: break;
4120:
4121: case RELOAD_FOR_INSN:
4122: CLEAR_HARD_REG_BIT (reload_reg_used_in_insn, i);
4123: break;
4124: }
4125: }
4126: }
4127:
4128: /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4129: specified by OPNUM and TYPE. */
4130:
4131: static int
4132: reload_reg_free_p (regno, opnum, type)
4133: int regno;
4134: int opnum;
4135: enum reload_type type;
4136: {
4137: int i;
4138:
4139: /* In use for a RELOAD_OTHER means it's not available for anything except
4140: RELOAD_FOR_OTHER_ADDRESS. Recall that RELOAD_FOR_OTHER_ADDRESS is known
4141: to be used only for inputs. */
4142:
4143: if (type != RELOAD_FOR_OTHER_ADDRESS
4144: && TEST_HARD_REG_BIT (reload_reg_used, regno))
4145: return 0;
4146:
4147: switch (type)
4148: {
4149: case RELOAD_OTHER:
4150: /* In use for anything means not available for a RELOAD_OTHER. */
4151: return ! TEST_HARD_REG_BIT (reload_reg_used_at_all, regno);
4152:
4153: /* The other kinds of use can sometimes share a register. */
4154: case RELOAD_FOR_INPUT:
4155: if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4156: || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4157: return 0;
4158:
4159: /* If it is used for some other input, can't use it. */
4160: for (i = 0; i < reload_n_operands; i++)
4161: if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4162: return 0;
4163:
4164: /* If it is used in a later operand's address, can't use it. */
4165: for (i = opnum + 1; i < reload_n_operands; i++)
4166: if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4167: return 0;
4168:
4169: return 1;
4170:
4171: case RELOAD_FOR_INPUT_ADDRESS:
4172: /* Can't use a register if it is used for an input address for this
4173: operand or used as an input in an earlier one. */
4174: if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno))
4175: return 0;
4176:
4177: for (i = 0; i < opnum; i++)
4178: if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4179: return 0;
4180:
4181: return 1;
4182:
4183: case RELOAD_FOR_OUTPUT_ADDRESS:
4184: /* Can't use a register if it is used for an output address for this
4185: operand or used as an output in this or a later operand. */
4186: if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4187: return 0;
4188:
4189: for (i = opnum; i < reload_n_operands; i++)
4190: if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4191: return 0;
4192:
4193: return 1;
4194:
4195: case RELOAD_FOR_OPERAND_ADDRESS:
4196: for (i = 0; i < reload_n_operands; i++)
4197: if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4198: return 0;
4199:
4200: return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4201: && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4202:
4203: case RELOAD_FOR_OUTPUT:
4204: /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4205: outputs, or an operand address for this or an earlier output. */
4206: if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4207: return 0;
4208:
4209: for (i = 0; i < reload_n_operands; i++)
4210: if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4211: return 0;
4212:
4213: for (i = 0; i <= opnum; i++)
4214: if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno))
4215: return 0;
4216:
4217: return 1;
4218:
4219: case RELOAD_FOR_INSN:
4220: for (i = 0; i < reload_n_operands; i++)
4221: if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4222: || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4223: return 0;
4224:
4225: return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4226: && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4227:
4228: case RELOAD_FOR_OTHER_ADDRESS:
4229: return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4230: }
4231: abort ();
4232: }
4233:
4234: /* Return 1 if the value in reload reg REGNO, as used by a reload
4235: needed for the part of the insn specified by OPNUM and TYPE,
4236: is not in use for a reload in any prior part of the insn.
4237:
4238: We can assume that the reload reg was already tested for availability
4239: at the time it is needed, and we should not check this again,
4240: in case the reg has already been marked in use. */
4241:
4242: static int
4243: reload_reg_free_before_p (regno, opnum, type)
4244: int regno;
4245: int opnum;
4246: enum reload_type type;
4247: {
4248: int i;
4249:
4250: switch (type)
4251: {
4252: case RELOAD_FOR_OTHER_ADDRESS:
4253: /* These always come first. */
4254: return 1;
4255:
4256: case RELOAD_OTHER:
4257: return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4258:
4259: /* If this use is for part of the insn,
4260: check the reg is not in use for any prior part. It is tempting
4261: to try to do this by falling through from objecs that occur
4262: later in the insn to ones that occur earlier, but that will not
4263: correctly take into account the fact that here we MUST ignore
4264: things that would prevent the register from being allocated in
4265: the first place, since we know that it was allocated. */
4266:
4267: case RELOAD_FOR_OUTPUT_ADDRESS:
4268: /* Earlier reloads are for earlier outputs or their addresses,
4269: any RELOAD_FOR_INSN reloads, any inputs or their addresses, or any
4270: RELOAD_FOR_OTHER_ADDRESS reloads (we know it can't conflict with
4271: RELOAD_OTHER).. */
4272: for (i = 0; i < opnum; i++)
4273: if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4274: || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4275: return 0;
4276:
4277: if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4278: return 0;
4279:
4280: for (i = 0; i < reload_n_operands; i++)
4281: if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4282: || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4283: return 0;
4284:
4285: return (! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4286: && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4287: && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4288:
4289: case RELOAD_FOR_OUTPUT:
4290: /* This can't be used in the output address for this operand and
4291: anything that can't be used for it, except that we've already
4292: tested for RELOAD_FOR_INSN objects. */
4293:
4294: if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4295: return 0;
4296:
4297: for (i = 0; i < opnum; i++)
4298: if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4299: || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4300: return 0;
4301:
4302: for (i = 0; i < reload_n_operands; i++)
4303: if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4304: || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4305: || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4306: return 0;
4307:
4308: return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4309:
4310: case RELOAD_FOR_OPERAND_ADDRESS:
4311: case RELOAD_FOR_INSN:
4312: /* These can't conflict with inputs, or each other, so all we have to
4313: test is input addresses and the addresses of OTHER items. */
4314:
4315: for (i = 0; i < reload_n_operands; i++)
4316: if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4317: return 0;
4318:
4319: return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4320:
4321: case RELOAD_FOR_INPUT:
4322: /* The only things earlier are the address for this and
4323: earlier inputs, other inputs (which we know we don't conflict
4324: with), and addresses of RELOAD_OTHER objects. */
4325:
4326: for (i = 0; i <= opnum; i++)
4327: if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4328: return 0;
4329:
4330: return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4331:
4332: case RELOAD_FOR_INPUT_ADDRESS:
4333: /* Similarly, all we have to check is for use in earlier inputs'
4334: addresses. */
4335: for (i = 0; i < opnum; i++)
4336: if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4337: return 0;
4338:
4339: return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4340: }
4341: abort ();
4342: }
4343:
4344: /* Return 1 if the value in reload reg REGNO, as used by a reload
4345: needed for the part of the insn specified by OPNUM and TYPE,
4346: is still available in REGNO at the end of the insn.
4347:
4348: We can assume that the reload reg was already tested for availability
4349: at the time it is needed, and we should not check this again,
4350: in case the reg has already been marked in use. */
4351:
4352: static int
4353: reload_reg_reaches_end_p (regno, opnum, type)
4354: int regno;
4355: int opnum;
4356: enum reload_type type;
4357: {
4358: int i;
4359:
4360: switch (type)
4361: {
4362: case RELOAD_OTHER:
4363: /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4364: its value must reach the end. */
4365: return 1;
4366:
4367: /* If this use is for part of the insn,
4368: its value reaches if no subsequent part uses the same register.
4369: Just like the above function, don't try to do this with lots
4370: of fallthroughs. */
4371:
4372: case RELOAD_FOR_OTHER_ADDRESS:
4373: /* Here we check for everything else, since these don't conflict
4374: with anything else and everything comes later. */
4375:
4376: for (i = 0; i < reload_n_operands; i++)
4377: if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4378: || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4379: || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4380: || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4381: return 0;
4382:
4383: return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4384: && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4385: && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4386:
4387: case RELOAD_FOR_INPUT_ADDRESS:
4388: /* Similar, except that we check only for this and subsequent inputs
4389: and the address of only subsequent inputs and we do not need
4390: to check for RELOAD_OTHER objects since they are known not to
4391: conflict. */
4392:
4393: for (i = opnum; i < reload_n_operands; i++)
4394: if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4395: return 0;
4396:
4397: for (i = opnum + 1; i < reload_n_operands; i++)
4398: if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4399: return 0;
4400:
4401: for (i = 0; i < reload_n_operands; i++)
4402: if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4403: || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4404: return 0;
4405:
4406: return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4407: && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4408:
4409: case RELOAD_FOR_INPUT:
4410: /* Similar to input address, except we start at the next operand for
4411: both input and input address and we do not check for
4412: RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4413: would conflict. */
4414:
4415: for (i = opnum + 1; i < reload_n_operands; i++)
4416: if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4417: || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4418: return 0;
4419:
4420: /* ... fall through ... */
4421:
4422: case RELOAD_FOR_OPERAND_ADDRESS:
4423: /* Check outputs and their addresses. */
4424:
4425: for (i = 0; i < reload_n_operands; i++)
4426: if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4427: || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4428: return 0;
4429:
4430: return 1;
4431:
4432: case RELOAD_FOR_INSN:
4433: /* These conflict with other outputs with with RELOAD_OTHER. So
4434: we need only check for output addresses. */
4435:
4436: opnum = -1;
4437:
4438: /* ... fall through ... */
4439:
4440: case RELOAD_FOR_OUTPUT:
4441: case RELOAD_FOR_OUTPUT_ADDRESS:
4442: /* We already know these can't conflict with a later output. So the
4443: only thing to check are later output addresses. */
4444: for (i = opnum + 1; i < reload_n_operands; i++)
4445: if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno))
4446: return 0;
4447:
4448: return 1;
4449: }
4450:
4451: abort ();
4452: }
4453:
4454: /* Vector of reload-numbers showing the order in which the reloads should
4455: be processed. */
4456: short reload_order[MAX_RELOADS];
4457:
4458: /* Indexed by reload number, 1 if incoming value
4459: inherited from previous insns. */
4460: char reload_inherited[MAX_RELOADS];
4461:
4462: /* For an inherited reload, this is the insn the reload was inherited from,
4463: if we know it. Otherwise, this is 0. */
4464: rtx reload_inheritance_insn[MAX_RELOADS];
4465:
4466: /* If non-zero, this is a place to get the value of the reload,
4467: rather than using reload_in. */
4468: rtx reload_override_in[MAX_RELOADS];
4469:
4470: /* For each reload, the index in spill_regs of the spill register used,
4471: or -1 if we did not need one of the spill registers for this reload. */
4472: int reload_spill_index[MAX_RELOADS];
4473:
4474: /* Index of last register assigned as a spill register. We allocate in
4475: a round-robin fashio. */
4476:
4477: static int last_spill_reg = 0;
4478:
4479: /* Find a spill register to use as a reload register for reload R.
4480: LAST_RELOAD is non-zero if this is the last reload for the insn being
4481: processed.
4482:
4483: Set reload_reg_rtx[R] to the register allocated.
4484:
4485: If NOERROR is nonzero, we return 1 if successful,
4486: or 0 if we couldn't find a spill reg and we didn't change anything. */
4487:
4488: static int
4489: allocate_reload_reg (r, insn, last_reload, noerror)
4490: int r;
4491: rtx insn;
4492: int last_reload;
4493: int noerror;
4494: {
4495: int i;
4496: int pass;
4497: int count;
4498: rtx new;
4499: int regno;
4500:
4501: /* If we put this reload ahead, thinking it is a group,
4502: then insist on finding a group. Otherwise we can grab a
4503: reg that some other reload needs.
4504: (That can happen when we have a 68000 DATA_OR_FP_REG
4505: which is a group of data regs or one fp reg.)
4506: We need not be so restrictive if there are no more reloads
4507: for this insn.
4508:
4509: ??? Really it would be nicer to have smarter handling
4510: for that kind of reg class, where a problem like this is normal.
4511: Perhaps those classes should be avoided for reloading
4512: by use of more alternatives. */
4513:
4514: int force_group = reload_nregs[r] > 1 && ! last_reload;
4515:
4516: /* If we want a single register and haven't yet found one,
4517: take any reg in the right class and not in use.
4518: If we want a consecutive group, here is where we look for it.
4519:
4520: We use two passes so we can first look for reload regs to
4521: reuse, which are already in use for other reloads in this insn,
4522: and only then use additional registers.
4523: I think that maximizing reuse is needed to make sure we don't
4524: run out of reload regs. Suppose we have three reloads, and
4525: reloads A and B can share regs. These need two regs.
4526: Suppose A and B are given different regs.
4527: That leaves none for C. */
4528: for (pass = 0; pass < 2; pass++)
4529: {
4530: /* I is the index in spill_regs.
4531: We advance it round-robin between insns to use all spill regs
4532: equally, so that inherited reloads have a chance
4533: of leapfrogging each other. */
4534:
4535: for (count = 0, i = last_spill_reg; count < n_spills; count++)
4536: {
4537: int class = (int) reload_reg_class[r];
4538:
4539: i = (i + 1) % n_spills;
4540:
4541: if (reload_reg_free_p (spill_regs[i], reload_opnum[r],
4542: reload_when_needed[r])
4543: && TEST_HARD_REG_BIT (reg_class_contents[class], spill_regs[i])
4544: && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r])
4545: /* Look first for regs to share, then for unshared. But
4546: don't share regs used for inherited reloads; they are
4547: the ones we want to preserve. */
4548: && (pass
4549: || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
4550: spill_regs[i])
4551: && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
4552: spill_regs[i]))))
4553: {
4554: int nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
4555: /* Avoid the problem where spilling a GENERAL_OR_FP_REG
4556: (on 68000) got us two FP regs. If NR is 1,
4557: we would reject both of them. */
4558: if (force_group)
4559: nr = CLASS_MAX_NREGS (reload_reg_class[r], reload_mode[r]);
4560: /* If we need only one reg, we have already won. */
4561: if (nr == 1)
4562: {
4563: /* But reject a single reg if we demand a group. */
4564: if (force_group)
4565: continue;
4566: break;
4567: }
4568: /* Otherwise check that as many consecutive regs as we need
4569: are available here.
4570: Also, don't use for a group registers that are
4571: needed for nongroups. */
4572: if (! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]))
4573: while (nr > 1)
4574: {
4575: regno = spill_regs[i] + nr - 1;
4576: if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
4577: && spill_reg_order[regno] >= 0
4578: && reload_reg_free_p (regno, reload_opnum[r],
4579: reload_when_needed[r])
4580: && ! TEST_HARD_REG_BIT (counted_for_nongroups,
4581: regno)))
4582: break;
4583: nr--;
4584: }
4585: if (nr == 1)
4586: break;
4587: }
4588: }
4589:
4590: /* If we found something on pass 1, omit pass 2. */
4591: if (count < n_spills)
4592: break;
4593: }
4594:
4595: /* We should have found a spill register by now. */
4596: if (count == n_spills)
4597: {
4598: if (noerror)
4599: return 0;
4600: goto failure;
4601: }
4602:
4603: /* I is the index in SPILL_REG_RTX of the reload register we are to
4604: allocate. Get an rtx for it and find its register number. */
4605:
4606: new = spill_reg_rtx[i];
4607:
4608: if (new == 0 || GET_MODE (new) != reload_mode[r])
4609: spill_reg_rtx[i] = new
4610: = gen_rtx (REG, reload_mode[r], spill_regs[i]);
4611:
4612: regno = true_regnum (new);
4613:
4614: /* Detect when the reload reg can't hold the reload mode.
4615: This used to be one `if', but Sequent compiler can't handle that. */
4616: if (HARD_REGNO_MODE_OK (regno, reload_mode[r]))
4617: {
4618: enum machine_mode test_mode = VOIDmode;
4619: if (reload_in[r])
4620: test_mode = GET_MODE (reload_in[r]);
4621: /* If reload_in[r] has VOIDmode, it means we will load it
4622: in whatever mode the reload reg has: to wit, reload_mode[r].
4623: We have already tested that for validity. */
4624: /* Aside from that, we need to test that the expressions
4625: to reload from or into have modes which are valid for this
4626: reload register. Otherwise the reload insns would be invalid. */
4627: if (! (reload_in[r] != 0 && test_mode != VOIDmode
4628: && ! HARD_REGNO_MODE_OK (regno, test_mode)))
4629: if (! (reload_out[r] != 0
4630: && ! HARD_REGNO_MODE_OK (regno, GET_MODE (reload_out[r]))))
4631: {
4632: /* The reg is OK. */
4633: last_spill_reg = i;
4634:
4635: /* Mark as in use for this insn the reload regs we use
4636: for this. */
4637: mark_reload_reg_in_use (spill_regs[i], reload_opnum[r],
4638: reload_when_needed[r], reload_mode[r]);
4639:
4640: reload_reg_rtx[r] = new;
4641: reload_spill_index[r] = i;
4642: return 1;
4643: }
4644: }
4645:
4646: /* The reg is not OK. */
4647: if (noerror)
4648: return 0;
4649:
4650: failure:
4651: if (asm_noperands (PATTERN (insn)) < 0)
4652: /* It's the compiler's fault. */
4653: abort ();
4654:
4655: /* It's the user's fault; the operand's mode and constraint
4656: don't match. Disable this reload so we don't crash in final. */
4657: error_for_asm (insn,
4658: "`asm' operand constraint incompatible with operand size");
4659: reload_in[r] = 0;
4660: reload_out[r] = 0;
4661: reload_reg_rtx[r] = 0;
4662: reload_optional[r] = 1;
4663: reload_secondary_p[r] = 1;
4664:
4665: return 1;
4666: }
4667:
4668: /* Assign hard reg targets for the pseudo-registers we must reload
4669: into hard regs for this insn.
4670: Also output the instructions to copy them in and out of the hard regs.
4671:
4672: For machines with register classes, we are responsible for
4673: finding a reload reg in the proper class. */
4674:
4675: static void
4676: choose_reload_regs (insn, avoid_return_reg)
4677: rtx insn;
4678: rtx avoid_return_reg;
4679: {
4680: register int i, j;
4681: int max_group_size = 1;
4682: enum reg_class group_class = NO_REGS;
4683: int inheritance;
4684:
4685: rtx save_reload_reg_rtx[MAX_RELOADS];
4686: char save_reload_inherited[MAX_RELOADS];
4687: rtx save_reload_inheritance_insn[MAX_RELOADS];
4688: rtx save_reload_override_in[MAX_RELOADS];
4689: int save_reload_spill_index[MAX_RELOADS];
4690: HARD_REG_SET save_reload_reg_used;
4691: HARD_REG_SET save_reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4692: HARD_REG_SET save_reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4693: HARD_REG_SET save_reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4694: HARD_REG_SET save_reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4695: HARD_REG_SET save_reload_reg_used_in_op_addr;
4696: HARD_REG_SET save_reload_reg_used_in_insn;
4697: HARD_REG_SET save_reload_reg_used_in_other_addr;
4698: HARD_REG_SET save_reload_reg_used_at_all;
4699:
4700: bzero (reload_inherited, MAX_RELOADS);
4701: bzero (reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
4702: bzero (reload_override_in, MAX_RELOADS * sizeof (rtx));
4703:
4704: CLEAR_HARD_REG_SET (reload_reg_used);
4705: CLEAR_HARD_REG_SET (reload_reg_used_at_all);
4706: CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
4707: CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
4708: CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
4709:
4710: for (i = 0; i < reload_n_operands; i++)
4711: {
4712: CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
4713: CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
4714: CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
4715: CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
4716: }
4717:
4718: #ifdef SMALL_REGISTER_CLASSES
4719: /* Don't bother with avoiding the return reg
4720: if we have no mandatory reload that could use it. */
4721: if (avoid_return_reg)
4722: {
4723: int do_avoid = 0;
4724: int regno = REGNO (avoid_return_reg);
4725: int nregs
4726: = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
4727: int r;
4728:
4729: for (r = regno; r < regno + nregs; r++)
4730: if (spill_reg_order[r] >= 0)
4731: for (j = 0; j < n_reloads; j++)
4732: if (!reload_optional[j] && reload_reg_rtx[j] == 0
4733: && (reload_in[j] != 0 || reload_out[j] != 0
4734: || reload_secondary_p[j])
4735: &&
4736: TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[j]], r))
4737: do_avoid = 1;
4738: if (!do_avoid)
4739: avoid_return_reg = 0;
4740: }
4741: #endif /* SMALL_REGISTER_CLASSES */
4742:
4743: #if 0 /* Not needed, now that we can always retry without inheritance. */
4744: /* See if we have more mandatory reloads than spill regs.
4745: If so, then we cannot risk optimizations that could prevent
4746: reloads from sharing one spill register.
4747:
4748: Since we will try finding a better register than reload_reg_rtx
4749: unless it is equal to reload_in or reload_out, count such reloads. */
4750:
4751: {
4752: int tem = 0;
4753: #ifdef SMALL_REGISTER_CLASSES
4754: int tem = (avoid_return_reg != 0);
4755: #endif
4756: for (j = 0; j < n_reloads; j++)
4757: if (! reload_optional[j]
4758: && (reload_in[j] != 0 || reload_out[j] != 0 || reload_secondary_p[j])
4759: && (reload_reg_rtx[j] == 0
4760: || (! rtx_equal_p (reload_reg_rtx[j], reload_in[j])
4761: && ! rtx_equal_p (reload_reg_rtx[j], reload_out[j]))))
4762: tem++;
4763: if (tem > n_spills)
4764: must_reuse = 1;
4765: }
4766: #endif
4767:
4768: #ifdef SMALL_REGISTER_CLASSES
4769: /* Don't use the subroutine call return reg for a reload
4770: if we are supposed to avoid it. */
4771: if (avoid_return_reg)
4772: {
4773: int regno = REGNO (avoid_return_reg);
4774: int nregs
4775: = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
4776: int r;
4777:
4778: for (r = regno; r < regno + nregs; r++)
4779: if (spill_reg_order[r] >= 0)
4780: SET_HARD_REG_BIT (reload_reg_used, r);
4781: }
4782: #endif /* SMALL_REGISTER_CLASSES */
4783:
4784: /* In order to be certain of getting the registers we need,
4785: we must sort the reloads into order of increasing register class.
4786: Then our grabbing of reload registers will parallel the process
4787: that provided the reload registers.
4788:
4789: Also note whether any of the reloads wants a consecutive group of regs.
4790: If so, record the maximum size of the group desired and what
4791: register class contains all the groups needed by this insn. */
4792:
4793: for (j = 0; j < n_reloads; j++)
4794: {
4795: reload_order[j] = j;
4796: reload_spill_index[j] = -1;
4797:
4798: reload_mode[j]
4799: = (reload_inmode[j] == VOIDmode
4800: || (GET_MODE_SIZE (reload_outmode[j])
4801: > GET_MODE_SIZE (reload_inmode[j])))
4802: ? reload_outmode[j] : reload_inmode[j];
4803:
4804: reload_nregs[j] = CLASS_MAX_NREGS (reload_reg_class[j], reload_mode[j]);
4805:
4806: if (reload_nregs[j] > 1)
4807: {
4808: max_group_size = MAX (reload_nregs[j], max_group_size);
4809: group_class = reg_class_superunion[(int)reload_reg_class[j]][(int)group_class];
4810: }
4811:
4812: /* If we have already decided to use a certain register,
4813: don't use it in another way. */
4814: if (reload_reg_rtx[j])
4815: mark_reload_reg_in_use (REGNO (reload_reg_rtx[j]), reload_opnum[j],
4816: reload_when_needed[j], reload_mode[j]);
4817: }
4818:
4819: if (n_reloads > 1)
4820: qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
4821:
4822: bcopy (reload_reg_rtx, save_reload_reg_rtx, sizeof reload_reg_rtx);
4823: bcopy (reload_inherited, save_reload_inherited, sizeof reload_inherited);
4824: bcopy (reload_inheritance_insn, save_reload_inheritance_insn,
4825: sizeof reload_inheritance_insn);
4826: bcopy (reload_override_in, save_reload_override_in,
4827: sizeof reload_override_in);
4828: bcopy (reload_spill_index, save_reload_spill_index,
4829: sizeof reload_spill_index);
4830: COPY_HARD_REG_SET (save_reload_reg_used, reload_reg_used);
4831: COPY_HARD_REG_SET (save_reload_reg_used_at_all, reload_reg_used_at_all);
4832: COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr,
4833: reload_reg_used_in_op_addr);
4834: COPY_HARD_REG_SET (save_reload_reg_used_in_insn,
4835: reload_reg_used_in_insn);
4836: COPY_HARD_REG_SET (save_reload_reg_used_in_other_addr,
4837: reload_reg_used_in_other_addr);
4838:
4839: for (i = 0; i < reload_n_operands; i++)
4840: {
4841: COPY_HARD_REG_SET (save_reload_reg_used_in_output[i],
4842: reload_reg_used_in_output[i]);
4843: COPY_HARD_REG_SET (save_reload_reg_used_in_input[i],
4844: reload_reg_used_in_input[i]);
4845: COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr[i],
4846: reload_reg_used_in_input_addr[i]);
4847: COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr[i],
4848: reload_reg_used_in_output_addr[i]);
4849: }
4850:
4851: /* If -O, try first with inheritance, then turning it off.
4852: If not -O, don't do inheritance.
4853: Using inheritance when not optimizing leads to paradoxes
4854: with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
4855: because one side of the comparison might be inherited. */
4856:
4857: for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
4858: {
4859: /* Process the reloads in order of preference just found.
4860: Beyond this point, subregs can be found in reload_reg_rtx.
4861:
4862: This used to look for an existing reloaded home for all
4863: of the reloads, and only then perform any new reloads.
4864: But that could lose if the reloads were done out of reg-class order
4865: because a later reload with a looser constraint might have an old
4866: home in a register needed by an earlier reload with a tighter constraint.
4867:
4868: To solve this, we make two passes over the reloads, in the order
4869: described above. In the first pass we try to inherit a reload
4870: from a previous insn. If there is a later reload that needs a
4871: class that is a proper subset of the class being processed, we must
4872: also allocate a spill register during the first pass.
4873:
4874: Then make a second pass over the reloads to allocate any reloads
4875: that haven't been given registers yet. */
4876:
4877: CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
4878:
4879: for (j = 0; j < n_reloads; j++)
4880: {
4881: register int r = reload_order[j];
4882:
4883: /* Ignore reloads that got marked inoperative. */
4884: if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
4885: continue;
4886:
4887: /* If find_reloads chose a to use reload_in or reload_out as a reload
4888: register, we don't need to chose one. Otherwise, try even if it found
4889: one since we might save an insn if we find the value lying around. */
4890: if (reload_in[r] != 0 && reload_reg_rtx[r] != 0
4891: && (rtx_equal_p (reload_in[r], reload_reg_rtx[r])
4892: || rtx_equal_p (reload_out[r], reload_reg_rtx[r])))
4893: continue;
4894:
4895: #if 0 /* No longer needed for correct operation.
4896: It might give better code, or might not; worth an experiment? */
4897: /* If this is an optional reload, we can't inherit from earlier insns
4898: until we are sure that any non-optional reloads have been allocated.
4899: The following code takes advantage of the fact that optional reloads
4900: are at the end of reload_order. */
4901: if (reload_optional[r] != 0)
4902: for (i = 0; i < j; i++)
4903: if ((reload_out[reload_order[i]] != 0
4904: || reload_in[reload_order[i]] != 0
4905: || reload_secondary_p[reload_order[i]])
4906: && ! reload_optional[reload_order[i]]
4907: && reload_reg_rtx[reload_order[i]] == 0)
4908: allocate_reload_reg (reload_order[i], insn, 0, inheritance);
4909: #endif
4910:
4911: /* First see if this pseudo is already available as reloaded
4912: for a previous insn. We cannot try to inherit for reloads
4913: that are smaller than the maximum number of registers needed
4914: for groups unless the register we would allocate cannot be used
4915: for the groups.
4916:
4917: We could check here to see if this is a secondary reload for
4918: an object that is already in a register of the desired class.
4919: This would avoid the need for the secondary reload register.
4920: But this is complex because we can't easily determine what
4921: objects might want to be loaded via this reload. So let a register
4922: be allocated here. In `emit_reload_insns' we suppress one of the
4923: loads in the case described above. */
4924:
4925: if (inheritance)
4926: {
4927: register int regno = -1;
4928: enum machine_mode mode;
4929:
4930: if (reload_in[r] == 0)
4931: ;
4932: else if (GET_CODE (reload_in[r]) == REG)
4933: {
4934: regno = REGNO (reload_in[r]);
4935: mode = GET_MODE (reload_in[r]);
4936: }
4937: else if (GET_CODE (reload_in_reg[r]) == REG)
4938: {
4939: regno = REGNO (reload_in_reg[r]);
4940: mode = GET_MODE (reload_in_reg[r]);
4941: }
4942: #if 0
4943: /* This won't work, since REGNO can be a pseudo reg number.
4944: Also, it takes much more hair to keep track of all the things
4945: that can invalidate an inherited reload of part of a pseudoreg. */
4946: else if (GET_CODE (reload_in[r]) == SUBREG
4947: && GET_CODE (SUBREG_REG (reload_in[r])) == REG)
4948: regno = REGNO (SUBREG_REG (reload_in[r])) + SUBREG_WORD (reload_in[r]);
4949: #endif
4950:
4951: if (regno >= 0 && reg_last_reload_reg[regno] != 0)
4952: {
4953: i = spill_reg_order[REGNO (reg_last_reload_reg[regno])];
4954:
4955: if (reg_reloaded_contents[i] == regno
4956: && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno]))
4957: >= GET_MODE_SIZE (mode))
4958: && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r])
4959: && TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
4960: spill_regs[i])
4961: && (reload_nregs[r] == max_group_size
4962: || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
4963: spill_regs[i]))
4964: && reload_reg_free_p (spill_regs[i], reload_opnum[r],
4965: reload_when_needed[r])
4966: && reload_reg_free_before_p (spill_regs[i],
4967: reload_opnum[r],
4968: reload_when_needed[r]))
4969: {
4970: /* If a group is needed, verify that all the subsequent
4971: registers still have their values intact. */
4972: int nr
4973: = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
4974: int k;
4975:
4976: for (k = 1; k < nr; k++)
4977: if (reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
4978: != regno)
4979: break;
4980:
4981: if (k == nr)
4982: {
4983: int i1;
4984:
4985: /* We found a register that contains the
4986: value we need. If this register is the
4987: same as an `earlyclobber' operand of the
4988: current insn, just mark it as a place to
4989: reload from since we can't use it as the
4990: reload register itself. */
4991:
4992: for (i1 = 0; i1 < n_earlyclobbers; i1++)
4993: if (reg_overlap_mentioned_for_reload_p
4994: (reg_last_reload_reg[regno],
4995: reload_earlyclobbers[i1]))
4996: break;
4997:
4998: if (i1 != n_earlyclobbers
4999: /* Don't really use the inherited spill reg
5000: if we need it wider than we've got it. */
5001: || (GET_MODE_SIZE (reload_mode[r])
5002: > GET_MODE_SIZE (mode)))
5003: reload_override_in[r] = reg_last_reload_reg[regno];
5004: else
5005: {
5006: int k;
5007: /* We can use this as a reload reg. */
5008: /* Mark the register as in use for this part of
5009: the insn. */
5010: mark_reload_reg_in_use (spill_regs[i],
5011: reload_opnum[r],
5012: reload_when_needed[r],
5013: reload_mode[r]);
5014: reload_reg_rtx[r] = reg_last_reload_reg[regno];
5015: reload_inherited[r] = 1;
5016: reload_inheritance_insn[r]
5017: = reg_reloaded_insn[i];
5018: reload_spill_index[r] = i;
5019: for (k = 0; k < nr; k++)
5020: SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5021: spill_regs[i + k]);
5022: }
5023: }
5024: }
5025: }
5026: }
5027:
5028: /* Here's another way to see if the value is already lying around. */
5029: if (inheritance
5030: && reload_in[r] != 0
5031: && ! reload_inherited[r]
5032: && reload_out[r] == 0
5033: && (CONSTANT_P (reload_in[r])
5034: || GET_CODE (reload_in[r]) == PLUS
5035: || GET_CODE (reload_in[r]) == REG
5036: || GET_CODE (reload_in[r]) == MEM)
5037: && (reload_nregs[r] == max_group_size
5038: || ! reg_classes_intersect_p (reload_reg_class[r], group_class)))
5039: {
5040: register rtx equiv
5041: = find_equiv_reg (reload_in[r], insn, reload_reg_class[r],
5042: -1, NULL_PTR, 0, reload_mode[r]);
5043: int regno;
5044:
5045: if (equiv != 0)
5046: {
5047: if (GET_CODE (equiv) == REG)
5048: regno = REGNO (equiv);
5049: else if (GET_CODE (equiv) == SUBREG)
5050: {
5051: regno = REGNO (SUBREG_REG (equiv));
5052: if (regno < FIRST_PSEUDO_REGISTER)
5053: regno += SUBREG_WORD (equiv);
5054: }
5055: else
5056: abort ();
5057: }
5058:
5059: /* If we found a spill reg, reject it unless it is free
5060: and of the desired class. */
5061: if (equiv != 0
5062: && ((spill_reg_order[regno] >= 0
5063: && ! reload_reg_free_before_p (regno, reload_opnum[r],
5064: reload_when_needed[r]))
5065: || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
5066: regno)))
5067: equiv = 0;
5068:
5069: if (equiv != 0 && TEST_HARD_REG_BIT (reload_reg_used_at_all, regno))
5070: equiv = 0;
5071:
5072: if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, reload_mode[r]))
5073: equiv = 0;
5074:
5075: /* We found a register that contains the value we need.
5076: If this register is the same as an `earlyclobber' operand
5077: of the current insn, just mark it as a place to reload from
5078: since we can't use it as the reload register itself. */
5079:
5080: if (equiv != 0)
5081: for (i = 0; i < n_earlyclobbers; i++)
5082: if (reg_overlap_mentioned_for_reload_p (equiv,
5083: reload_earlyclobbers[i]))
5084: {
5085: reload_override_in[r] = equiv;
5086: equiv = 0;
5087: break;
5088: }
5089:
5090: /* JRV: If the equiv register we have found is explicitly
5091: clobbered in the current insn, mark but don't use, as above. */
5092:
5093: if (equiv != 0 && regno_clobbered_p (regno, insn))
5094: {
5095: reload_override_in[r] = equiv;
5096: equiv = 0;
5097: }
5098:
5099: /* If we found an equivalent reg, say no code need be generated
5100: to load it, and use it as our reload reg. */
5101: if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5102: {
5103: reload_reg_rtx[r] = equiv;
5104: reload_inherited[r] = 1;
5105: /* If it is a spill reg,
5106: mark the spill reg as in use for this insn. */
5107: i = spill_reg_order[regno];
5108: if (i >= 0)
5109: {
5110: int nr = HARD_REGNO_NREGS (regno, reload_mode[r]);
5111: int k;
5112: mark_reload_reg_in_use (regno, reload_opnum[r],
5113: reload_when_needed[r],
5114: reload_mode[r]);
5115: for (k = 0; k < nr; k++)
5116: SET_HARD_REG_BIT (reload_reg_used_for_inherit, regno + k);
5117: }
5118: }
5119: }
5120:
5121: /* If we found a register to use already, or if this is an optional
5122: reload, we are done. */
5123: if (reload_reg_rtx[r] != 0 || reload_optional[r] != 0)
5124: continue;
5125:
5126: #if 0 /* No longer needed for correct operation. Might or might not
5127: give better code on the average. Want to experiment? */
5128:
5129: /* See if there is a later reload that has a class different from our
5130: class that intersects our class or that requires less register
5131: than our reload. If so, we must allocate a register to this
5132: reload now, since that reload might inherit a previous reload
5133: and take the only available register in our class. Don't do this
5134: for optional reloads since they will force all previous reloads
5135: to be allocated. Also don't do this for reloads that have been
5136: turned off. */
5137:
5138: for (i = j + 1; i < n_reloads; i++)
5139: {
5140: int s = reload_order[i];
5141:
5142: if ((reload_in[s] == 0 && reload_out[s] == 0
5143: && ! reload_secondary_p[s])
5144: || reload_optional[s])
5145: continue;
5146:
5147: if ((reload_reg_class[s] != reload_reg_class[r]
5148: && reg_classes_intersect_p (reload_reg_class[r],
5149: reload_reg_class[s]))
5150: || reload_nregs[s] < reload_nregs[r])
5151: break;
5152: }
5153:
5154: if (i == n_reloads)
5155: continue;
5156:
5157: allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance);
5158: #endif
5159: }
5160:
5161: /* Now allocate reload registers for anything non-optional that
5162: didn't get one yet. */
5163: for (j = 0; j < n_reloads; j++)
5164: {
5165: register int r = reload_order[j];
5166:
5167: /* Ignore reloads that got marked inoperative. */
5168: if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
5169: continue;
5170:
5171: /* Skip reloads that already have a register allocated or are
5172: optional. */
5173: if (reload_reg_rtx[r] != 0 || reload_optional[r])
5174: continue;
5175:
5176: if (! allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance))
5177: break;
5178: }
5179:
5180: /* If that loop got all the way, we have won. */
5181: if (j == n_reloads)
5182: break;
5183:
5184: fail:
5185: /* Loop around and try without any inheritance. */
5186: /* First undo everything done by the failed attempt
5187: to allocate with inheritance. */
5188: bcopy (save_reload_reg_rtx, reload_reg_rtx, sizeof reload_reg_rtx);
5189: bcopy (save_reload_inherited, reload_inherited, sizeof reload_inherited);
5190: bcopy (save_reload_inheritance_insn, reload_inheritance_insn,
5191: sizeof reload_inheritance_insn);
5192: bcopy (save_reload_override_in, reload_override_in,
5193: sizeof reload_override_in);
5194: bcopy (save_reload_spill_index, reload_spill_index,
5195: sizeof reload_spill_index);
5196: COPY_HARD_REG_SET (reload_reg_used, save_reload_reg_used);
5197: COPY_HARD_REG_SET (reload_reg_used_at_all, save_reload_reg_used_at_all);
5198: COPY_HARD_REG_SET (reload_reg_used_in_op_addr,
5199: save_reload_reg_used_in_op_addr);
5200: COPY_HARD_REG_SET (reload_reg_used_in_insn,
5201: save_reload_reg_used_in_insn);
5202: COPY_HARD_REG_SET (reload_reg_used_in_other_addr,
5203: save_reload_reg_used_in_other_addr);
5204:
5205: for (i = 0; i < reload_n_operands; i++)
5206: {
5207: COPY_HARD_REG_SET (reload_reg_used_in_input[i],
5208: save_reload_reg_used_in_input[i]);
5209: COPY_HARD_REG_SET (reload_reg_used_in_output[i],
5210: save_reload_reg_used_in_output[i]);
5211: COPY_HARD_REG_SET (reload_reg_used_in_input_addr[i],
5212: save_reload_reg_used_in_input_addr[i]);
5213: COPY_HARD_REG_SET (reload_reg_used_in_output_addr[i],
5214: save_reload_reg_used_in_output_addr[i]);
5215: }
5216: }
5217:
5218: /* If we thought we could inherit a reload, because it seemed that
5219: nothing else wanted the same reload register earlier in the insn,
5220: verify that assumption, now that all reloads have been assigned. */
5221:
5222: for (j = 0; j < n_reloads; j++)
5223: {
5224: register int r = reload_order[j];
5225:
5226: if (reload_inherited[r] && reload_reg_rtx[r] != 0
5227: && ! reload_reg_free_before_p (true_regnum (reload_reg_rtx[r]),
5228: reload_opnum[r],
5229: reload_when_needed[r]))
5230: reload_inherited[r] = 0;
5231:
5232: /* If we found a better place to reload from,
5233: validate it in the same fashion, if it is a reload reg. */
5234: if (reload_override_in[r]
5235: && (GET_CODE (reload_override_in[r]) == REG
5236: || GET_CODE (reload_override_in[r]) == SUBREG))
5237: {
5238: int regno = true_regnum (reload_override_in[r]);
5239: if (spill_reg_order[regno] >= 0
5240: && ! reload_reg_free_before_p (regno, reload_opnum[r],
5241: reload_when_needed[r]))
5242: reload_override_in[r] = 0;
5243: }
5244: }
5245:
5246: /* Now that reload_override_in is known valid,
5247: actually override reload_in. */
5248: for (j = 0; j < n_reloads; j++)
5249: if (reload_override_in[j])
5250: reload_in[j] = reload_override_in[j];
5251:
5252: /* If this reload won't be done because it has been cancelled or is
5253: optional and not inherited, clear reload_reg_rtx so other
5254: routines (such as subst_reloads) don't get confused. */
5255: for (j = 0; j < n_reloads; j++)
5256: if (reload_reg_rtx[j] != 0
5257: && ((reload_optional[j] && ! reload_inherited[j])
5258: || (reload_in[j] == 0 && reload_out[j] == 0
5259: && ! reload_secondary_p[j])))
5260: {
5261: int regno = true_regnum (reload_reg_rtx[j]);
5262:
5263: if (spill_reg_order[regno] >= 0)
5264: clear_reload_reg_in_use (regno, reload_opnum[j],
5265: reload_when_needed[j], reload_mode[j]);
5266: reload_reg_rtx[j] = 0;
5267: }
5268:
5269: /* Record which pseudos and which spill regs have output reloads. */
5270: for (j = 0; j < n_reloads; j++)
5271: {
5272: register int r = reload_order[j];
5273:
5274: i = reload_spill_index[r];
5275:
5276: /* I is nonneg if this reload used one of the spill regs.
5277: If reload_reg_rtx[r] is 0, this is an optional reload
5278: that we opted to ignore. */
5279: if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG
5280: && reload_reg_rtx[r] != 0)
5281: {
5282: register int nregno = REGNO (reload_out[r]);
5283: int nr = 1;
5284:
5285: if (nregno < FIRST_PSEUDO_REGISTER)
5286: nr = HARD_REGNO_NREGS (nregno, reload_mode[r]);
5287:
5288: while (--nr >= 0)
5289: reg_has_output_reload[nregno + nr] = 1;
5290:
5291: if (i >= 0)
5292: {
5293: nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
5294: while (--nr >= 0)
5295: SET_HARD_REG_BIT (reg_is_output_reload, spill_regs[i] + nr);
5296: }
5297:
5298: if (reload_when_needed[r] != RELOAD_OTHER
5299: && reload_when_needed[r] != RELOAD_FOR_OUTPUT
5300: && reload_when_needed[r] != RELOAD_FOR_INSN)
5301: abort ();
5302: }
5303: }
5304: }
5305:
5306: /* If SMALL_REGISTER_CLASSES are defined, we may not have merged two
5307: reloads of the same item for fear that we might not have enough reload
5308: registers. However, normally they will get the same reload register
5309: and hence actually need not be loaded twice.
5310:
5311: Here we check for the most common case of this phenomenon: when we have
5312: a number of reloads for the same object, each of which were allocated
5313: the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5314: reload, and is not modified in the insn itself. If we find such,
5315: merge all the reloads and set the resulting reload to RELOAD_OTHER.
5316: This will not increase the number of spill registers needed and will
5317: prevent redundant code. */
5318:
5319: #ifdef SMALL_REGISTER_CLASSES
5320:
5321: static void
5322: merge_assigned_reloads (insn)
5323: rtx insn;
5324: {
5325: int i, j;
5326:
5327: /* Scan all the reloads looking for ones that only load values and
5328: are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5329: assigned and not modified by INSN. */
5330:
5331: for (i = 0; i < n_reloads; i++)
5332: {
5333: if (reload_in[i] == 0 || reload_when_needed[i] == RELOAD_OTHER
5334: || reload_out[i] != 0 || reload_reg_rtx[i] == 0
5335: || reg_set_p (reload_reg_rtx[i], insn))
5336: continue;
5337:
5338: /* Look at all other reloads. Ensure that the only use of this
5339: reload_reg_rtx is in a reload that just loads the same value
5340: as we do. Note that any secondary reloads must be of the identical
5341: class since the values, modes, and result registers are the
5342: same, so we need not do anything with any secondary reloads. */
5343:
5344: for (j = 0; j < n_reloads; j++)
5345: {
5346: if (i == j || reload_reg_rtx[j] == 0
5347: || ! reg_overlap_mentioned_p (reload_reg_rtx[j],
5348: reload_reg_rtx[i]))
5349: continue;
5350:
5351: /* If the reload regs aren't exactly the same (e.g, different modes)
5352: or if the values are different, we can't merge anything with this
5353: reload register. */
5354:
5355: if (! rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
5356: || reload_out[j] != 0 || reload_in[j] == 0
5357: || ! rtx_equal_p (reload_in[i], reload_in[j]))
5358: break;
5359: }
5360:
5361: /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
5362: we, in fact, found any matching reloads. */
5363:
5364: if (j == n_reloads)
5365: {
5366: for (j = 0; j < n_reloads; j++)
5367: if (i != j && reload_reg_rtx[j] != 0
5368: && rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j]))
5369: {
5370: reload_when_needed[i] = RELOAD_OTHER;
5371: reload_in[j] = 0;
5372: transfer_replacements (i, j);
5373: }
5374:
5375: /* If this is now RELOAD_OTHER, look for any reloads that load
5376: parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
5377: if they were for inputs, RELOAD_OTHER for outputs. Note that
5378: this test is equivalent to looking for reloads for this operand
5379: number. */
5380:
5381: if (reload_when_needed[i] == RELOAD_OTHER)
5382: for (j = 0; j < n_reloads; j++)
5383: if (reload_in[j] != 0
5384: && reload_when_needed[i] != RELOAD_OTHER
5385: && reg_overlap_mentioned_for_reload_p (reload_in[j],
5386: reload_in[i]))
5387: reload_when_needed[j]
5388: = reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS
5389: ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER;
5390: }
5391: }
5392: }
5393: #endif /* SMALL_RELOAD_CLASSES */
5394:
5395: /* Output insns to reload values in and out of the chosen reload regs. */
5396:
5397: static void
5398: emit_reload_insns (insn)
5399: rtx insn;
5400: {
5401: register int j;
5402: rtx input_reload_insns[MAX_RECOG_OPERANDS];
5403: rtx other_input_address_reload_insns = 0;
5404: rtx other_input_reload_insns = 0;
5405: rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
5406: rtx output_reload_insns[MAX_RECOG_OPERANDS];
5407: rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
5408: rtx operand_reload_insns = 0;
5409: rtx following_insn = NEXT_INSN (insn);
5410: rtx before_insn = insn;
5411: int special;
5412: /* Values to be put in spill_reg_store are put here first. */
5413: rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
5414:
5415: for (j = 0; j < reload_n_operands; j++)
5416: input_reload_insns[j] = input_address_reload_insns[j]
5417: = output_reload_insns[j] = output_address_reload_insns[j] = 0;
5418:
5419: /* If this is a CALL_INSN preceded by USE insns, any reload insns
5420: must go in front of the first USE insn, not in front of INSN. */
5421:
5422: if (GET_CODE (insn) == CALL_INSN && GET_CODE (PREV_INSN (insn)) == INSN
5423: && GET_CODE (PATTERN (PREV_INSN (insn))) == USE)
5424: while (GET_CODE (PREV_INSN (before_insn)) == INSN
5425: && GET_CODE (PATTERN (PREV_INSN (before_insn))) == USE)
5426: before_insn = PREV_INSN (before_insn);
5427:
5428: /* If INSN is followed by any CLOBBER insns made by find_reloads,
5429: put our reloads after them since they may otherwise be
5430: misinterpreted. */
5431:
5432: while (GET_CODE (following_insn) == INSN
5433: && GET_MODE (following_insn) == DImode
5434: && GET_CODE (PATTERN (following_insn)) == CLOBBER
5435: && NEXT_INSN (following_insn) != 0)
5436: following_insn = NEXT_INSN (following_insn);
5437:
5438: /* Now output the instructions to copy the data into and out of the
5439: reload registers. Do these in the order that the reloads were reported,
5440: since reloads of base and index registers precede reloads of operands
5441: and the operands may need the base and index registers reloaded. */
5442:
5443: for (j = 0; j < n_reloads; j++)
5444: {
5445: register rtx old;
5446: rtx oldequiv_reg = 0;
5447: rtx store_insn = 0;
5448:
5449: old = reload_in[j];
5450: if (old != 0 && ! reload_inherited[j]
5451: && ! rtx_equal_p (reload_reg_rtx[j], old)
5452: && reload_reg_rtx[j] != 0)
5453: {
5454: register rtx reloadreg = reload_reg_rtx[j];
5455: rtx oldequiv = 0;
5456: enum machine_mode mode;
5457: rtx *where;
5458:
5459: /* Determine the mode to reload in.
5460: This is very tricky because we have three to choose from.
5461: There is the mode the insn operand wants (reload_inmode[J]).
5462: There is the mode of the reload register RELOADREG.
5463: There is the intrinsic mode of the operand, which we could find
5464: by stripping some SUBREGs.
5465: It turns out that RELOADREG's mode is irrelevant:
5466: we can change that arbitrarily.
5467:
5468: Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
5469: then the reload reg may not support QImode moves, so use SImode.
5470: If foo is in memory due to spilling a pseudo reg, this is safe,
5471: because the QImode value is in the least significant part of a
5472: slot big enough for a SImode. If foo is some other sort of
5473: memory reference, then it is impossible to reload this case,
5474: so previous passes had better make sure this never happens.
5475:
5476: Then consider a one-word union which has SImode and one of its
5477: members is a float, being fetched as (SUBREG:SF union:SI).
5478: We must fetch that as SFmode because we could be loading into
5479: a float-only register. In this case OLD's mode is correct.
5480:
5481: Consider an immediate integer: it has VOIDmode. Here we need
5482: to get a mode from something else.
5483:
5484: In some cases, there is a fourth mode, the operand's
5485: containing mode. If the insn specifies a containing mode for
5486: this operand, it overrides all others.
5487:
5488: I am not sure whether the algorithm here is always right,
5489: but it does the right things in those cases. */
5490:
5491: mode = GET_MODE (old);
5492: if (mode == VOIDmode)
5493: mode = reload_inmode[j];
5494:
5495: #ifdef SECONDARY_INPUT_RELOAD_CLASS
5496: /* If we need a secondary register for this operation, see if
5497: the value is already in a register in that class. Don't
5498: do this if the secondary register will be used as a scratch
5499: register. */
5500:
5501: if (reload_secondary_reload[j] >= 0
5502: && reload_secondary_icode[j] == CODE_FOR_nothing
5503: && optimize)
5504: oldequiv
5505: = find_equiv_reg (old, insn,
5506: reload_reg_class[reload_secondary_reload[j]],
5507: -1, NULL_PTR, 0, mode);
5508: #endif
5509:
5510: /* If reloading from memory, see if there is a register
5511: that already holds the same value. If so, reload from there.
5512: We can pass 0 as the reload_reg_p argument because
5513: any other reload has either already been emitted,
5514: in which case find_equiv_reg will see the reload-insn,
5515: or has yet to be emitted, in which case it doesn't matter
5516: because we will use this equiv reg right away. */
5517:
5518: if (oldequiv == 0 && optimize
5519: && (GET_CODE (old) == MEM
5520: || (GET_CODE (old) == REG
5521: && REGNO (old) >= FIRST_PSEUDO_REGISTER
5522: && reg_renumber[REGNO (old)] < 0)))
5523: oldequiv = find_equiv_reg (old, insn, ALL_REGS,
5524: -1, NULL_PTR, 0, mode);
5525:
5526: if (oldequiv)
5527: {
5528: int regno = true_regnum (oldequiv);
5529:
5530: /* If OLDEQUIV is a spill register, don't use it for this
5531: if any other reload needs it at an earlier stage of this insn
5532: or at this stage. */
5533: if (spill_reg_order[regno] >= 0
5534: && (! reload_reg_free_p (regno, reload_opnum[j],
5535: reload_when_needed[j])
5536: || ! reload_reg_free_before_p (regno, reload_opnum[j],
5537: reload_when_needed[j])))
5538: oldequiv = 0;
5539:
5540: /* If OLDEQUIV is not a spill register,
5541: don't use it if any other reload wants it. */
5542: if (spill_reg_order[regno] < 0)
5543: {
5544: int k;
5545: for (k = 0; k < n_reloads; k++)
5546: if (reload_reg_rtx[k] != 0 && k != j
5547: && reg_overlap_mentioned_for_reload_p (reload_reg_rtx[k],
5548: oldequiv))
5549: {
5550: oldequiv = 0;
5551: break;
5552: }
5553: }
5554:
5555: /* If it is no cheaper to copy from OLDEQUIV into the
5556: reload register than it would be to move from memory,
5557: don't use it. Likewise, if we need a secondary register
5558: or memory. */
5559:
5560: if (oldequiv != 0
5561: && ((REGNO_REG_CLASS (regno) != reload_reg_class[j]
5562: && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
5563: reload_reg_class[j])
5564: >= MEMORY_MOVE_COST (mode)))
5565: #ifdef SECONDARY_INPUT_RELOAD_CLASS
5566: || (SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
5567: mode, oldequiv)
5568: != NO_REGS)
5569: #endif
5570: #ifdef SECONDARY_MEMORY_NEEDED
5571: || SECONDARY_MEMORY_NEEDED (reload_reg_class[j],
5572: REGNO_REG_CLASS (regno),
5573: mode)
5574: #endif
5575: ))
5576: oldequiv = 0;
5577: }
5578:
5579: if (oldequiv == 0)
5580: oldequiv = old;
5581: else if (GET_CODE (oldequiv) == REG)
5582: oldequiv_reg = oldequiv;
5583: else if (GET_CODE (oldequiv) == SUBREG)
5584: oldequiv_reg = SUBREG_REG (oldequiv);
5585:
5586: /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
5587: then load RELOADREG from OLDEQUIV. Note that we cannot use
5588: gen_lowpart_common since it can do the wrong thing when
5589: RELOADREG has a multi-word mode. Note that RELOADREG
5590: must always be a REG here. */
5591:
5592: if (GET_MODE (reloadreg) != mode)
5593: reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
5594: while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
5595: oldequiv = SUBREG_REG (oldequiv);
5596: if (GET_MODE (oldequiv) != VOIDmode
5597: && mode != GET_MODE (oldequiv))
5598: oldequiv = gen_rtx (SUBREG, mode, oldequiv, 0);
5599:
5600: /* Switch to the right place to emit the reload insns. */
5601: switch (reload_when_needed[j])
5602: {
5603: case RELOAD_OTHER:
5604: where = &other_input_reload_insns;
5605: break;
5606: case RELOAD_FOR_INPUT:
5607: where = &input_reload_insns[reload_opnum[j]];
5608: break;
5609: case RELOAD_FOR_INPUT_ADDRESS:
5610: where = &input_address_reload_insns[reload_opnum[j]];
5611: break;
5612: case RELOAD_FOR_OUTPUT_ADDRESS:
5613: where = &output_address_reload_insns[reload_opnum[j]];
5614: break;
5615: case RELOAD_FOR_OPERAND_ADDRESS:
5616: where = &operand_reload_insns;
5617: break;
5618: case RELOAD_FOR_OTHER_ADDRESS:
5619: where = &other_input_address_reload_insns;
5620: break;
5621: default:
5622: abort ();
5623: }
5624:
5625: push_to_sequence (*where);
5626: special = 0;
5627:
5628: /* Auto-increment addresses must be reloaded in a special way. */
5629: if (GET_CODE (oldequiv) == POST_INC
5630: || GET_CODE (oldequiv) == POST_DEC
5631: || GET_CODE (oldequiv) == PRE_INC
5632: || GET_CODE (oldequiv) == PRE_DEC)
5633: {
5634: /* We are not going to bother supporting the case where a
5635: incremented register can't be copied directly from
5636: OLDEQUIV since this seems highly unlikely. */
5637: if (reload_secondary_reload[j] >= 0)
5638: abort ();
5639: /* Prevent normal processing of this reload. */
5640: special = 1;
5641: /* Output a special code sequence for this case. */
5642: inc_for_reload (reloadreg, oldequiv, reload_inc[j]);
5643: }
5644:
5645: /* If we are reloading a pseudo-register that was set by the previous
5646: insn, see if we can get rid of that pseudo-register entirely
5647: by redirecting the previous insn into our reload register. */
5648:
5649: else if (optimize && GET_CODE (old) == REG
5650: && REGNO (old) >= FIRST_PSEUDO_REGISTER
5651: && dead_or_set_p (insn, old)
5652: /* This is unsafe if some other reload
5653: uses the same reg first. */
5654: && reload_reg_free_before_p (REGNO (reloadreg),
5655: reload_opnum[j],
5656: reload_when_needed[j]))
5657: {
5658: rtx temp = PREV_INSN (insn);
5659: while (temp && GET_CODE (temp) == NOTE)
5660: temp = PREV_INSN (temp);
5661: if (temp
5662: && GET_CODE (temp) == INSN
5663: && GET_CODE (PATTERN (temp)) == SET
5664: && SET_DEST (PATTERN (temp)) == old
5665: /* Make sure we can access insn_operand_constraint. */
5666: && asm_noperands (PATTERN (temp)) < 0
5667: /* This is unsafe if prev insn rejects our reload reg. */
5668: && constraint_accepts_reg_p (insn_operand_constraint[recog_memoized (temp)][0],
5669: reloadreg)
5670: /* This is unsafe if operand occurs more than once in current
5671: insn. Perhaps some occurrences aren't reloaded. */
5672: && count_occurrences (PATTERN (insn), old) == 1
5673: /* Don't risk splitting a matching pair of operands. */
5674: && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
5675: {
5676: /* Store into the reload register instead of the pseudo. */
5677: SET_DEST (PATTERN (temp)) = reloadreg;
5678: /* If these are the only uses of the pseudo reg,
5679: pretend for GDB it lives in the reload reg we used. */
5680: if (reg_n_deaths[REGNO (old)] == 1
5681: && reg_n_sets[REGNO (old)] == 1)
5682: {
5683: reg_renumber[REGNO (old)] = REGNO (reload_reg_rtx[j]);
5684: alter_reg (REGNO (old), -1);
5685: }
5686: special = 1;
5687: }
5688: }
5689:
5690: /* We can't do that, so output an insn to load RELOADREG. */
5691:
5692: if (! special)
5693: {
5694: #ifdef SECONDARY_INPUT_RELOAD_CLASS
5695: rtx second_reload_reg = 0;
5696: enum insn_code icode;
5697:
5698: /* If we have a secondary reload, pick up the secondary register
5699: and icode, if any. If OLDEQUIV and OLD are different or
5700: if this is an in-out reload, recompute whether or not we
5701: still need a secondary register and what the icode should
5702: be. If we still need a secondary register and the class or
5703: icode is different, go back to reloading from OLD if using
5704: OLDEQUIV means that we got the wrong type of register. We
5705: cannot have different class or icode due to an in-out reload
5706: because we don't make such reloads when both the input and
5707: output need secondary reload registers. */
5708:
5709: if (reload_secondary_reload[j] >= 0)
5710: {
5711: int secondary_reload = reload_secondary_reload[j];
5712: rtx real_oldequiv = oldequiv;
5713: rtx real_old = old;
5714:
5715: /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
5716: and similarly for OLD.
5717: See comments in find_secondary_reload in reload.c. */
5718: if (GET_CODE (oldequiv) == REG
5719: && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
5720: && reg_equiv_mem[REGNO (oldequiv)] != 0)
5721: real_oldequiv = reg_equiv_mem[REGNO (oldequiv)];
5722:
5723: if (GET_CODE (old) == REG
5724: && REGNO (old) >= FIRST_PSEUDO_REGISTER
5725: && reg_equiv_mem[REGNO (old)] != 0)
5726: real_old = reg_equiv_mem[REGNO (old)];
5727:
5728: second_reload_reg = reload_reg_rtx[secondary_reload];
5729: icode = reload_secondary_icode[j];
5730:
5731: if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
5732: || (reload_in[j] != 0 && reload_out[j] != 0))
5733: {
5734: enum reg_class new_class
5735: = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
5736: mode, real_oldequiv);
5737:
5738: if (new_class == NO_REGS)
5739: second_reload_reg = 0;
5740: else
5741: {
5742: enum insn_code new_icode;
5743: enum machine_mode new_mode;
5744:
5745: if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
5746: REGNO (second_reload_reg)))
5747: oldequiv = old, real_oldequiv = real_old;
5748: else
5749: {
5750: new_icode = reload_in_optab[(int) mode];
5751: if (new_icode != CODE_FOR_nothing
5752: && ((insn_operand_predicate[(int) new_icode][0]
5753: && ! ((*insn_operand_predicate[(int) new_icode][0])
5754: (reloadreg, mode)))
5755: || (insn_operand_predicate[(int) new_icode][1]
5756: && ! ((*insn_operand_predicate[(int) new_icode][1])
5757: (real_oldequiv, mode)))))
5758: new_icode = CODE_FOR_nothing;
5759:
5760: if (new_icode == CODE_FOR_nothing)
5761: new_mode = mode;
5762: else
5763: new_mode = insn_operand_mode[(int) new_icode][2];
5764:
5765: if (GET_MODE (second_reload_reg) != new_mode)
5766: {
5767: if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
5768: new_mode))
5769: oldequiv = old, real_oldequiv = real_old;
5770: else
5771: second_reload_reg
5772: = gen_rtx (REG, new_mode,
5773: REGNO (second_reload_reg));
5774: }
5775: }
5776: }
5777: }
5778:
5779: /* If we still need a secondary reload register, check
5780: to see if it is being used as a scratch or intermediate
5781: register and generate code appropriately. If we need
5782: a scratch register, use REAL_OLDEQUIV since the form of
5783: the insn may depend on the actual address if it is
5784: a MEM. */
5785:
5786: if (second_reload_reg)
5787: {
5788: if (icode != CODE_FOR_nothing)
5789: {
5790: emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
5791: second_reload_reg));
5792: special = 1;
5793: }
5794: else
5795: {
5796: /* See if we need a scratch register to load the
5797: intermediate register (a tertiary reload). */
5798: enum insn_code tertiary_icode
5799: = reload_secondary_icode[secondary_reload];
5800:
5801: if (tertiary_icode != CODE_FOR_nothing)
5802: {
5803: rtx third_reload_reg
5804: = reload_reg_rtx[reload_secondary_reload[secondary_reload]];
5805:
5806: emit_insn ((GEN_FCN (tertiary_icode)
5807: (second_reload_reg, real_oldequiv,
5808: third_reload_reg)));
5809: }
5810: else
5811: gen_input_reload (second_reload_reg, oldequiv,
5812: reload_opnum[j],
5813: reload_when_needed[j]);
5814:
5815: oldequiv = second_reload_reg;
5816: }
5817: }
5818: }
5819: #endif
5820:
5821: if (! special)
5822: gen_input_reload (reloadreg, oldequiv, reload_opnum[j],
5823: reload_when_needed[j]);
5824:
5825: #if defined(SECONDARY_INPUT_RELOAD_CLASS) && defined(PRESERVE_DEATH_INFO_REGNO_P)
5826: /* We may have to make a REG_DEAD note for the secondary reload
5827: register in the insns we just made. Find the last insn that
5828: mentioned the register. */
5829: if (! special && second_reload_reg
5830: && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reload_reg)))
5831: {
5832: rtx prev;
5833:
5834: for (prev = get_last_insn (); prev;
5835: prev = PREV_INSN (prev))
5836: if (GET_RTX_CLASS (GET_CODE (prev) == 'i')
5837: && reg_overlap_mentioned_for_reload_p (second_reload_reg,
5838: PATTERN (prev)))
5839: {
5840: REG_NOTES (prev) = gen_rtx (EXPR_LIST, REG_DEAD,
5841: second_reload_reg,
5842: REG_NOTES (prev));
5843: break;
5844: }
5845: }
5846: #endif
5847: }
5848:
5849: /* End this sequence. */
5850: *where = get_insns ();
5851: end_sequence ();
5852: }
5853:
5854: /* Add a note saying the input reload reg
5855: dies in this insn, if anyone cares. */
5856: #ifdef PRESERVE_DEATH_INFO_REGNO_P
5857: if (old != 0
5858: && reload_reg_rtx[j] != old
5859: && reload_reg_rtx[j] != 0
5860: && reload_out[j] == 0
5861: && ! reload_inherited[j]
5862: && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j])))
5863: {
5864: register rtx reloadreg = reload_reg_rtx[j];
5865:
5866: #if 0
5867: /* We can't abort here because we need to support this for sched.c.
5868: It's not terrible to miss a REG_DEAD note, but we should try
5869: to figure out how to do this correctly. */
5870: /* The code below is incorrect for address-only reloads. */
5871: if (reload_when_needed[j] != RELOAD_OTHER
5872: && reload_when_needed[j] != RELOAD_FOR_INPUT)
5873: abort ();
5874: #endif
5875:
5876: /* Add a death note to this insn, for an input reload. */
5877:
5878: if ((reload_when_needed[j] == RELOAD_OTHER
5879: || reload_when_needed[j] == RELOAD_FOR_INPUT)
5880: && ! dead_or_set_p (insn, reloadreg))
5881: REG_NOTES (insn)
5882: = gen_rtx (EXPR_LIST, REG_DEAD,
5883: reloadreg, REG_NOTES (insn));
5884: }
5885:
5886: /* When we inherit a reload, the last marked death of the reload reg
5887: may no longer really be a death. */
5888: if (reload_reg_rtx[j] != 0
5889: && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j]))
5890: && reload_inherited[j])
5891: {
5892: /* Handle inheriting an output reload.
5893: Remove the death note from the output reload insn. */
5894: if (reload_spill_index[j] >= 0
5895: && GET_CODE (reload_in[j]) == REG
5896: && spill_reg_store[reload_spill_index[j]] != 0
5897: && find_regno_note (spill_reg_store[reload_spill_index[j]],
5898: REG_DEAD, REGNO (reload_reg_rtx[j])))
5899: remove_death (REGNO (reload_reg_rtx[j]),
5900: spill_reg_store[reload_spill_index[j]]);
5901: /* Likewise for input reloads that were inherited. */
5902: else if (reload_spill_index[j] >= 0
5903: && GET_CODE (reload_in[j]) == REG
5904: && spill_reg_store[reload_spill_index[j]] == 0
5905: && reload_inheritance_insn[j] != 0
5906: && find_regno_note (reload_inheritance_insn[j], REG_DEAD,
5907: REGNO (reload_reg_rtx[j])))
5908: remove_death (REGNO (reload_reg_rtx[j]),
5909: reload_inheritance_insn[j]);
5910: else
5911: {
5912: rtx prev;
5913:
5914: /* We got this register from find_equiv_reg.
5915: Search back for its last death note and get rid of it.
5916: But don't search back too far.
5917: Don't go past a place where this reg is set,
5918: since a death note before that remains valid. */
5919: for (prev = PREV_INSN (insn);
5920: prev && GET_CODE (prev) != CODE_LABEL;
5921: prev = PREV_INSN (prev))
5922: if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
5923: && dead_or_set_p (prev, reload_reg_rtx[j]))
5924: {
5925: if (find_regno_note (prev, REG_DEAD,
5926: REGNO (reload_reg_rtx[j])))
5927: remove_death (REGNO (reload_reg_rtx[j]), prev);
5928: break;
5929: }
5930: }
5931: }
5932:
5933: /* We might have used find_equiv_reg above to choose an alternate
5934: place from which to reload. If so, and it died, we need to remove
5935: that death and move it to one of the insns we just made. */
5936:
5937: if (oldequiv_reg != 0
5938: && PRESERVE_DEATH_INFO_REGNO_P (true_regnum (oldequiv_reg)))
5939: {
5940: rtx prev, prev1;
5941:
5942: for (prev = PREV_INSN (insn); prev && GET_CODE (prev) != CODE_LABEL;
5943: prev = PREV_INSN (prev))
5944: if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
5945: && dead_or_set_p (prev, oldequiv_reg))
5946: {
5947: if (find_regno_note (prev, REG_DEAD, REGNO (oldequiv_reg)))
5948: {
5949: for (prev1 = this_reload_insn;
5950: prev1; prev1 = PREV_INSN (prev1))
5951: if (GET_RTX_CLASS (GET_CODE (prev1) == 'i')
5952: && reg_overlap_mentioned_for_reload_p (oldequiv_reg,
5953: PATTERN (prev1)))
5954: {
5955: REG_NOTES (prev1) = gen_rtx (EXPR_LIST, REG_DEAD,
5956: oldequiv_reg,
5957: REG_NOTES (prev1));
5958: break;
5959: }
5960: remove_death (REGNO (oldequiv_reg), prev);
5961: }
5962: break;
5963: }
5964: }
5965: #endif
5966:
5967: /* If we are reloading a register that was recently stored in with an
5968: output-reload, see if we can prove there was
5969: actually no need to store the old value in it. */
5970:
5971: if (optimize && reload_inherited[j] && reload_spill_index[j] >= 0
5972: && reload_in[j] != 0
5973: && GET_CODE (reload_in[j]) == REG
5974: #if 0
5975: /* There doesn't seem to be any reason to restrict this to pseudos
5976: and doing so loses in the case where we are copying from a
5977: register of the wrong class. */
5978: && REGNO (reload_in[j]) >= FIRST_PSEUDO_REGISTER
5979: #endif
5980: && spill_reg_store[reload_spill_index[j]] != 0
5981: /* This is unsafe if some other reload uses the same reg first. */
5982: && reload_reg_free_before_p (spill_regs[reload_spill_index[j]],
5983: reload_opnum[j], reload_when_needed[j])
5984: && dead_or_set_p (insn, reload_in[j])
5985: /* This is unsafe if operand occurs more than once in current
5986: insn. Perhaps some occurrences weren't reloaded. */
5987: && count_occurrences (PATTERN (insn), reload_in[j]) == 1)
5988: delete_output_reload (insn, j,
5989: spill_reg_store[reload_spill_index[j]]);
5990:
5991: /* Input-reloading is done. Now do output-reloading,
5992: storing the value from the reload-register after the main insn
5993: if reload_out[j] is nonzero.
5994:
5995: ??? At some point we need to support handling output reloads of
5996: JUMP_INSNs or insns that set cc0. */
5997: old = reload_out[j];
5998: if (old != 0
5999: && reload_reg_rtx[j] != old
6000: && reload_reg_rtx[j] != 0)
6001: {
6002: register rtx reloadreg = reload_reg_rtx[j];
6003: register rtx second_reloadreg = 0;
6004: rtx note, p;
6005: enum machine_mode mode;
6006: int special = 0;
6007:
6008: /* An output operand that dies right away does need a reload,
6009: but need not be copied from it. Show the new location in the
6010: REG_UNUSED note. */
6011: if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6012: && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6013: {
6014: XEXP (note, 0) = reload_reg_rtx[j];
6015: continue;
6016: }
6017: else if (GET_CODE (old) == SCRATCH)
6018: /* If we aren't optimizing, there won't be a REG_UNUSED note,
6019: but we don't want to make an output reload. */
6020: continue;
6021:
6022: #if 0
6023: /* Strip off of OLD any size-increasing SUBREGs such as
6024: (SUBREG:SI foo:QI 0). */
6025:
6026: while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0
6027: && (GET_MODE_SIZE (GET_MODE (old))
6028: > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old)))))
6029: old = SUBREG_REG (old);
6030: #endif
6031:
6032: /* If is a JUMP_INSN, we can't support output reloads yet. */
6033: if (GET_CODE (insn) == JUMP_INSN)
6034: abort ();
6035:
6036: push_to_sequence (output_reload_insns[reload_opnum[j]]);
6037:
6038: /* Determine the mode to reload in.
6039: See comments above (for input reloading). */
6040:
6041: mode = GET_MODE (old);
6042: if (mode == VOIDmode)
6043: {
6044: /* VOIDmode should never happen for an output. */
6045: if (asm_noperands (PATTERN (insn)) < 0)
6046: /* It's the compiler's fault. */
6047: abort ();
6048: error_for_asm (insn, "output operand is constant in `asm'");
6049: /* Prevent crash--use something we know is valid. */
6050: mode = word_mode;
6051: old = gen_rtx (REG, mode, REGNO (reloadreg));
6052: }
6053:
6054: if (GET_MODE (reloadreg) != mode)
6055: reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
6056:
6057: #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6058:
6059: /* If we need two reload regs, set RELOADREG to the intermediate
6060: one, since it will be stored into OUT. We might need a secondary
6061: register only for an input reload, so check again here. */
6062:
6063: if (reload_secondary_reload[j] >= 0)
6064: {
6065: rtx real_old = old;
6066:
6067: if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6068: && reg_equiv_mem[REGNO (old)] != 0)
6069: real_old = reg_equiv_mem[REGNO (old)];
6070:
6071: if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class[j],
6072: mode, real_old)
6073: != NO_REGS))
6074: {
6075: second_reloadreg = reloadreg;
6076: reloadreg = reload_reg_rtx[reload_secondary_reload[j]];
6077:
6078: /* See if RELOADREG is to be used as a scratch register
6079: or as an intermediate register. */
6080: if (reload_secondary_icode[j] != CODE_FOR_nothing)
6081: {
6082: emit_insn ((GEN_FCN (reload_secondary_icode[j])
6083: (real_old, second_reloadreg, reloadreg)));
6084: special = 1;
6085: }
6086: else
6087: {
6088: /* See if we need both a scratch and intermediate reload
6089: register. */
6090: int secondary_reload = reload_secondary_reload[j];
6091: enum insn_code tertiary_icode
6092: = reload_secondary_icode[secondary_reload];
6093: rtx pat;
6094:
6095: if (GET_MODE (reloadreg) != mode)
6096: reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
6097:
6098: if (tertiary_icode != CODE_FOR_nothing)
6099: {
6100: rtx third_reloadreg
6101: = reload_reg_rtx[reload_secondary_reload[secondary_reload]];
6102: pat = (GEN_FCN (tertiary_icode)
6103: (reloadreg, second_reloadreg, third_reloadreg));
6104: }
6105: #ifdef SECONDARY_MEMORY_NEEDED
6106: /* If we need a memory location to do the move, do it that way. */
6107: else if (GET_CODE (reloadreg) == REG
6108: && REGNO (reloadreg) < FIRST_PSEUDO_REGISTER
6109: && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (reloadreg)),
6110: REGNO_REG_CLASS (REGNO (second_reloadreg)),
6111: GET_MODE (second_reloadreg)))
6112: {
6113: /* Get the memory to use and rewrite both registers
6114: to its mode. */
6115: rtx loc
6116: = get_secondary_mem (reloadreg,
6117: GET_MODE (second_reloadreg),
6118: reload_opnum[j],
6119: reload_when_needed[j]);
6120: rtx tmp_reloadreg;
6121:
6122: if (GET_MODE (loc) != GET_MODE (second_reloadreg))
6123: second_reloadreg = gen_rtx (REG, GET_MODE (loc),
6124: REGNO (second_reloadreg));
6125:
6126: if (GET_MODE (loc) != GET_MODE (reloadreg))
6127: tmp_reloadreg = gen_rtx (REG, GET_MODE (loc),
6128: REGNO (reloadreg));
6129: else
6130: tmp_reloadreg = reloadreg;
6131:
6132: emit_move_insn (loc, second_reloadreg);
6133: pat = gen_move_insn (tmp_reloadreg, loc);
6134: }
6135: #endif
6136: else
6137: pat = gen_move_insn (reloadreg, second_reloadreg);
6138:
6139: emit_insn (pat);
6140: }
6141: }
6142: }
6143: #endif
6144:
6145: /* Output the last reload insn. */
6146: if (! special)
6147: {
6148: #ifdef SECONDARY_MEMORY_NEEDED
6149: /* If we need a memory location to do the move, do it that way. */
6150: if (GET_CODE (old) == REG && REGNO (old) < FIRST_PSEUDO_REGISTER
6151: && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (old)),
6152: REGNO_REG_CLASS (REGNO (reloadreg)),
6153: GET_MODE (reloadreg)))
6154: {
6155: /* Get the memory to use and rewrite both registers to
6156: its mode. */
6157: rtx loc = get_secondary_mem (old, GET_MODE (reloadreg),
6158: reload_opnum[j],
6159: reload_when_needed[j]);
6160:
6161: if (GET_MODE (loc) != GET_MODE (reloadreg))
6162: reloadreg = gen_rtx (REG, GET_MODE (loc),
6163: REGNO (reloadreg));
6164:
6165: if (GET_MODE (loc) != GET_MODE (old))
6166: old = gen_rtx (REG, GET_MODE (loc), REGNO (old));
6167:
6168: emit_insn (gen_move_insn (loc, reloadreg));
6169: emit_insn (gen_move_insn (old, loc));
6170: }
6171: else
6172: #endif
6173: emit_insn (gen_move_insn (old, reloadreg));
6174: }
6175:
6176: #ifdef PRESERVE_DEATH_INFO_REGNO_P
6177: /* If final will look at death notes for this reg,
6178: put one on the last output-reload insn to use it. Similarly
6179: for any secondary register. */
6180: if (PRESERVE_DEATH_INFO_REGNO_P (REGNO (reloadreg)))
6181: for (p = get_last_insn (); p; p = PREV_INSN (p))
6182: if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
6183: && reg_overlap_mentioned_for_reload_p (reloadreg,
6184: PATTERN (p)))
6185: REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD,
6186: reloadreg, REG_NOTES (p));
6187:
6188: #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6189: if (! special
6190: && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reloadreg)))
6191: for (p = get_last_insn (); p; p = PREV_INSN (p))
6192: if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
6193: && reg_overlap_mentioned_for_reload_p (second_reloadreg,
6194: PATTERN (p)))
6195: REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD,
6196: second_reloadreg, REG_NOTES (p));
6197: #endif
6198: #endif
6199: /* Look at all insns we emitted, just to be safe. */
6200: for (p = get_insns (); p; p = NEXT_INSN (p))
6201: if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
6202: {
6203: /* If this output reload doesn't come from a spill reg,
6204: clear any memory of reloaded copies of the pseudo reg.
6205: If this output reload comes from a spill reg,
6206: reg_has_output_reload will make this do nothing. */
6207: note_stores (PATTERN (p), forget_old_reloads_1);
6208:
6209: if (reg_mentioned_p (reload_reg_rtx[j], PATTERN (p)))
6210: store_insn = p;
6211: }
6212:
6213: output_reload_insns[reload_opnum[j]] = get_insns ();
6214: end_sequence ();
6215:
6216: }
6217:
6218: if (reload_spill_index[j] >= 0)
6219: new_spill_reg_store[reload_spill_index[j]] = store_insn;
6220: }
6221:
6222: /* Now write all the insns we made for reloads in the order expected by
6223: the allocation functions. Prior to the insn being reloaded, we write
6224: the following reloads:
6225:
6226: RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6227:
6228: RELOAD_OTHER reloads.
6229:
6230: For each operand, any RELOAD_FOR_INPUT_ADDRESS reloads followed by
6231: the RELOAD_FOR_INPUT reload for the operand.
6232:
6233: RELOAD_FOR_OPERAND_ADDRESS reloads.
6234:
6235: After the insn being reloaded, we write the following:
6236:
6237: For each operand, any RELOAD_FOR_OUTPUT_ADDRESS reload followed by
6238: the RELOAD_FOR_OUTPUT reload for that operand. */
6239:
6240: emit_insns_before (other_input_address_reload_insns, before_insn);
6241: emit_insns_before (other_input_reload_insns, before_insn);
6242:
6243: for (j = 0; j < reload_n_operands; j++)
6244: {
6245: emit_insns_before (input_address_reload_insns[j], before_insn);
6246: emit_insns_before (input_reload_insns[j], before_insn);
6247: }
6248:
6249: emit_insns_before (operand_reload_insns, before_insn);
6250:
6251: for (j = 0; j < reload_n_operands; j++)
6252: {
6253: emit_insns_before (output_address_reload_insns[j], following_insn);
6254: emit_insns_before (output_reload_insns[j], following_insn);
6255: }
6256:
6257: /* Move death notes from INSN
6258: to output-operand-address and output reload insns. */
6259: #ifdef PRESERVE_DEATH_INFO_REGNO_P
6260: {
6261: rtx insn1;
6262: /* Loop over those insns, last ones first. */
6263: for (insn1 = PREV_INSN (following_insn); insn1 != insn;
6264: insn1 = PREV_INSN (insn1))
6265: if (GET_CODE (insn1) == INSN && GET_CODE (PATTERN (insn1)) == SET)
6266: {
6267: rtx source = SET_SRC (PATTERN (insn1));
6268: rtx dest = SET_DEST (PATTERN (insn1));
6269:
6270: /* The note we will examine next. */
6271: rtx reg_notes = REG_NOTES (insn);
6272: /* The place that pointed to this note. */
6273: rtx *prev_reg_note = ®_NOTES (insn);
6274:
6275: /* If the note is for something used in the source of this
6276: reload insn, or in the output address, move the note. */
6277: while (reg_notes)
6278: {
6279: rtx next_reg_notes = XEXP (reg_notes, 1);
6280: if (REG_NOTE_KIND (reg_notes) == REG_DEAD
6281: && GET_CODE (XEXP (reg_notes, 0)) == REG
6282: && ((GET_CODE (dest) != REG
6283: && reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
6284: dest))
6285: || reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
6286: source)))
6287: {
6288: *prev_reg_note = next_reg_notes;
6289: XEXP (reg_notes, 1) = REG_NOTES (insn1);
6290: REG_NOTES (insn1) = reg_notes;
6291: }
6292: else
6293: prev_reg_note = &XEXP (reg_notes, 1);
6294:
6295: reg_notes = next_reg_notes;
6296: }
6297: }
6298: }
6299: #endif
6300:
6301: /* For all the spill regs newly reloaded in this instruction,
6302: record what they were reloaded from, so subsequent instructions
6303: can inherit the reloads.
6304:
6305: Update spill_reg_store for the reloads of this insn.
6306: Copy the elements that were updated in the loop above. */
6307:
6308: for (j = 0; j < n_reloads; j++)
6309: {
6310: register int r = reload_order[j];
6311: register int i = reload_spill_index[r];
6312:
6313: /* I is nonneg if this reload used one of the spill regs.
6314: If reload_reg_rtx[r] is 0, this is an optional reload
6315: that we opted to ignore.
6316:
6317: Also ignore reloads that don't reach the end of the insn,
6318: since we will eventually see the one that does. */
6319:
6320: if (i >= 0 && reload_reg_rtx[r] != 0
6321: && reload_reg_reaches_end_p (spill_regs[i], reload_opnum[r],
6322: reload_when_needed[r]))
6323: {
6324: /* First, clear out memory of what used to be in this spill reg.
6325: If consecutive registers are used, clear them all. */
6326: int nr
6327: = HARD_REGNO_NREGS (spill_regs[i], GET_MODE (reload_reg_rtx[r]));
6328: int k;
6329:
6330: for (k = 0; k < nr; k++)
6331: {
6332: reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]] = -1;
6333: reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = 0;
6334: }
6335:
6336: /* Maybe the spill reg contains a copy of reload_out. */
6337: if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
6338: {
6339: register int nregno = REGNO (reload_out[r]);
6340: int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6341: : HARD_REGNO_NREGS (nregno,
6342: GET_MODE (reload_reg_rtx[r])));
6343:
6344: spill_reg_store[i] = new_spill_reg_store[i];
6345: reg_last_reload_reg[nregno] = reload_reg_rtx[r];
6346:
6347: /* If NREGNO is a hard register, it may occupy more than
6348: one register. If it does, say what is in the
6349: rest of the registers assuming that both registers
6350: agree on how many words the object takes. If not,
6351: invalidate the subsequent registers. */
6352:
6353: if (nregno < FIRST_PSEUDO_REGISTER)
6354: for (k = 1; k < nnr; k++)
6355: reg_last_reload_reg[nregno + k]
6356: = (nr == nnr ? gen_rtx (REG, word_mode,
6357: REGNO (reload_reg_rtx[r]) + k)
6358: : 0);
6359:
6360: /* Now do the inverse operation. */
6361: for (k = 0; k < nr; k++)
6362: {
6363: reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
6364: = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr ? nregno
6365: : nregno + k);
6366: reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = insn;
6367: }
6368: }
6369:
6370: /* Maybe the spill reg contains a copy of reload_in. Only do
6371: something if there will not be an output reload for
6372: the register being reloaded. */
6373: else if (reload_out[r] == 0
6374: && reload_in[r] != 0
6375: && ((GET_CODE (reload_in[r]) == REG
6376: && ! reg_has_output_reload[REGNO (reload_in[r])]
6377: || (GET_CODE (reload_in_reg[r]) == REG
6378: && ! reg_has_output_reload[REGNO (reload_in_reg[r])]))))
6379: {
6380: register int nregno;
6381: int nnr;
6382:
6383: if (GET_CODE (reload_in[r]) == REG)
6384: nregno = REGNO (reload_in[r]);
6385: else
6386: nregno = REGNO (reload_in_reg[r]);
6387:
6388: nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6389: : HARD_REGNO_NREGS (nregno,
6390: GET_MODE (reload_reg_rtx[r])));
6391:
6392: reg_last_reload_reg[nregno] = reload_reg_rtx[r];
6393:
6394: if (nregno < FIRST_PSEUDO_REGISTER)
6395: for (k = 1; k < nnr; k++)
6396: reg_last_reload_reg[nregno + k]
6397: = (nr == nnr ? gen_rtx (REG, word_mode,
6398: REGNO (reload_reg_rtx[r]) + k)
6399: : 0);
6400:
6401: /* Unless we inherited this reload, show we haven't
6402: recently done a store. */
6403: if (! reload_inherited[r])
6404: spill_reg_store[i] = 0;
6405:
6406: for (k = 0; k < nr; k++)
6407: {
6408: reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
6409: = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr ? nregno
6410: : nregno + k);
6411: reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]]
6412: = insn;
6413: }
6414: }
6415: }
6416:
6417: /* The following if-statement was #if 0'd in 1.34 (or before...).
6418: It's reenabled in 1.35 because supposedly nothing else
6419: deals with this problem. */
6420:
6421: /* If a register gets output-reloaded from a non-spill register,
6422: that invalidates any previous reloaded copy of it.
6423: But forget_old_reloads_1 won't get to see it, because
6424: it thinks only about the original insn. So invalidate it here. */
6425: if (i < 0 && reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
6426: {
6427: register int nregno = REGNO (reload_out[r]);
6428: reg_last_reload_reg[nregno] = 0;
6429: }
6430: }
6431: }
6432:
6433: /* Emit code to perform an input reload of IN to RELOADREG. IN is from
6434: operand OPNUM with reload type TYPE.
6435:
6436: Returns first insn emitted. */
6437:
6438: rtx
6439: gen_input_reload (reloadreg, in, opnum, type)
6440: rtx reloadreg;
6441: rtx in;
6442: int opnum;
6443: enum reload_type type;
6444: {
6445: rtx last = get_last_insn ();
6446:
6447: /* How to do this reload can get quite tricky. Normally, we are being
6448: asked to reload a simple operand, such as a MEM, a constant, or a pseudo
6449: register that didn't get a hard register. In that case we can just
6450: call emit_move_insn.
6451:
6452: We can also be asked to reload a PLUS that adds a register or a MEM to
6453: another register, constant or MEM. This can occur during frame pointer
6454: elimination and while reloading addresses. This case is handled by
6455: trying to emit a single insn to perform the add. If it is not valid,
6456: we use a two insn sequence.
6457:
6458: Finally, we could be called to handle an 'o' constraint by putting
6459: an address into a register. In that case, we first try to do this
6460: with a named pattern of "reload_load_address". If no such pattern
6461: exists, we just emit a SET insn and hope for the best (it will normally
6462: be valid on machines that use 'o').
6463:
6464: This entire process is made complex because reload will never
6465: process the insns we generate here and so we must ensure that
6466: they will fit their constraints and also by the fact that parts of
6467: IN might be being reloaded separately and replaced with spill registers.
6468: Because of this, we are, in some sense, just guessing the right approach
6469: here. The one listed above seems to work.
6470:
6471: ??? At some point, this whole thing needs to be rethought. */
6472:
6473: if (GET_CODE (in) == PLUS
6474: && (GET_CODE (XEXP (in, 0)) == REG
6475: || GET_CODE (XEXP (in, 0)) == MEM)
6476: && (GET_CODE (XEXP (in, 1)) == REG
6477: || CONSTANT_P (XEXP (in, 1))
6478: || GET_CODE (XEXP (in, 1)) == MEM))
6479: {
6480: /* We need to compute the sum of a register or a MEM and another
6481: register, constant, or MEM, and put it into the reload
6482: register. The best possible way of doing this is if the machine
6483: has a three-operand ADD insn that accepts the required operands.
6484:
6485: The simplest approach is to try to generate such an insn and see if it
6486: is recognized and matches its constraints. If so, it can be used.
6487:
6488: It might be better not to actually emit the insn unless it is valid,
6489: but we need to pass the insn as an operand to `recog' and
6490: `insn_extract' and it is simpler to emit and then delete the insn if
6491: not valid than to dummy things up. */
6492:
6493: rtx op0, op1, tem, insn;
6494: int code;
6495:
6496: op0 = find_replacement (&XEXP (in, 0));
6497: op1 = find_replacement (&XEXP (in, 1));
6498:
6499: /* Since constraint checking is strict, commutativity won't be
6500: checked, so we need to do that here to avoid spurious failure
6501: if the add instruction is two-address and the second operand
6502: of the add is the same as the reload reg, which is frequently
6503: the case. If the insn would be A = B + A, rearrange it so
6504: it will be A = A + B as constrain_operands expects. */
6505:
6506: if (GET_CODE (XEXP (in, 1)) == REG
6507: && REGNO (reloadreg) == REGNO (XEXP (in, 1)))
6508: tem = op0, op0 = op1, op1 = tem;
6509:
6510: if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
6511: in = gen_rtx (PLUS, GET_MODE (in), op0, op1);
6512:
6513: insn = emit_insn (gen_rtx (SET, VOIDmode, reloadreg, in));
6514: code = recog_memoized (insn);
6515:
6516: if (code >= 0)
6517: {
6518: insn_extract (insn);
6519: /* We want constrain operands to treat this insn strictly in
6520: its validity determination, i.e., the way it would after reload
6521: has completed. */
6522: if (constrain_operands (code, 1))
6523: return insn;
6524: }
6525:
6526: delete_insns_since (last);
6527:
6528: /* If that failed, we must use a conservative two-insn sequence.
6529: use move to copy constant, MEM, or pseudo register to the reload
6530: register since "move" will be able to handle an arbitrary operand,
6531: unlike add which can't, in general. Then add the registers.
6532:
6533: If there is another way to do this for a specific machine, a
6534: DEFINE_PEEPHOLE should be specified that recognizes the sequence
6535: we emit below. */
6536:
6537: if (CONSTANT_P (op1) || GET_CODE (op1) == MEM
6538: || (GET_CODE (op1) == REG
6539: && REGNO (op1) >= FIRST_PSEUDO_REGISTER))
6540: tem = op0, op0 = op1, op1 = tem;
6541:
6542: emit_insn (gen_move_insn (reloadreg, op0));
6543:
6544: /* If OP0 and OP1 are the same, we can use RELOADREG for OP1.
6545: This fixes a problem on the 32K where the stack pointer cannot
6546: be used as an operand of an add insn. */
6547:
6548: if (rtx_equal_p (op0, op1))
6549: op1 = reloadreg;
6550:
6551: emit_insn (gen_add2_insn (reloadreg, op1));
6552: }
6553:
6554: #ifdef SECONDARY_MEMORY_NEEDED
6555: /* If we need a memory location to do the move, do it that way. */
6556: else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
6557: && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
6558: REGNO_REG_CLASS (REGNO (reloadreg)),
6559: GET_MODE (reloadreg)))
6560: {
6561: /* Get the memory to use and rewrite both registers to its mode. */
6562: rtx loc = get_secondary_mem (in, GET_MODE (reloadreg), opnum, type);
6563:
6564: if (GET_MODE (loc) != GET_MODE (reloadreg))
6565: reloadreg = gen_rtx (REG, GET_MODE (loc), REGNO (reloadreg));
6566:
6567: if (GET_MODE (loc) != GET_MODE (in))
6568: in = gen_rtx (REG, GET_MODE (loc), REGNO (in));
6569:
6570: emit_insn (gen_move_insn (loc, in));
6571: emit_insn (gen_move_insn (reloadreg, loc));
6572: }
6573: #endif
6574:
6575: /* If IN is a simple operand, use gen_move_insn. */
6576: else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
6577: emit_insn (gen_move_insn (reloadreg, in));
6578:
6579: #ifdef HAVE_reload_load_address
6580: else if (HAVE_reload_load_address)
6581: emit_insn (gen_reload_load_address (reloadreg, in));
6582: #endif
6583:
6584: /* Otherwise, just write (set REGLOADREG IN) and hope for the best. */
6585: else
6586: emit_insn (gen_rtx (SET, VOIDmode, reloadreg, in));
6587:
6588: /* Return the first insn emitted.
6589: We can not just return get_last_insn, because there may have
6590: been multiple instructions emitted. Also note that gen_move_insn may
6591: emit more than one insn itself, so we can not assume that there is one
6592: insn emitted per emit_insn_before call. */
6593:
6594: return last ? NEXT_INSN (last) : get_insns ();
6595: }
6596:
6597: /* Delete a previously made output-reload
6598: whose result we now believe is not needed.
6599: First we double-check.
6600:
6601: INSN is the insn now being processed.
6602: OUTPUT_RELOAD_INSN is the insn of the output reload.
6603: J is the reload-number for this insn. */
6604:
6605: static void
6606: delete_output_reload (insn, j, output_reload_insn)
6607: rtx insn;
6608: int j;
6609: rtx output_reload_insn;
6610: {
6611: register rtx i1;
6612:
6613: /* Get the raw pseudo-register referred to. */
6614:
6615: rtx reg = reload_in[j];
6616: while (GET_CODE (reg) == SUBREG)
6617: reg = SUBREG_REG (reg);
6618:
6619: /* If the pseudo-reg we are reloading is no longer referenced
6620: anywhere between the store into it and here,
6621: and no jumps or labels intervene, then the value can get
6622: here through the reload reg alone.
6623: Otherwise, give up--return. */
6624: for (i1 = NEXT_INSN (output_reload_insn);
6625: i1 != insn; i1 = NEXT_INSN (i1))
6626: {
6627: if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
6628: return;
6629: if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
6630: && reg_mentioned_p (reg, PATTERN (i1)))
6631: return;
6632: }
6633:
6634: if (cannot_omit_stores[REGNO (reg)])
6635: return;
6636:
6637: /* If this insn will store in the pseudo again,
6638: the previous store can be removed. */
6639: if (reload_out[j] == reload_in[j])
6640: delete_insn (output_reload_insn);
6641:
6642: /* See if the pseudo reg has been completely replaced
6643: with reload regs. If so, delete the store insn
6644: and forget we had a stack slot for the pseudo. */
6645: else if (reg_n_deaths[REGNO (reg)] == 1
6646: && reg_basic_block[REGNO (reg)] >= 0
6647: && find_regno_note (insn, REG_DEAD, REGNO (reg)))
6648: {
6649: rtx i2;
6650:
6651: /* We know that it was used only between here
6652: and the beginning of the current basic block.
6653: (We also know that the last use before INSN was
6654: the output reload we are thinking of deleting, but never mind that.)
6655: Search that range; see if any ref remains. */
6656: for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
6657: {
6658: rtx set = single_set (i2);
6659:
6660: /* Uses which just store in the pseudo don't count,
6661: since if they are the only uses, they are dead. */
6662: if (set != 0 && SET_DEST (set) == reg)
6663: continue;
6664: if (GET_CODE (i2) == CODE_LABEL
6665: || GET_CODE (i2) == JUMP_INSN)
6666: break;
6667: if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
6668: && reg_mentioned_p (reg, PATTERN (i2)))
6669: /* Some other ref remains;
6670: we can't do anything. */
6671: return;
6672: }
6673:
6674: /* Delete the now-dead stores into this pseudo. */
6675: for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
6676: {
6677: rtx set = single_set (i2);
6678:
6679: if (set != 0 && SET_DEST (set) == reg)
6680: delete_insn (i2);
6681: if (GET_CODE (i2) == CODE_LABEL
6682: || GET_CODE (i2) == JUMP_INSN)
6683: break;
6684: }
6685:
6686: /* For the debugging info,
6687: say the pseudo lives in this reload reg. */
6688: reg_renumber[REGNO (reg)] = REGNO (reload_reg_rtx[j]);
6689: alter_reg (REGNO (reg), -1);
6690: }
6691: }
6692:
6693: /* Output reload-insns to reload VALUE into RELOADREG.
6694: VALUE is an autoincrement or autodecrement RTX whose operand
6695: is a register or memory location;
6696: so reloading involves incrementing that location.
6697:
6698: INC_AMOUNT is the number to increment or decrement by (always positive).
6699: This cannot be deduced from VALUE. */
6700:
6701: static void
6702: inc_for_reload (reloadreg, value, inc_amount)
6703: rtx reloadreg;
6704: rtx value;
6705: int inc_amount;
6706: {
6707: /* REG or MEM to be copied and incremented. */
6708: rtx incloc = XEXP (value, 0);
6709: /* Nonzero if increment after copying. */
6710: int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
6711: rtx last;
6712: rtx inc;
6713: rtx add_insn;
6714: int code;
6715:
6716: /* No hard register is equivalent to this register after
6717: inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
6718: we could inc/dec that register as well (maybe even using it for
6719: the source), but I'm not sure it's worth worrying about. */
6720: if (GET_CODE (incloc) == REG)
6721: reg_last_reload_reg[REGNO (incloc)] = 0;
6722:
6723: if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
6724: inc_amount = - inc_amount;
6725:
6726: inc = GEN_INT (inc_amount);
6727:
6728: /* If this is post-increment, first copy the location to the reload reg. */
6729: if (post)
6730: emit_insn (gen_move_insn (reloadreg, incloc));
6731:
6732: /* See if we can directly increment INCLOC. Use a method similar to that
6733: in gen_input_reload. */
6734:
6735: last = get_last_insn ();
6736: add_insn = emit_insn (gen_rtx (SET, VOIDmode, incloc,
6737: gen_rtx (PLUS, GET_MODE (incloc),
6738: incloc, inc)));
6739:
6740: code = recog_memoized (add_insn);
6741: if (code >= 0)
6742: {
6743: insn_extract (add_insn);
6744: if (constrain_operands (code, 1))
6745: {
6746: /* If this is a pre-increment and we have incremented the value
6747: where it lives, copy the incremented value to RELOADREG to
6748: be used as an address. */
6749:
6750: if (! post)
6751: emit_insn (gen_move_insn (reloadreg, incloc));
6752:
6753: return;
6754: }
6755: }
6756:
6757: delete_insns_since (last);
6758:
6759: /* If couldn't do the increment directly, must increment in RELOADREG.
6760: The way we do this depends on whether this is pre- or post-increment.
6761: For pre-increment, copy INCLOC to the reload register, increment it
6762: there, then save back. */
6763:
6764: if (! post)
6765: {
6766: emit_insn (gen_move_insn (reloadreg, incloc));
6767: emit_insn (gen_add2_insn (reloadreg, inc));
6768: emit_insn (gen_move_insn (incloc, reloadreg));
6769: }
6770: else
6771: {
6772: /* Postincrement.
6773: Because this might be a jump insn or a compare, and because RELOADREG
6774: may not be available after the insn in an input reload, we must do
6775: the incrementation before the insn being reloaded for.
6776:
6777: We have already copied INCLOC to RELOADREG. Increment the copy in
6778: RELOADREG, save that back, then decrement RELOADREG so it has
6779: the original value. */
6780:
6781: emit_insn (gen_add2_insn (reloadreg, inc));
6782: emit_insn (gen_move_insn (incloc, reloadreg));
6783: emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
6784: }
6785:
6786: return;
6787: }
6788:
6789: /* Return 1 if we are certain that the constraint-string STRING allows
6790: the hard register REG. Return 0 if we can't be sure of this. */
6791:
6792: static int
6793: constraint_accepts_reg_p (string, reg)
6794: char *string;
6795: rtx reg;
6796: {
6797: int value = 0;
6798: int regno = true_regnum (reg);
6799: int c;
6800:
6801: /* Initialize for first alternative. */
6802: value = 0;
6803: /* Check that each alternative contains `g' or `r'. */
6804: while (1)
6805: switch (c = *string++)
6806: {
6807: case 0:
6808: /* If an alternative lacks `g' or `r', we lose. */
6809: return value;
6810: case ',':
6811: /* If an alternative lacks `g' or `r', we lose. */
6812: if (value == 0)
6813: return 0;
6814: /* Initialize for next alternative. */
6815: value = 0;
6816: break;
6817: case 'g':
6818: case 'r':
6819: /* Any general reg wins for this alternative. */
6820: if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
6821: value = 1;
6822: break;
6823: default:
6824: /* Any reg in specified class wins for this alternative. */
6825: {
6826: enum reg_class class = REG_CLASS_FROM_LETTER (c);
6827:
6828: if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
6829: value = 1;
6830: }
6831: }
6832: }
6833:
6834: /* Return the number of places FIND appears within X, but don't count
6835: an occurrence if some SET_DEST is FIND. */
6836:
6837: static int
6838: count_occurrences (x, find)
6839: register rtx x, find;
6840: {
6841: register int i, j;
6842: register enum rtx_code code;
6843: register char *format_ptr;
6844: int count;
6845:
6846: if (x == find)
6847: return 1;
6848: if (x == 0)
6849: return 0;
6850:
6851: code = GET_CODE (x);
6852:
6853: switch (code)
6854: {
6855: case REG:
6856: case QUEUED:
6857: case CONST_INT:
6858: case CONST_DOUBLE:
6859: case SYMBOL_REF:
6860: case CODE_LABEL:
6861: case PC:
6862: case CC0:
6863: return 0;
6864:
6865: case SET:
6866: if (SET_DEST (x) == find)
6867: return count_occurrences (SET_SRC (x), find);
6868: break;
6869: }
6870:
6871: format_ptr = GET_RTX_FORMAT (code);
6872: count = 0;
6873:
6874: for (i = 0; i < GET_RTX_LENGTH (code); i++)
6875: {
6876: switch (*format_ptr++)
6877: {
6878: case 'e':
6879: count += count_occurrences (XEXP (x, i), find);
6880: break;
6881:
6882: case 'E':
6883: if (XVEC (x, i) != NULL)
6884: {
6885: for (j = 0; j < XVECLEN (x, i); j++)
6886: count += count_occurrences (XVECEXP (x, i, j), find);
6887: }
6888: break;
6889: }
6890: }
6891: return count;
6892: }
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