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1.1 ! root 1: /* hppa-opcode.h */ ! 2: /* Table of opcodes for the hppa. ! 3: Copyright (C) 1990 Free Software Foundation, Inc. ! 4: ! 5: This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler. ! 6: ! 7: GAS/GDB is free software; you can redistribute it and/or modify ! 8: it under the terms of the GNU General Public License as published by ! 9: the Free Software Foundation; either version 1, or (at your option) ! 10: any later version. ! 11: ! 12: GAS/GDB is distributed in the hope that it will be useful, ! 13: but WITHOUT ANY WARRANTY; without even the implied warranty of ! 14: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ! 15: GNU General Public License for more details. ! 16: ! 17: You should have received a copy of the GNU General Public License ! 18: along with GAS or GDB; see the file COPYING. If not, write to ! 19: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ ! 20: ! 21: /* ! 22: HP PA-RISC support was contributed by the Center for Software Science ! 23: at the University of Utah. ! 24: */ ! 25: ! 26: /* HP-PA support for Mach-O ... USV */ ! 27: ! 28: #ifndef HPPA_OPCODE_INCLUDED ! 29: #define HPPA_OPCODE_INCLUDED ! 30: ! 31: #if !defined(__STDC__) && !defined(const) ! 32: #define const ! 33: #endif ! 34: ! 35: /* bug #41317 .... [email protected] Mon May 2 17:53:29 PDT 1994 */ ! 36: /* The masks for 2 bits at 20 */ ! 37: ! 38: #define NO_CACHE_CONTROL_HINT (unsigned long)0x0UL ! 39: #define BC_OR_CO_CACHE_CONTROL_HINT (unsigned long)0x400UL ! 40: ! 41: /************************************************************************ ! 42: * The parsing characters used in the opcode table are listed in ASCII ! 43: * order. This is updated list as of Wed Jul 27 14:15:09 PDT 1994 ! 44: * --- Umesh. ! 45: ***************** Begin List ******************************************* ! 46: ! negated or non-negated add conditions (used only by 'addb' and 'addib' pseudo-instructions) ! 47: & logical instruction conditions ! 48: + non-negated add conditions ! 49: - compare/subtract conditions ! 50: 0 10 bit Special Function Unit operation split between 5 bits at 20 and 5 bits at 31 ! 51: 1 15 bit Special Function Unit operation split between 10 bits at 20 and 5 bits at 31 ! 52: 2 22 bit Special Function Unit operation split between 17 bits at 20 and 5 bits at 31 ! 53: 3 Store Instruction Cache Control Hint (Table 5-8) with Indexed load completers (Table 5-10) ! 54: 4 a variation of the 'b' operand type for 'fmpyadd' and 'fmpysub' ! 55: 5 5 bit immediate at 15. ! 56: 6 a variation of the 'x' operand type for 'fmpyadd' and 'fmpysub' ! 57: 7 a variation of the 't' operand type for 'fmpyadd' and 'fmpysub' ! 58: 8 5 bit register field at 20 (used in 'fmpyadd' and 'fmpysub') ! 59: 9 5 bit register field at 25 (used in 'fmpyadd' and 'fmpysub') ! 60: < non-negated compare/subtract conditions. ! 61: > shift/extract/deposit conditions. ! 62: ? negated or non-negated compare/subtract conditions (used only by 'comb' and 'comib' pseudo-instructions) ! 63: @ 17 bit branch displacement --- JBSR ! 64: A 13 bit immediate at 18 (to support the BREAK instruction) ! 65: B either s,b or b where 's' 2 bit space specifier at 17 and 'b' register field at 10. ! 66: C short load and store completer. ! 67: D 26 bit immediate at 31 (to support the DIAG instruction) ! 68: E a 'b' operand type extended to handle L/R register halves. ! 69: F Source Floating Point Operand Format Completer encoded 2 bits at 20 ! 70: G Destination Floating Point Operand Format Completer encoded 2 bits at 18 ! 71: H Floating Point Operand Format at 26 for 'fmpyadd' and 'fmpysub' (very similar to 'F') ! 72: L Load and Clear Word Cache Control Hint with Indexed load completers ! 73: M Floating-Point Compare Conditions (encoded as 5 bits at 31) ! 74: O 20 bit Special Function Unit operation split between 15 bits at 20 and 5 bits at 31 ! 75: P 5 bit bit position at 26 ! 76: Q 5 bit immediate value at 10 (a bit position specified in the bb instruction. It's the same as r above, except the value is in a different location) ! 77: R 5 bit immediate value at 15 (for the ssm, rsm instruction) (same as r above, except the value is in a different location) ! 78: S 3 bit space specifier at 18. ! 79: T 5 bit field length at 31 (encoded as 32-T) ! 80: U unit instruction conditions ! 81: V 5 bit immediate value at 31 ! 82: W 17 bit branch displacement (pc-rel for BL and GATE) ! 83: X an 'x' operand type extended to handle L/R register halves. ! 84: Y Store Bytes Short completer with cache control hints ! 85: Z System Control Completer (to support LDA, LHA, etc.) ! 86: a Load and Clear Word Cache Control Hint with Short displacement load and store completers ! 87: b register field at 10. ! 88: c indexed load completer. ! 89: f 3 bit Special Function Unit identifier at 25 ! 90: i 11 bit immediate value at 31 ! 91: j 14 bit immediate value at 31 ! 92: k 21 bit immediate value at 31 ! 93: l Store Instruction Cache Control Hint with Short displacement load and store completers ! 94: n nullification for branch instructions ! 95: o 15 bit Special Function Unit operation at 20 ! 96: p 5 bit shift count at 26 (to support the SHD instruction) encoded as (31-p) ! 97: r 5 bit immediate value at 31 (for the break instruction) (very similar to V above, except the value is unsigned instead of low_sign_ext) ! 98: s 2 bit space specifier at 17. ! 99: t register field at 31. ! 100: u 3 bit coprocessor unit identifier at 25 ! 101: v a 't' operand type extended to handle L/R register halves. ! 102: w 12 bit branch displacement ! 103: x register field at 15. ! 104: y nullification at 26 ! 105: z 17 bit branch displacement (not pc-rel) ! 106: ~ bvb,bb conditions ! 107: ***************** End List ******************************************* ! 108: * The following characters are available for use later. If used in future ! 109: * please delete from this list and add to the list above (in order). ! 110: ! 111: " # $ % ' * . / : ; = I J K N [ \ ] ^ _ ` d e g h m q { | } ! 112: ! 113: ************************************************************************/ ! 114: ! 115: /* ! 116: * Structure of an opcode table entry. ! 117: */ ! 118: ! 119: /* There are two kinds of delay slot nullification: normal which is ! 120: * controled by the nullification bit, and conditional, which depends ! 121: * on the direction of the branch and its success or failure. ! 122: */ ! 123: enum delay_type {NONE, NORMAL, CONDITIONAL}; ! 124: struct pa_opcode ! 125: { ! 126: const char *name; ! 127: unsigned long int match; /* Bits that must be set... */ ! 128: unsigned long int mask; /* ... in these bits. */ ! 129: char *args; ! 130: /* Nonzero if this is a delayed branch instruction. */ ! 131: char delayed; ! 132: }; ! 133: ! 134: /* ! 135: All hppa opcodes are 32 bits. ! 136: ! 137: The match component is a mask saying which bits must match a ! 138: particular opcode in order for an instruction to be an instance ! 139: of that opcode. ! 140: ! 141: The args component is a string containing one character ! 142: for each operand of the instruction. ! 143: ! 144: Bit positions in this description follow HP usage of lsb = 31, ! 145: "at" is lsb of field. ! 146: ! 147: Kinds of operands: ! 148: x register field at 15. ! 149: b register field at 10. ! 150: t register field at 31. ! 151: 5 5 bit immediate at 15. ! 152: s 2 bit space specifier at 17. ! 153: S 3 bit space specifier at 18. ! 154: c indexed load completer. ! 155: C short load and store completer. ! 156: Y Store Bytes Short completer ! 157: < non-negated compare/subtract conditions. ! 158: - compare/subtract conditions ! 159: + non-negated add conditions ! 160: & logical instruction conditions ! 161: U unit instruction conditions ! 162: > shift/extract/deposit conditions. ! 163: ~ bvb,bb conditions ! 164: V 5 bit immediate value at 31 ! 165: i 11 bit immediate value at 31 ! 166: j 14 bit immediate value at 31 ! 167: k 21 bit immediate value at 31 ! 168: n nullification for branch instructions ! 169: w 12 bit branch displacement ! 170: W 17 bit branch displacement (pc-rel for BL and GATE) ! 171: z 17 bit branch displacement (not pc-rel) ! 172: ! 173: Also these (PJH): ! 174: ! 175: B either s,b or b where ! 176: ! 177: s 2 bit space specifier at 17. ! 178: b register field at 10. ! 179: ! 180: p 5 bit shift count at 26 (to support the SHD instruction) encoded as ! 181: 31-p ! 182: P 5 bit bit position at 26 ! 183: T 5 bit field length at 31 (encoded as 32-T) ! 184: A 13 bit immediate at 18 (to support the BREAK instruction) ! 185: Z System Control Completer (to support LDA, LHA, etc.) ! 186: D 26 bit immediate at 31 (to support the DIAG instruction) ! 187: ! 188: f 3 bit Special Function Unit identifier at 25 ! 189: O 20 bit Special Function Unit operation split between 15 bits at 20 ! 190: and 5 bits at 31 ! 191: o 15 bit Special Function Unit operation at 20 ! 192: 2 22 bit Special Function Unit operation split between 17 bits at 20 ! 193: and 5 bits at 31 ! 194: 1 15 bit Special Function Unit operation split between 10 bits at 20 ! 195: and 5 bits at 31 ! 196: 0 10 bit Special Function Unit operation split between 5 bits at 20 ! 197: and 5 bits at 31 ! 198: u 3 bit coprocessor unit identifier at 25 ! 199: F Source Floating Point Operand Format Completer encoded 2 bits at 20 ! 200: G Destination Floating Point Operand Format Completer encoded 2 bits at 18 ! 201: M Floating-Point Compare Conditions (encoded as 5 bits at 31) ! 202: ? negated or non-negated compare/subtract conditions ! 203: (used only by 'comb' and 'comib' pseudo-instructions) ! 204: ! negated or non-negated add conditions ! 205: (used only by 'addb' and 'addib' pseudo-instructions) ! 206: r 5 bit immediate value at 31 (for the break instruction) ! 207: (very similar to V above, except the value is unsigned instead of ! 208: low_sign_ext) ! 209: R 5 bit immediate value at 15 (for the ssm, rsm instruction) ! 210: (same as r above, except the value is in a different location) ! 211: Q 5 bit immediate value at 10 (a bit position specified in ! 212: the bb instruction. It's the same as r above, except the ! 213: value is in a different location) ! 214: ! 215: And these (PJH) for PA-89 F.P. registers and instructions: ! 216: ! 217: v a 't' operand type extended to handle L/R register halves. ! 218: E a 'b' operand type extended to handle L/R register halves. ! 219: X an 'x' operand type extended to handle L/R register halves. ! 220: 4 a variation of the 'b' operand type for 'fmpyadd' and 'fmpysub' ! 221: 6 a variation of the 'x' operand type for 'fmpyadd' and 'fmpysub' ! 222: 7 a variation of the 't' operand type for 'fmpyadd' and 'fmpysub' ! 223: 8 5 bit register field at 20 (used in 'fmpyadd' and 'fmpysub') ! 224: 9 5 bit register field at 25 (used in 'fmpyadd' and 'fmpysub') ! 225: H Floating Point Operand Format at 26 for 'fmpyadd' and 'fmpysub' ! 226: (very similar to 'F') ! 227: ! 228: */ ! 229: ! 230: /* bug #41317 .... [email protected] Mon May 2 17:53:29 PDT 1994 ! 231: ! 232: These are for 'cache control hints' ! 233: ! 234: l Store Instruction Cache Control Hint (Table 5-8) with ! 235: Short displacement load and store completers (Table 5-11) ! 236: ! 237: L Load and Clear Word Cache Control Hint (Table 5-9) with ! 238: Indexed load completers (Table 5-10) ! 239: ! 240: 3 Store Instruction Cache Control Hint (Table 5-8) with ! 241: Indexed load completers (Table 5-10) ! 242: ! 243: a Load and Clear Word Cache Control Hint (Table 5-9) with ! 244: Short displacement load and store completers (Table 5-11) ! 245: ! 246: These parse ",cc" and encode "cc" in 2 bits at 20, ! 247: where "cc" encoding is as given in Tables 5-8, 5-9. ! 248: Refer to 'PA-RISC 1.1 Architecture and Instruction Set Reference ! 249: Manual, Second Edition' for the tables. ! 250: */ ! 251: ! 252: /* The order of the opcodes in this table is significant: ! 253: ! 254: * The assembler requires that all instances of the same mnemonic must be ! 255: consecutive. If they aren't, the assembler will bomb at runtime. ! 256: ! 257: * The disassembler should not care about the order of the opcodes. */ ! 258: ! 259: static struct pa_opcode pa_opcodes[] = ! 260: { ! 261: ! 262: /* pseudo-instructions (first so otool matches them) */ ! 263: ! 264: { "b", 0xe8000000, 0xffe0e000, "nW", NORMAL}, ! 265: { "ldi", 0x34000000, 0xffe0c000, "j,x"}, /* j by a */ ! 266: { "comib", 0x84000000, 0xfc000000, "?n5,b,w", CONDITIONAL}, ! 267: { "comb", 0x80000000, 0xfc000000, "?nx,b,w", CONDITIONAL}, ! 268: { "addb", 0xa0000000, 0xfc000000, "!nx,b,w", CONDITIONAL}, ! 269: { "addib", 0xa4000000, 0xfc000000, "!n5,b,w", CONDITIONAL}, ! 270: { "nop", 0x08000240, 0xffffffff, ""}, /* NOP <=> OR 0,0,0 */ ! 271: { "copy", 0x08000240, 0xffe0ffe0, "x,t"}, /* COPY <=> OR r,0,t */ ! 272: ! 273: /* real instructions */ ! 274: { "ldw", 0x48000000, 0xfc000000, "j(B),x"}, ! 275: { "ldh", 0x44000000, 0xfc000000, "j(B),x"}, ! 276: { "ldb", 0x40000000, 0xfc000000, "j(B),x"}, ! 277: { "stw", 0x68000000, 0xfc000000, "x,j(B)"}, ! 278: { "sth", 0x64000000, 0xfc000000, "x,j(B)"}, ! 279: { "stb", 0x60000000, 0xfc000000, "x,j(B)"}, ! 280: { "ldwm", 0x4c000000, 0xfc000000, "j(B),x"}, ! 281: { "stwm", 0x6c000000, 0xfc000000, "x,j(B)"}, ! 282: { "ldwx", 0x0c000080, 0xfc001fc0, "cx(B),t"}, ! 283: { "ldhx", 0x0c000040, 0xfc001fc0, "cx(B),t"}, ! 284: { "ldbx", 0x0c000000, 0xfc001fc0, "cx(B),t"}, ! 285: { "ldwax", 0x0c000180, 0xfc00dfc0, "cx(b),t"}, ! 286: { "ldcwx", 0x0c0001c0, 0xfc001bc0, "Lx(B),t"}, /* #41317 */ ! 287: { "ldws", 0x0c001080, 0xfc001fc0, "C5(B),t"}, ! 288: { "ldhs", 0x0c001040, 0xfc001fc0, "C5(B),t"}, ! 289: { "ldbs", 0x0c001000, 0xfc001fc0, "C5(B),t"}, ! 290: { "ldwas", 0x0c001180, 0xfc00dfc0, "C5(b),t"}, ! 291: { "ldcws", 0x0c0011c0, 0xfc001bc0, "a5(B),t"}, /* #41317 was "CL5(B),t" */ ! 292: { "stws", 0x0c001280, 0xfc001bc0, "lx,V(B)"}, /* #41317 */ ! 293: { "sths", 0x0c001240, 0xfc001bc0, "lx,V(B)"}, /* #41317 */ ! 294: { "stbs", 0x0c001200, 0xfc001bc0, "lx,V(B)"}, /* #41317 */ ! 295: { "stwas", 0x0c001380, 0xfc00dbc0, "lx,V(b)"}, /* #41317 */ ! 296: { "stbys", 0x0c001300, 0xfc001bc0, "Yx,V(B)"}, /* #41317 */ ! 297: { "ldo", 0x34000000, 0xfc00c000, "j(b),x"}, ! 298: { "ldil", 0x20000000, 0xfc000000, "k,b"}, ! 299: { "addil", 0x28000000, 0xfc000000, "k,b"}, ! 300: { "bl", 0xe8000000, 0xfc00e000, "nW,b", NORMAL}, ! 301: { "gate", 0xe8002000, 0xfc00e000, "nW,b", NORMAL}, ! 302: { "blr", 0xe8004000, 0xfc00e001, "nx,b", NORMAL}, ! 303: { "bv", 0xe800c000, 0xfc00e001, "nx(b)", NORMAL}, ! 304: { "be", 0xe0000000, 0xfc000000, "nz(S,b)", NORMAL}, ! 305: { "ble", 0xe4000000, 0xfc000000, "nz(S,b)", NORMAL}, ! 306: { "movb", 0xc8000000, 0xfc000000, ">nx,b,w", CONDITIONAL}, ! 307: { "movib", 0xcc000000, 0xfc000000, ">n5,b,w", CONDITIONAL}, ! 308: { "combt", 0x80000000, 0xfc000000, "<nx,b,w", CONDITIONAL}, ! 309: { "combf", 0x88000000, 0xfc000000, "<nx,b,w", CONDITIONAL}, ! 310: { "comibt", 0x84000000, 0xfc000000, "<n5,b,w", CONDITIONAL}, ! 311: { "comibf", 0x8c000000, 0xfc000000, "<n5,b,w", CONDITIONAL}, ! 312: { "addbt", 0xa0000000, 0xfc000000, "+nx,b,w", CONDITIONAL}, ! 313: { "addbf", 0xa8000000, 0xfc000000, "+nx,b,w", CONDITIONAL}, ! 314: { "addibt", 0xa4000000, 0xfc000000, "+n5,b,w", CONDITIONAL}, ! 315: { "addibf", 0xac000000, 0xfc000000, "+n5,b,w", CONDITIONAL}, ! 316: { "bvb", 0xc0000000, 0xffe00000, "~nx,w", CONDITIONAL}, ! 317: { "bb", 0xc4000000, 0xfc000000, "~nx,Q,w", CONDITIONAL}, /* maybe */ ! 318: ! 319: /* Computation Instructions */ ! 320: ! 321: { "add", 0x08000600, 0xfc000fe0, "+x,b,t", CONDITIONAL}, ! 322: { "addl", 0x08000a00, 0xfc000fe0, "+x,b,t", CONDITIONAL}, ! 323: { "addo", 0x08000e00, 0xfc000fe0, "+x,b,t", CONDITIONAL}, ! 324: { "addc", 0x08000700, 0xfc000fe0, "+x,b,t", CONDITIONAL}, ! 325: { "addco", 0x08000f00, 0xfc000fe0, "+x,b,t", CONDITIONAL}, ! 326: { "sh1add", 0x08000640, 0xfc000fe0, "+x,b,t", CONDITIONAL}, ! 327: { "sh1addl", 0x08000a40, 0xfc000fe0, "+x,b,t", CONDITIONAL}, ! 328: { "sh1addo", 0x08000e40, 0xfc000fe0, "+x,b,t", CONDITIONAL}, ! 329: { "sh2add", 0x08000680, 0xfc000fe0, "+x,b,t", CONDITIONAL}, ! 330: { "sh2addl", 0x08000a80, 0xfc000fe0, "+x,b,t", CONDITIONAL}, ! 331: { "sh2addo", 0x08000e80, 0xfc000fe0, "+x,b,t", CONDITIONAL}, ! 332: { "sh3add", 0x080006c0, 0xfc000fe0, "+x,b,t", CONDITIONAL}, ! 333: { "sh3addl", 0x08000ac0, 0xfc000fe0, "+x,b,t", CONDITIONAL}, ! 334: { "sh3addo", 0x08000ec0, 0xfc000fe0, "+x,b,t", CONDITIONAL}, ! 335: { "sub", 0x08000400, 0xfc000fe0, "-x,b,t", CONDITIONAL}, ! 336: { "subo", 0x08000c00, 0xfc000fe0, "-x,b,t", CONDITIONAL}, ! 337: { "subb", 0x08000500, 0xfc000fe0, "-x,b,t", CONDITIONAL}, ! 338: { "subbo", 0x08000d00, 0xfc000fe0, "-x,b,t", CONDITIONAL}, ! 339: { "subt", 0x080004c0, 0xfc000fe0, "-x,b,t", CONDITIONAL}, ! 340: { "subto", 0x08000cc0, 0xfc000fe0, "-x,b,t", CONDITIONAL}, ! 341: { "ds", 0x08000440, 0xfc000fe0, "-x,b,t", CONDITIONAL}, ! 342: { "comclr", 0x08000880, 0xfc000fe0, "-x,b,t", CONDITIONAL}, ! 343: { "or", 0x08000240, 0xfc000fe0, "&x,b,t", CONDITIONAL}, ! 344: { "xor", 0x08000280, 0xfc000fe0, "&x,b,t", CONDITIONAL}, ! 345: { "and", 0x08000200, 0xfc000fe0, "&x,b,t", CONDITIONAL}, ! 346: { "andcm", 0x08000000, 0xfc000fe0, "&x,b,t", CONDITIONAL}, ! 347: { "uxor", 0x08000380, 0xfc000fe0, "Ux,b,t", CONDITIONAL}, ! 348: { "uaddcm", 0x08000980, 0xfc000fe0, "Ux,b,t", CONDITIONAL}, ! 349: { "uaddcmt", 0x080009c0, 0xfc000fe0, "Ux,b,t", CONDITIONAL}, ! 350: { "dcor", 0x08000b80, 0xfc1f0fe0, "Ub,t", CONDITIONAL}, ! 351: { "idcor", 0x08000bc0, 0xfc1f0fe0, "Ub,t", CONDITIONAL}, ! 352: { "addi", 0xb4000000, 0xfc000800, "+i,b,x", CONDITIONAL}, ! 353: { "addio", 0xb4000800, 0xfc000800, "+i,b,x", CONDITIONAL}, ! 354: { "addit", 0xb0000000, 0xfc000800, "+i,b,x", CONDITIONAL}, ! 355: { "addito", 0xb0000800, 0xfc000800, "+i,b,x", CONDITIONAL}, ! 356: { "subi", 0x94000000, 0xfc000800, "-i,b,x", CONDITIONAL}, ! 357: { "subio", 0x94000800, 0xfc000800, "-i,b,x", CONDITIONAL}, ! 358: { "comiclr", 0x90000000, 0xfc000800, "-i,b,x", CONDITIONAL}, ! 359: { "vshd", 0xd0000000, 0xfc001fe0, ">x,b,t", CONDITIONAL}, ! 360: { "shd", 0xd0000800, 0xfc001c00, ">x,b,p,t", CONDITIONAL}, ! 361: { "vextru", 0xd0001000, 0xfc001fe0, ">b,T,x", CONDITIONAL}, ! 362: { "vextrs", 0xd0001400, 0xfc001fe0, ">b,T,x", CONDITIONAL}, ! 363: { "extru", 0xd0001800, 0xfc001c00, ">b,P,T,x", CONDITIONAL}, ! 364: { "extrs", 0xd0001c00, 0xfc001c00, ">b,P,T,x", CONDITIONAL}, ! 365: { "vdep", 0xd4000400, 0xfc001fe0, ">x,T,b", CONDITIONAL}, ! 366: { "dep", 0xd4000c00, 0xfc001c00, ">x,p,T,b", CONDITIONAL}, ! 367: { "vdepi", 0xd4001400, 0xfc001fe0, ">5,T,b", CONDITIONAL}, ! 368: { "depi", 0xd4001c00, 0xfc001c00, ">5,p,T,b", CONDITIONAL}, ! 369: { "zvdep", 0xd4000000, 0xfc001fe0, ">x,T,b", CONDITIONAL}, ! 370: { "zdep", 0xd4000800, 0xfc001c00, ">x,p,T,b", CONDITIONAL}, ! 371: { "zvdepi", 0xd4001000, 0xfc001fe0, ">5,T,b", CONDITIONAL}, ! 372: { "zdepi", 0xd4001800, 0xfc001c00, ">5,p,T,b", CONDITIONAL}, ! 373: ! 374: /* System Control Instructions */ ! 375: ! 376: { "break", 0x00000000, 0xfc001fe0, "r,A"}, ! 377: { "rfi", 0x00000c00, 0xffffffff, ""}, ! 378: { "rfir", 0x00000ca0, 0xffffffff, ""}, ! 379: { "ssm", 0x00000d60, 0xffe0ffe0, "R,t"}, ! 380: { "rsm", 0x00000e60, 0xffe0ffe0, "R,t"}, ! 381: { "mtsm", 0x00001860, 0xffe0ffff, "x"}, ! 382: { "ldsid", 0x000010a0, 0xfc1f3fe0, "(B),t"}, ! 383: { "mtsp", 0x00001820, 0xffe01fff, "x,S"}, ! 384: { "mtctl", 0x00001840, 0xfc00ffff, "x,b"}, ! 385: { "mfsp", 0x000004a0, 0xffff1fe0, "S,t"}, ! 386: { "mfctl", 0x000008a0, 0xfc1fffe0, "b,t"}, ! 387: { "sync", 0x00000400, 0xffffffff, ""}, ! 388: { "prober", 0x04001180, 0xfc003fe0, "(B),x,t"}, ! 389: { "proberi", 0x04003180, 0xfc003fe0, "(B),5,t"}, ! 390: { "probew", 0x040011c0, 0xfc003fe0, "(B),x,t"}, ! 391: { "probewi", 0x040031c0, 0xfc003fe0, "(B),5,t"}, ! 392: { "lpa", 0x04001340, 0xfc003fc0, "Zx(B),t"}, ! 393: { "lha", 0x04001300, 0xfc003fc0, "Zx(B),t"}, ! 394: { "pdtlb", 0x04001200, 0xfc003fdf, "Zx(B)"}, ! 395: { "pitlb", 0x04000200, 0xfc001fdf, "Zx(S,b)"}, ! 396: { "pdtlbe", 0x04001240, 0xfc003fdf, "Zx(B)"}, ! 397: { "pitlbe", 0x04000240, 0xfc003fdf, "Zx(B)"}, ! 398: { "idtlba", 0x04001040, 0xfc003fff, "x,(B)"}, ! 399: { "iitlba", 0x04000040, 0xfc001fff, "x,(S,b)"}, ! 400: { "idtlbp", 0x04001000, 0xfc003fff, "x,(B)"}, ! 401: { "iitlbp", 0x04000000, 0xfc001fff, "x,(S,b)"}, ! 402: { "pdc", 0x04001380, 0xfc003fdf, "Zx(B)"}, ! 403: { "fdc", 0x04001280, 0xfc003fdf, "Zx(B)"}, ! 404: { "fic", 0x04000280, 0xfc001fdf, "Zx(S,b)"}, ! 405: { "fdce", 0x040012c0, 0xfc003fdf, "Zx(B)"}, ! 406: { "fice", 0x040002c0, 0xfc001fdf, "Zx(S,b)"}, ! 407: { "diag", 0x14000000, 0xfc000000, "D"}, ! 408: { "gfw", 0x04001680, 0xfc003fdf, "Zx(B)"}, /* variant of fdc */ ! 409: { "gfr", 0x04001a80, 0xfc003fdf, "Zx(B)"}, /* variant of fdc */ ! 410: ! 411: /* Floating Point Coprocessor Instructions */ ! 412: ! 413: { "fldwx", 0x24000000, 0xfc001f80, "cx(B),v"}, /* PJH: v used to be t */ ! 414: /* and 0xfc001f80 used to be 0xfc001fc0 */ ! 415: { "flddx", 0x2c000000, 0xfc001fc0, "cx(B),t"}, ! 416: { "fstwx", 0x24000200, 0xfc001fc0, "cv,x(B)"}, /* PJH: v used to be t */ ! 417: { "fstdx", 0x2c000200, 0xfc001bc0, "3t,x(B)"}, /* #41317 was "clt,x(B)" */ ! 418: { "fldws", 0x24001000, 0xfc001fc0, "C5(B),v"}, /* PJH: v used to be t */ ! 419: { "fldds", 0x2c001000, 0xfc001fc0, "C5(B),t"}, ! 420: { "fstws", 0x24001200, 0xfc001bc0, "lv,5(B)"}, /* #41317 */ ! 421: { "fstds", 0x2c001200, 0xfc001bc0, "lt,5(B)"}, /* #41317 */ ! 422: { "fadd", 0x30000600, 0xf400e720, "FE,X,v"}, /* PJH: operands were "Fb,x,t" */ ! 423: { "fsub", 0x30002600, 0xf400e720, "FE,X,v"}, /* PJH: operands were "Fb,x,t" */ ! 424: { "fmpy", 0x30004600, 0xf400e720, "FE,X,v"}, /* PJH: operands were "Fb,x,t" */ ! 425: { "fdiv", 0x30006600, 0xf400e720, "FE,X,v"}, /* PJH: operands were "Fb,x,t" */ ! 426: { "fsqrt", 0x30008000, 0xf41fe720, "FE,v"}, /* PJH: operands were "Fb,t" */ ! 427: { "fabs", 0x30006000, 0xf41fe720, "FE,v"}, /* PJH: operands were "Fb,t" */ ! 428: { "frem", 0x30008600, 0xf400e720, "FE,X,v"}, /* PJH: operands were "Fb,x,t" */ ! 429: { "frnd", 0x3000a000, 0xf41fe720, "FE,v"}, /* PJH: operands were "Fb,t" */ ! 430: { "fcpy", 0x30004000, 0xf41fe720, "FE,v"}, /* PJH: operands were "Fb,t" */ ! 431: { "fcnvff", 0x30000200, 0xf41f8720, "FGE,v"}, /* PJH: operands were "FGb,t" */ ! 432: { "fcnvxf", 0x30008200, 0xf41f8720, "FGE,v"}, /* PJH: operands were "FGb,t" */ ! 433: { "fcnvfx", 0x30010200, 0xf41f8720, "FGE,v"}, /* PJH: operands were "FGb,t" */ ! 434: { "fcnvfxt", 0x30018200, 0xf41f8720, "FGE,v"}, /* PJH: operands were "FGb,t" */ ! 435: { "fcmp", 0x30000400, 0xf400e760, "FME,X"}, /* PJH: operands were "FMb,x" */ ! 436: { "ftest", 0x30002420, 0xffffffff, ""}, ! 437: ! 438: /* PA-89 only instructions */ ! 439: ! 440: { "xmpyu", 0x38004700, 0xfc00e720, "FE,X,v"}, ! 441: { "fmpyadd", 0x18000000, 0xfc000000, "H4,6,7,9,8"}, ! 442: { "fmpysub", 0x98000000, 0xfc000000, "H4,6,7,9,8"}, ! 443: ! 444: /* Assist Instructions */ ! 445: ! 446: /* { "spop0", 0x10000000, 0xfc000600, ",f,On", NORMAL}, */ ! 447: /* { "spop1", 0x10000200, 0xfc000600, ",f,ont", NORMAL}, */ ! 448: /* { "spop2", 0x10000400, 0xfc000600, ",f,1nb", NORMAL}, */ ! 449: /* { "spop3", 0x10000600, 0xfc000600, ",f,0nx,b", NORMAL}, */ ! 450: /* { "copr", 0x30000000, 0xfc000000, ",u,2n", NORMAL}, */ ! 451: { "spop0", 0x10000000, 0xfc000600, ",f,Oy", NORMAL}, ! 452: { "spop1", 0x10000200, 0xfc000600, ",f,oyt", NORMAL}, ! 453: { "spop2", 0x10000400, 0xfc000600, ",f,1yb", NORMAL}, ! 454: { "spop3", 0x10000600, 0xfc000600, ",f,0yx,b", NORMAL}, ! 455: { "copr", 0x30000000, 0xfc000000, ",u,2y", NORMAL}, ! 456: { "cldwx", 0x24000000, 0xfc001e00, ",u,Zx(B),t"}, ! 457: { "clddx", 0x2c000000, 0xfc001e00, ",u,Zx(B),t"}, ! 458: { "cstwx", 0x24000200, 0xfc001a00, ",u,3t,x(B)"}, /* #41317 */ ! 459: { "cstdx", 0x2c000200, 0xfc001200, ",u,3t,x(B)"}, /* #41317 */ ! 460: { "cldws", 0x24001000, 0xfc001e00, ",u,Z5(B),t"}, ! 461: { "cldds", 0x2c001000, 0xfc001e00, ",u,Z5(B),t"}, ! 462: { "cstws", 0x24001200, 0xfc001e00, ",u,Zt,5(B)"}, ! 463: { "cstds", 0x2c001200, 0xfc001a00, ",u,3t,5(B)"}, /* #41317 */ ! 464: { "mtsar", 0x01601840, 0xffe0ffff, "x"}, ! 465: ! 466: /* ! 467: * This pseudo-instruction must be at the end so otool will dissassemble using ! 468: * it over a bl. ! 469: */ ! 470: ! 471: /* Gets translated to BL,n W,b (NeXT procedure call) and */ ! 472: /* creates a relocation entry for @ .. USV */ ! 473: ! 474: { "jbsr", 0xe8000000, 0xfc00e000, "n@,b,W", NORMAL}, ! 475: }; ! 476: ! 477: #define NUMOPCODES ((sizeof pa_opcodes)/(sizeof pa_opcodes[0])) ! 478: ! 479: #endif /* HPPA_OPCODE_INCLUDED */ ! 480: ! 481: /* end hppa-opcode.h */
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