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1.1 ! root 1: /* i386-opcode.h -- Intel 80386 opcode table ! 2: Copyright (C) 1989, Free Software Foundation. ! 3: ! 4: This file is part of GAS, the GNU Assembler. ! 5: ! 6: GAS is free software; you can redistribute it and/or modify ! 7: it under the terms of the GNU General Public License as published by ! 8: the Free Software Foundation; either version 1, or (at your option) ! 9: any later version. ! 10: ! 11: GAS is distributed in the hope that it will be useful, ! 12: but WITHOUT ANY WARRANTY; without even the implied warranty of ! 13: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ! 14: GNU General Public License for more details. ! 15: ! 16: You should have received a copy of the GNU General Public License ! 17: along with GAS; see the file COPYING. If not, write to ! 18: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ ! 19: ! 20: static const template i386_optab[] = { ! 21: ! 22: #define _ None ! 23: /* move instructions */ ! 24: { "mov", 2, 0xa0, _, DW|NoModrm, Disp32, Acc, 0 }, ! 25: { "mov", 2, 0x88, _, DW|Modrm, Reg, Reg|Mem, 0 }, ! 26: { "mov", 2, 0xb0, _, ShortFormW, Imm, Reg, 0 }, ! 27: { "mov", 2, 0xc6, _, W|Modrm, Imm, Reg|Mem, 0 }, ! 28: #ifdef NeXT /* bug fix for "movw %ds,64(%edx)" */ ! 29: { "mov", 2, 0x8c, _, D|Modrm, SReg3|SReg2, Reg16|Mem, 0 }, ! 30: #else ! 31: { "mov", 2, 0x8c, _, D|Modrm, SReg3|SReg2, Reg16|Mem16, 0 }, ! 32: #endif ! 33: /* move to/from control debug registers */ ! 34: { "mov", 2, 0x0f20, _, D|Modrm, Control, Reg32, 0}, ! 35: { "mov", 2, 0x0f21, _, D|Modrm, Debug, Reg32, 0}, ! 36: #ifndef STRICT_i586 ! 37: /* The i586 doesn't have test registers - so this is ifdef'ed out */ ! 38: { "mov", 2, 0x0f24, _, D|Modrm, Test, Reg32, 0}, ! 39: #endif /* !defined(STRICT_i586) */ ! 40: ! 41: /* move with sign extend */ ! 42: /* "movsbl" & "movsbw" must not be unified into "movsb" to avoid ! 43: conflict with the "movs" string move instruction. Thus, ! 44: {"movsb", 2, 0x0fbe, _, ReverseRegRegmem|Modrm, Reg8|Mem, Reg16|Reg32, 0}, ! 45: is not kosher; we must seperate the two instructions. */ ! 46: {"movsbl", 2, 0x0fbe, _, ReverseRegRegmem|Modrm, Reg8|Mem, Reg32, 0}, ! 47: {"movsbw", 2, 0x0fbe, _, ReverseRegRegmem|Modrm, Reg8|Mem, Reg16, 0}, ! 48: {"movswl", 2, 0x0fbf, _, ReverseRegRegmem|Modrm, Reg16|Mem, Reg32, 0}, ! 49: ! 50: /* move with zero extend */ ! 51: {"movzb", 2, 0x0fb6, _, ReverseRegRegmem|Modrm, Reg8|Mem, Reg16|Reg32, 0}, ! 52: {"movzwl", 2, 0x0fb7, _, ReverseRegRegmem|Modrm, Reg16|Mem, Reg32, 0}, ! 53: ! 54: /* push instructions */ ! 55: {"push", 1, 0x50, _, ShortForm, WordReg,0,0 }, ! 56: {"push", 1, 0xff, 0x6, Modrm, WordReg|WordMem, 0, 0 }, ! 57: {"push", 1, 0x6a, _, NoModrm, Imm8S, 0, 0}, ! 58: {"push", 1, 0x68, _, NoModrm, Imm32, 0, 0}, ! 59: {"push", 1, 0x06, _, Seg2ShortForm, SReg2,0,0 }, ! 60: {"push", 1, 0x0fa0, _, Seg3ShortForm, SReg3,0,0 }, ! 61: /* push all */ ! 62: {"pusha", 0, 0x60, _, NoModrm, 0, 0, 0 }, ! 63: ! 64: /* pop instructions */ ! 65: {"pop", 1, 0x58, _, ShortForm, WordReg,0,0 }, ! 66: {"pop", 1, 0x8f, 0x0, Modrm, WordReg|WordMem, 0, 0 }, ! 67: #define POP_SEG_SHORT 0x7 ! 68: {"pop", 1, 0x07, _, Seg2ShortForm, SReg2,0,0 }, ! 69: {"pop", 1, 0x0fa1, _, Seg3ShortForm, SReg3,0,0 }, ! 70: /* pop all */ ! 71: {"popa", 0, 0x61, _, NoModrm, 0, 0, 0 }, ! 72: ! 73: /* xchg exchange instructions ! 74: xchg commutes: we allow both operand orders */ ! 75: {"xchg", 2, 0x90, _, ShortForm, WordReg, Acc, 0 }, ! 76: {"xchg", 2, 0x90, _, ShortForm, Acc, WordReg, 0 }, ! 77: {"xchg", 2, 0x86, _, W|Modrm, Reg, Reg|Mem, 0 }, ! 78: {"xchg", 2, 0x86, _, W|Modrm, Reg|Mem, Reg, 0 }, ! 79: ! 80: /* in/out from ports */ ! 81: {"in", 2, 0xe4, _, W|NoModrm, Imm8, Acc, 0 }, ! 82: {"in", 2, 0xec, _, W|NoModrm, InOutPortReg, Acc, 0 }, ! 83: {"out", 2, 0xe6, _, W|NoModrm, Acc, Imm8, 0 }, ! 84: {"out", 2, 0xee, _, W|NoModrm, Acc, InOutPortReg, 0 }, ! 85: ! 86: /* load effective address */ ! 87: {"lea", 2, 0x8d, _, Modrm, WordMem, WordReg, 0 }, ! 88: ! 89: /* load segment registers from memory */ ! 90: {"lds", 2, 0xc5, _, Modrm, Mem, Reg32, 0}, ! 91: {"les", 2, 0xc4, _, Modrm, Mem, Reg32, 0}, ! 92: {"lfs", 2, 0x0fb4, _, Modrm, Mem, Reg32, 0}, ! 93: {"lgs", 2, 0x0fb5, _, Modrm, Mem, Reg32, 0}, ! 94: {"lss", 2, 0x0fb2, _, Modrm, Mem, Reg32, 0}, ! 95: ! 96: /* flags register instructions */ ! 97: {"clc", 0, 0xf8, _, NoModrm, 0, 0, 0}, ! 98: {"cld", 0, 0xfc, _, NoModrm, 0, 0, 0}, ! 99: {"cli", 0, 0xfa, _, NoModrm, 0, 0, 0}, ! 100: {"clts", 0, 0x0f06, _, NoModrm, 0, 0, 0}, ! 101: {"cmc", 0, 0xf5, _, NoModrm, 0, 0, 0}, ! 102: {"lahf", 0, 0x9f, _, NoModrm, 0, 0, 0}, ! 103: {"sahf", 0, 0x9e, _, NoModrm, 0, 0, 0}, ! 104: {"pushf", 0, 0x9c, _, NoModrm, 0, 0, 0}, ! 105: {"popf", 0, 0x9d, _, NoModrm, 0, 0, 0}, ! 106: {"stc", 0, 0xf9, _, NoModrm, 0, 0, 0}, ! 107: {"std", 0, 0xfd, _, NoModrm, 0, 0, 0}, ! 108: {"sti", 0, 0xfb, _, NoModrm, 0, 0, 0}, ! 109: ! 110: {"add", 2, 0x0, _, DW|Modrm, Reg, Reg|Mem, 0}, ! 111: {"add", 2, 0x83, 0, Modrm, Imm8S, WordReg|WordMem, 0}, ! 112: {"add", 2, 0x4, _, W|NoModrm, Imm, Acc, 0}, ! 113: {"add", 2, 0x80, 0, W|Modrm, Imm, Reg|Mem, 0}, ! 114: ! 115: {"inc", 1, 0x40, _, ShortForm, WordReg, 0, 0}, ! 116: {"inc", 1, 0xfe, 0, W|Modrm, Reg|Mem, 0, 0}, ! 117: ! 118: {"sub", 2, 0x28, _, DW|Modrm, Reg, Reg|Mem, 0}, ! 119: {"sub", 2, 0x83, 5, Modrm, Imm8S, WordReg|WordMem, 0}, ! 120: {"sub", 2, 0x2c, _, W|NoModrm, Imm, Acc, 0}, ! 121: {"sub", 2, 0x80, 5, W|Modrm, Imm, Reg|Mem, 0}, ! 122: ! 123: {"dec", 1, 0x48, _, ShortForm, WordReg, 0, 0}, ! 124: {"dec", 1, 0xfe, 1, W|Modrm, Reg|Mem, 0, 0}, ! 125: ! 126: {"sbb", 2, 0x18, _, DW|Modrm, Reg, Reg|Mem, 0}, ! 127: {"sbb", 2, 0x83, 3, Modrm, Imm8S, WordReg|WordMem, 0}, ! 128: {"sbb", 2, 0x1c, _, W|NoModrm, Imm, Acc, 0}, ! 129: {"sbb", 2, 0x80, 3, W|Modrm, Imm, Reg|Mem, 0}, ! 130: ! 131: {"cmp", 2, 0x38, _, DW|Modrm, Reg, Reg|Mem, 0}, ! 132: {"cmp", 2, 0x83, 7, Modrm, Imm8S, WordReg|WordMem, 0}, ! 133: {"cmp", 2, 0x3c, _, W|NoModrm, Imm, Acc, 0}, ! 134: {"cmp", 2, 0x80, 7, W|Modrm, Imm, Reg|Mem, 0}, ! 135: ! 136: {"test", 2, 0x84, _, W|Modrm, Reg|Mem, Reg, 0}, ! 137: {"test", 2, 0x84, _, W|Modrm, Reg, Reg|Mem, 0}, ! 138: {"test", 2, 0xa8, _, W|NoModrm, Imm, Acc, 0}, ! 139: {"test", 2, 0xf6, 0, W|Modrm, Imm, Reg|Mem, 0}, ! 140: ! 141: {"and", 2, 0x20, _, DW|Modrm, Reg, Reg|Mem, 0}, ! 142: {"and", 2, 0x83, 4, Modrm, Imm8S, WordReg|WordMem, 0}, ! 143: {"and", 2, 0x24, _, W|NoModrm, Imm, Acc, 0}, ! 144: {"and", 2, 0x80, 4, W|Modrm, Imm, Reg|Mem, 0}, ! 145: ! 146: {"or", 2, 0x08, _, DW|Modrm, Reg, Reg|Mem, 0}, ! 147: {"or", 2, 0x83, 1, Modrm, Imm8S, WordReg|WordMem, 0}, ! 148: {"or", 2, 0x0c, _, W|NoModrm, Imm, Acc, 0}, ! 149: {"or", 2, 0x80, 1, W|Modrm, Imm, Reg|Mem, 0}, ! 150: ! 151: {"xor", 2, 0x30, _, DW|Modrm, Reg, Reg|Mem, 0}, ! 152: {"xor", 2, 0x83, 6, Modrm, Imm8S, WordReg|WordMem, 0}, ! 153: {"xor", 2, 0x34, _, W|NoModrm, Imm, Acc, 0}, ! 154: {"xor", 2, 0x80, 6, W|Modrm, Imm, Reg|Mem, 0}, ! 155: ! 156: {"adc", 2, 0x10, _, DW|Modrm, Reg, Reg|Mem, 0}, ! 157: {"adc", 2, 0x83, 2, Modrm, Imm8S, WordReg|WordMem, 0}, ! 158: {"adc", 2, 0x14, _, W|NoModrm, Imm, Acc, 0}, ! 159: {"adc", 2, 0x80, 2, W|Modrm, Imm, Reg|Mem, 0}, ! 160: ! 161: {"neg", 1, 0xf6, 3, W|Modrm, Reg|Mem, 0, 0}, ! 162: {"not", 1, 0xf6, 2, W|Modrm, Reg|Mem, 0, 0}, ! 163: ! 164: {"aaa", 0, 0x37, _, NoModrm, 0, 0, 0}, ! 165: {"aas", 0, 0x3f, _, NoModrm, 0, 0, 0}, ! 166: {"daa", 0, 0x27, _, NoModrm, 0, 0, 0}, ! 167: {"das", 0, 0x2f, _, NoModrm, 0, 0, 0}, ! 168: {"aad", 0, 0xd50a, _, NoModrm, 0, 0, 0}, ! 169: {"aam", 0, 0xd40a, _, NoModrm, 0, 0, 0}, ! 170: ! 171: /* conversion insns */ ! 172: /* conversion: intel naming */ ! 173: {"cbw", 0, 0x6698, _, NoModrm, 0, 0, 0}, ! 174: {"cwd", 0, 0x6699, _, NoModrm, 0, 0, 0}, ! 175: {"cwde", 0, 0x98, _, NoModrm, 0, 0, 0}, ! 176: {"cdq", 0, 0x99, _, NoModrm, 0, 0, 0}, ! 177: /* att naming */ ! 178: {"cbtw", 0, 0x6698, _, NoModrm, 0, 0, 0}, ! 179: {"cwtl", 0, 0x98, _, NoModrm, 0, 0, 0}, ! 180: {"cwtd", 0, 0x6699, _, NoModrm, 0, 0, 0}, ! 181: {"cltd", 0, 0x99, _, NoModrm, 0, 0, 0}, ! 182: ! 183: /* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are ! 184: expanding 64-bit multiplies, and *cannot* be selected to accomplish ! 185: 'imul %ebx, %eax' (opcode 0x0faf must be used in this case) ! 186: These multiplies can only be selected with single opearnd forms. */ ! 187: {"mul", 1, 0xf6, 4, W|Modrm, Reg|Mem, 0, 0}, ! 188: {"imul", 1, 0xf6, 5, W|Modrm, Reg|Mem, 0, 0}, ! 189: ! 190: ! 191: ! 192: ! 193: /* imulKludge here is needed to reverse the i.rm.reg & i.rm.regmem fields. ! 194: These instructions are exceptions: 'imul $2, %eax, %ecx' would put ! 195: '%eax' in the reg field and '%ecx' in the regmem field if we did not ! 196: switch them. */ ! 197: {"imul", 2, 0x0faf, _, Modrm|ReverseRegRegmem, WordReg|Mem, WordReg, 0}, ! 198: {"imul", 3, 0x6b, _, Modrm|ReverseRegRegmem, Imm8S, WordReg|Mem, WordReg}, ! 199: {"imul", 3, 0x69, _, Modrm|ReverseRegRegmem, Imm16|Imm32, WordReg|Mem, WordReg}, ! 200: /* ! 201: imul with 2 operands mimicks imul with 3 by puting register both ! 202: in i.rm.reg & i.rm.regmem fields ! 203: */ ! 204: {"imul", 2, 0x6b, _, Modrm|imulKludge, Imm8S, WordReg, 0}, ! 205: {"imul", 2, 0x69, _, Modrm|imulKludge, Imm16|Imm32, WordReg, 0}, ! 206: {"div", 1, 0xf6, 6, W|Modrm, Reg|Mem, 0, 0}, ! 207: {"div", 2, 0xf6, 6, W|Modrm, Reg|Mem, Acc, 0}, ! 208: {"idiv", 1, 0xf6, 7, W|Modrm, Reg|Mem, 0, 0}, ! 209: {"idiv", 2, 0xf6, 7, W|Modrm, Reg|Mem, Acc, 0}, ! 210: ! 211: {"rol", 2, 0xd0, 0, W|Modrm, Imm1, Reg|Mem, 0}, ! 212: {"rol", 2, 0xc0, 0, W|Modrm, Imm8, Reg|Mem, 0}, ! 213: {"rol", 2, 0xd2, 0, W|Modrm, ShiftCount, Reg|Mem, 0}, ! 214: {"rol", 1, 0xd0, 0, W|Modrm, Reg|Mem, 0, 0}, ! 215: ! 216: {"ror", 2, 0xd0, 1, W|Modrm, Imm1, Reg|Mem, 0}, ! 217: {"ror", 2, 0xc0, 1, W|Modrm, Imm8, Reg|Mem, 0}, ! 218: {"ror", 2, 0xd2, 1, W|Modrm, ShiftCount, Reg|Mem, 0}, ! 219: {"ror", 1, 0xd0, 1, W|Modrm, Reg|Mem, 0, 0}, ! 220: ! 221: {"rcl", 2, 0xd0, 2, W|Modrm, Imm1, Reg|Mem, 0}, ! 222: {"rcl", 2, 0xc0, 2, W|Modrm, Imm8, Reg|Mem, 0}, ! 223: {"rcl", 2, 0xd2, 2, W|Modrm, ShiftCount, Reg|Mem, 0}, ! 224: {"rcl", 1, 0xd0, 2, W|Modrm, Reg|Mem, 0, 0}, ! 225: ! 226: {"rcr", 2, 0xd0, 3, W|Modrm, Imm1, Reg|Mem, 0}, ! 227: {"rcr", 2, 0xc0, 3, W|Modrm, Imm8, Reg|Mem, 0}, ! 228: {"rcr", 2, 0xd2, 3, W|Modrm, ShiftCount, Reg|Mem, 0}, ! 229: {"rcr", 1, 0xd0, 3, W|Modrm, Reg|Mem, 0, 0}, ! 230: ! 231: {"sal", 2, 0xd0, 4, W|Modrm, Imm1, Reg|Mem, 0}, ! 232: {"sal", 2, 0xc0, 4, W|Modrm, Imm8, Reg|Mem, 0}, ! 233: {"sal", 2, 0xd2, 4, W|Modrm, ShiftCount, Reg|Mem, 0}, ! 234: {"sal", 1, 0xd0, 4, W|Modrm, Reg|Mem, 0, 0}, ! 235: {"shl", 2, 0xd0, 4, W|Modrm, Imm1, Reg|Mem, 0}, ! 236: {"shl", 2, 0xc0, 4, W|Modrm, Imm8, Reg|Mem, 0}, ! 237: {"shl", 2, 0xd2, 4, W|Modrm, ShiftCount, Reg|Mem, 0}, ! 238: {"shl", 1, 0xd0, 4, W|Modrm, Reg|Mem, 0, 0}, ! 239: ! 240: {"shld", 3, 0x0fa4, _, Modrm, Imm8, WordReg, WordReg|Mem}, ! 241: {"shld", 2, 0x0fa5, _, Modrm, WordReg, WordReg|Mem}, ! 242: {"shld", 3, 0x0fa5, _, Modrm, ShiftCount, WordReg, WordReg|Mem}, ! 243: ! 244: {"shr", 2, 0xd0, 5, W|Modrm, Imm1, Reg|Mem, 0}, ! 245: {"shr", 2, 0xc0, 5, W|Modrm, Imm8, Reg|Mem, 0}, ! 246: {"shr", 2, 0xd2, 5, W|Modrm, ShiftCount, Reg|Mem, 0}, ! 247: {"shr", 1, 0xd0, 5, W|Modrm, Reg|Mem, 0, 0}, ! 248: ! 249: {"shrd", 3, 0x0fac, _, Modrm, Imm8, WordReg, WordReg|Mem}, ! 250: {"shrd", 2, 0x0fad, _, Modrm, WordReg, WordReg|Mem}, ! 251: {"shrd", 3, 0x0fad, _, Modrm, ShiftCount, WordReg, WordReg|Mem}, ! 252: ! 253: {"sar", 2, 0xd0, 7, W|Modrm, Imm1, Reg|Mem, 0}, ! 254: {"sar", 2, 0xc0, 7, W|Modrm, Imm8, Reg|Mem, 0}, ! 255: {"sar", 2, 0xd2, 7, W|Modrm, ShiftCount, Reg|Mem, 0}, ! 256: {"sar", 1, 0xd0, 7, W|Modrm, Reg|Mem, 0, 0}, ! 257: ! 258: /* control transfer instructions */ ! 259: #define CALL_PC_RELATIVE 0xe8 ! 260: {"call", 1, 0xe8, _, JumpDword, Disp32, 0, 0}, ! 261: {"call", 1, 0xff, 2, Modrm, WordReg|WordMem|JumpAbsolute, 0, 0}, ! 262: #define CALL_FAR_IMMEDIATE 0x9a ! 263: {"lcall", 2, 0x9a, _, JumpInterSegment, Imm16, Imm32, 0}, ! 264: {"lcall", 1, 0xff, 3, Modrm, WordMem, 0, 0}, ! 265: ! 266: #define JUMP_PC_RELATIVE 0xeb ! 267: {"jmp", 1, 0xeb, _, Jump, Disp, 0, 0}, ! 268: {"jmp", 1, 0xff, 4, Modrm, Reg32|WordMem|JumpAbsolute, 0, 0}, ! 269: #define JUMP_FAR_IMMEDIATE 0xea ! 270: {"ljmp", 2, 0xea, _, JumpInterSegment, Imm16, Imm32, 0}, ! 271: {"ljmp", 1, 0xff, 5, Modrm, WordMem, 0, 0}, ! 272: ! 273: {"ret", 0, 0xc3, _, NoModrm, 0, 0, 0}, ! 274: {"ret", 1, 0xc2, _, NoModrm, Imm16, 0, 0}, ! 275: {"lret", 0, 0xcb, _, NoModrm, 0, 0, 0}, ! 276: {"lret", 1, 0xca, _, NoModrm, Imm16, 0, 0}, ! 277: {"enter", 2, 0xc8, _, NoModrm, Imm16, Imm8, 0}, ! 278: {"leave", 0, 0xc9, _, NoModrm, 0, 0, 0}, ! 279: ! 280: /* conditional jumps */ ! 281: {"jo", 1, 0x70, _, Jump, Disp, 0, 0}, ! 282: ! 283: {"jno", 1, 0x71, _, Jump, Disp, 0, 0}, ! 284: ! 285: {"jb", 1, 0x72, _, Jump, Disp, 0, 0}, ! 286: {"jc", 1, 0x72, _, Jump, Disp, 0, 0}, ! 287: {"jnae", 1, 0x72, _, Jump, Disp, 0, 0}, ! 288: ! 289: {"jnb", 1, 0x73, _, Jump, Disp, 0, 0}, ! 290: {"jnc", 1, 0x73, _, Jump, Disp, 0, 0}, ! 291: {"jae", 1, 0x73, _, Jump, Disp, 0, 0}, ! 292: ! 293: {"je", 1, 0x74, _, Jump, Disp, 0, 0}, ! 294: {"jz", 1, 0x74, _, Jump, Disp, 0, 0}, ! 295: ! 296: {"jne", 1, 0x75, _, Jump, Disp, 0, 0}, ! 297: {"jnz", 1, 0x75, _, Jump, Disp, 0, 0}, ! 298: ! 299: {"jbe", 1, 0x76, _, Jump, Disp, 0, 0}, ! 300: {"jna", 1, 0x76, _, Jump, Disp, 0, 0}, ! 301: ! 302: {"jnbe", 1, 0x77, _, Jump, Disp, 0, 0}, ! 303: {"ja", 1, 0x77, _, Jump, Disp, 0, 0}, ! 304: ! 305: {"js", 1, 0x78, _, Jump, Disp, 0, 0}, ! 306: ! 307: {"jns", 1, 0x79, _, Jump, Disp, 0, 0}, ! 308: ! 309: {"jp", 1, 0x7a, _, Jump, Disp, 0, 0}, ! 310: {"jpe", 1, 0x7a, _, Jump, Disp, 0, 0}, ! 311: ! 312: {"jnp", 1, 0x7b, _, Jump, Disp, 0, 0}, ! 313: {"jpo", 1, 0x7b, _, Jump, Disp, 0, 0}, ! 314: ! 315: {"jl", 1, 0x7c, _, Jump, Disp, 0, 0}, ! 316: {"jnge", 1, 0x7c, _, Jump, Disp, 0, 0}, ! 317: ! 318: {"jnl", 1, 0x7d, _, Jump, Disp, 0, 0}, ! 319: {"jge", 1, 0x7d, _, Jump, Disp, 0, 0}, ! 320: ! 321: {"jle", 1, 0x7e, _, Jump, Disp, 0, 0}, ! 322: {"jng", 1, 0x7e, _, Jump, Disp, 0, 0}, ! 323: ! 324: {"jnle", 1, 0x7f, _, Jump, Disp, 0, 0}, ! 325: {"jg", 1, 0x7f, _, Jump, Disp, 0, 0}, ! 326: ! 327: /* these turn into pseudo operations when disp is larger than 8 bits */ ! 328: #define IS_JUMP_ON_CX_ZERO(o) \ ! 329: (o == 0x67e3) ! 330: #define IS_JUMP_ON_ECX_ZERO(o) \ ! 331: (o == 0xe3) ! 332: ! 333: {"jcxz", 1, 0x67e3, _, JumpByte, Disp, 0, 0}, ! 334: {"jecxz", 1, 0xe3, _, JumpByte, Disp, 0, 0}, ! 335: ! 336: #define IS_LOOP_ECX_TIMES(o) \ ! 337: (o == 0xe2 || o == 0xe1 || o == 0xe0) ! 338: ! 339: {"loop", 1, 0xe2, _, JumpByte, Disp, 0, 0}, ! 340: ! 341: {"loopz", 1, 0xe1, _, JumpByte, Disp, 0, 0}, ! 342: {"loope", 1, 0xe1, _, JumpByte, Disp, 0, 0}, ! 343: ! 344: {"loopnz", 1, 0xe0, _, JumpByte, Disp, 0, 0}, ! 345: {"loopne", 1, 0xe0, _, JumpByte, Disp, 0, 0}, ! 346: ! 347: /* set byte on flag instructions */ ! 348: {"seto", 1, 0x0f90, 0, Modrm, Reg8|Mem, 0, 0}, ! 349: ! 350: {"setno", 1, 0x0f91, 0, Modrm, Reg8|Mem, 0, 0}, ! 351: ! 352: {"setb", 1, 0x0f92, 0, Modrm, Reg8|Mem, 0, 0}, ! 353: {"setnae", 1, 0x0f92, 0, Modrm, Reg8|Mem, 0, 0}, ! 354: ! 355: {"setnb", 1, 0x0f93, 0, Modrm, Reg8|Mem, 0, 0}, ! 356: {"setae", 1, 0x0f93, 0, Modrm, Reg8|Mem, 0, 0}, ! 357: {"setnc", 1, 0x0f93, 0, Modrm, Reg8|Mem, 0, 0}, ! 358: ! 359: {"sete", 1, 0x0f94, 0, Modrm, Reg8|Mem, 0, 0}, ! 360: {"setz", 1, 0x0f94, 0, Modrm, Reg8|Mem, 0, 0}, ! 361: ! 362: {"setne", 1, 0x0f95, 0, Modrm, Reg8|Mem, 0, 0}, ! 363: {"setnz", 1, 0x0f95, 0, Modrm, Reg8|Mem, 0, 0}, ! 364: ! 365: {"setbe", 1, 0x0f96, 0, Modrm, Reg8|Mem, 0, 0}, ! 366: {"setna", 1, 0x0f96, 0, Modrm, Reg8|Mem, 0, 0}, ! 367: ! 368: {"setnbe", 1, 0x0f97, 0, Modrm, Reg8|Mem, 0, 0}, ! 369: {"seta", 1, 0x0f97, 0, Modrm, Reg8|Mem, 0, 0}, ! 370: ! 371: {"sets", 1, 0x0f98, 0, Modrm, Reg8|Mem, 0, 0}, ! 372: ! 373: {"setns", 1, 0x0f99, 0, Modrm, Reg8|Mem, 0, 0}, ! 374: ! 375: {"setp", 1, 0x0f9a, 0, Modrm, Reg8|Mem, 0, 0}, ! 376: {"setpe", 1, 0x0f9a, 0, Modrm, Reg8|Mem, 0, 0}, ! 377: ! 378: {"setnp", 1, 0x0f9b, 0, Modrm, Reg8|Mem, 0, 0}, ! 379: {"setpo", 1, 0x0f9b, 0, Modrm, Reg8|Mem, 0, 0}, ! 380: ! 381: {"setl", 1, 0x0f9c, 0, Modrm, Reg8|Mem, 0, 0}, ! 382: {"setnge", 1, 0x0f9c, 0, Modrm, Reg8|Mem, 0, 0}, ! 383: ! 384: {"setnl", 1, 0x0f9d, 0, Modrm, Reg8|Mem, 0, 0}, ! 385: {"setge", 1, 0x0f9d, 0, Modrm, Reg8|Mem, 0, 0}, ! 386: ! 387: {"setle", 1, 0x0f9e, 0, Modrm, Reg8|Mem, 0, 0}, ! 388: {"setng", 1, 0x0f9e, 0, Modrm, Reg8|Mem, 0, 0}, ! 389: ! 390: {"setnle", 1, 0x0f9f, 0, Modrm, Reg8|Mem, 0, 0}, ! 391: {"setg", 1, 0x0f9f, 0, Modrm, Reg8|Mem, 0, 0}, ! 392: ! 393: #define IS_STRING_INSTRUCTION(o) \ ! 394: ((o) == 0xa6 || (o) == 0x6c || (o) == 0x6e || (o) == 0x6e || \ ! 395: (o) == 0xac || (o) == 0xa4 || (o) == 0xae || (o) == 0xaa || \ ! 396: (o) == 0xd7) ! 397: ! 398: /* string manipulation */ ! 399: {"cmps", 0, 0xa6, _, W|NoModrm, 0, 0, 0}, ! 400: #ifdef NeXT ! 401: #define CMPS_OPCODE 0xa6 ! 402: {"cmps", 2, 0xa6, _, W, BaseIndex|Mem8, BaseIndex|Mem8, 0}, ! 403: #endif /* NeXT */ ! 404: {"ins", 0, 0x6c, _, W|NoModrm, 0, 0, 0}, ! 405: {"outs", 0, 0x6e, _, W|NoModrm, 0, 0, 0}, ! 406: {"lods", 0, 0xac, _, W|NoModrm, 0, 0, 0}, ! 407: #ifdef NeXT ! 408: #define LODS_OPCODE 0xac ! 409: {"lods", 2, 0xac, _, W, BaseIndex|Mem8, Acc, 0}, ! 410: #endif /* NeXT */ ! 411: {"movs", 0, 0xa4, _, W|NoModrm, 0, 0, 0}, ! 412: #ifdef NeXT ! 413: #define MOVS_OPCODE 0xa4 ! 414: {"movs", 2, 0xa4, _, W, BaseIndex|Mem8, BaseIndex|Mem8, 0}, ! 415: #endif /* NeXT */ ! 416: {"scas", 0, 0xae, _, W|NoModrm, 0, 0, 0}, ! 417: #ifdef NeXT ! 418: #define SCAS_OPCODE 0xae ! 419: {"scas", 2, 0xae, _, W, Acc, BaseIndex|Mem8, 0}, ! 420: #endif /* NeXT */ ! 421: {"stos", 0, 0xaa, _, W|NoModrm, 0, 0, 0}, ! 422: #ifdef NeXT ! 423: #define STOS_OPCODE 0xaa ! 424: {"stos", 2, 0xaa, _, W, Acc, BaseIndex|Mem8, 0}, ! 425: #endif /* NeXT */ ! 426: {"xlat", 0, 0xd7, _, NoModrm, 0, 0, 0}, ! 427: ! 428: /* bit manipulation */ ! 429: {"bsf", 2, 0x0fbc, _, Modrm|ReverseRegRegmem, Reg|Mem, Reg, 0}, ! 430: {"bsr", 2, 0x0fbd, _, Modrm|ReverseRegRegmem, Reg|Mem, Reg, 0}, ! 431: {"bt", 2, 0x0fa3, _, Modrm, Reg, Reg|Mem, 0}, ! 432: {"bt", 2, 0x0fba, 4, Modrm, Imm8, Reg|Mem, 0}, ! 433: {"btc", 2, 0x0fbb, _, Modrm, Reg, Reg|Mem, 0}, ! 434: {"btc", 2, 0x0fba, 7, Modrm, Imm8, Reg|Mem, 0}, ! 435: {"btr", 2, 0x0fb3, _, Modrm, Reg, Reg|Mem, 0}, ! 436: {"btr", 2, 0x0fba, 6, Modrm, Imm8, Reg|Mem, 0}, ! 437: {"bts", 2, 0x0fab, _, Modrm, Reg, Reg|Mem, 0}, ! 438: {"bts", 2, 0x0fba, 5, Modrm, Imm8, Reg|Mem, 0}, ! 439: ! 440: /* interrupts & op. sys insns */ ! 441: /* See i386.c for conversion of 'int $3' into the special int 3 insn. */ ! 442: #define INT_OPCODE 0xcd ! 443: #define INT3_OPCODE 0xcc ! 444: {"int", 1, 0xcd, _, NoModrm, Imm8, 0, 0}, ! 445: {"int3", 0, 0xcc, _, NoModrm, 0, 0, 0}, ! 446: {"into", 0, 0xce, _, NoModrm, 0, 0, 0}, ! 447: {"iret", 0, 0xcf, _, NoModrm, 0, 0, 0}, ! 448: ! 449: {"boundl", 2, 0x62, _, Modrm, Mem, Reg32, 0}, ! 450: {"boundw", 2, 0x62, _, Modrm, Mem, Reg16, 0}, ! 451: ! 452: {"hlt", 0, 0xf4, _, NoModrm, 0, 0, 0}, ! 453: {"wait", 0, 0x9b, _, NoModrm, 0, 0, 0}, ! 454: /* nop is actually 'xchgl %eax, %eax' */ ! 455: {"nop", 0, 0x90, _, NoModrm, 0, 0, 0}, ! 456: ! 457: /* protection control */ ! 458: {"arpl", 2, 0x63, _, Modrm, Reg16, Reg16|Mem, 0}, ! 459: {"lar", 2, 0x0f02, _, Modrm|ReverseRegRegmem, WordReg|Mem, WordReg, 0}, ! 460: {"lgdt", 1, 0x0f01, 2, Modrm, Mem, 0, 0}, ! 461: {"lidt", 1, 0x0f01, 3, Modrm, Mem, 0, 0}, ! 462: {"lldt", 1, 0x0f00, 2, Modrm, WordReg|Mem, 0, 0}, ! 463: {"lmsw", 1, 0x0f01, 6, Modrm, WordReg|Mem, 0, 0}, ! 464: {"lsl", 2, 0x0f03, _, Modrm|ReverseRegRegmem, WordReg|Mem, WordReg, 0}, ! 465: {"ltr", 1, 0x0f00, 3, Modrm, WordReg|Mem, 0, 0}, ! 466: ! 467: {"sgdt", 1, 0x0f01, 0, Modrm, Mem, 0, 0}, ! 468: {"sidt", 1, 0x0f01, 1, Modrm, Mem, 0, 0}, ! 469: {"sldt", 1, 0x0f00, 0, Modrm, WordReg|Mem, 0, 0}, ! 470: {"smsw", 1, 0x0f01, 4, Modrm, WordReg|Mem, 0, 0}, ! 471: {"str", 1, 0x0f00, 1, Modrm, Reg16|Mem, 0, 0}, ! 472: ! 473: {"verr", 1, 0x0f00, 4, Modrm, WordReg|Mem, 0, 0}, ! 474: {"verw", 1, 0x0f00, 5, Modrm, WordReg|Mem, 0, 0}, ! 475: ! 476: #if defined(i486) || defined (i586) ! 477: #define BSWAP_OPCODE 0x0fc8 ! 478: {"bswap", 1, 0x0fc8, _, NoModrm, Reg32, 0, 0, "4" }, ! 479: {"xadd", 2, 0x0fc0, _, W| Modrm, Reg, Reg|Mem, 0, "4" }, ! 480: {"cmpxchg", 2, 0x0fa6, _, W| Modrm, Reg, Reg|Mem, 0, "4" }, ! 481: {"invd", 0, 0x0f08, _, NoModrm, 0, 0, 0, "4" }, ! 482: {"invlpg", 1, 0x0f01, 7, Modrm, Mem, 0, 0, "4" }, ! 483: {"wbinvd", 0, 0x0f09, _, NoModrm, 0, 0, 0, "4" }, ! 484: #endif /* defined (i486) || defined (i586) */ ! 485: ! 486: #ifdef i586 ! 487: /* cmpxchg8b - here Mem32 means 32 bit pointer to a 64bit entity */ ! 488: {"cmpxchg8b", 1, 0x0fc7, _, Modrm, Mem32, 0, 0, "5" }, ! 489: {"cpuid", 0, 0x0fa2, _, NoModrm, 0, 0, 0, "5" }, ! 490: {"rdtsc", 0, 0x0f31, _, NoModrm, 0, 0, 0, "5" }, ! 491: {"rdmsr", 0, 0x0f32, _, NoModrm, 0, 0, 0, "5" }, ! 492: {"wrmsr", 0, 0x0f30, _, NoModrm, 0, 0, 0, "5" }, ! 493: {"rsm", 0, 0x0faa, _, NoModrm, 0, 0, 0, "5" }, ! 494: #endif /* i586 */ ! 495: ! 496: /* floating point instructions */ ! 497: ! 498: /* load */ ! 499: {"fld", 1, 0xd9c0, _, ShortForm, FloatReg, 0, 0}, /* register */ ! 500: {"flds", 1, 0xd9, 0, Modrm, Mem, 0, 0}, /* %st0 <-- mem float */ ! 501: {"fildl", 1, 0xdb, 0, Modrm, Mem, 0, 0}, /* %st0 <-- mem word */ ! 502: {"fldl", 1, 0xdd, 0, Modrm, Mem, 0, 0}, /* %st0 <-- mem double */ ! 503: {"fldl", 1, 0xd9c0, _, ShortForm, FloatReg, 0, 0}, /* register */ ! 504: {"filds", 1, 0xdf, 0, Modrm, Mem, 0, 0}, /* %st0 <-- mem dword */ ! 505: {"fildq", 1, 0xdf, 5, Modrm, Mem, 0, 0}, /* %st0 <-- mem qword */ ! 506: {"fldt", 1, 0xdb, 5, Modrm, Mem, 0, 0}, /* %st0 <-- mem efloat */ ! 507: {"fbld", 1, 0xdf, 4, Modrm, Mem, 0, 0}, /* %st0 <-- mem bcd */ ! 508: ! 509: /* store (no pop) */ ! 510: {"fst", 1, 0xddd0, _, ShortForm, FloatReg, 0, 0}, /* register */ ! 511: {"fsts", 1, 0xd9, 2, Modrm, Mem, 0, 0}, /* %st0 --> mem float */ ! 512: {"fistl", 1, 0xdb, 2, Modrm, Mem, 0, 0}, /* %st0 --> mem dword */ ! 513: {"fstl", 1, 0xdd, 2, Modrm, Mem, 0, 0}, /* %st0 --> mem double */ ! 514: {"fstl", 1, 0xddd0, _, ShortForm, FloatReg, 0, 0}, /* register */ ! 515: {"fists", 1, 0xdf, 2, Modrm, Mem, 0, 0}, /* %st0 --> mem word */ ! 516: ! 517: /* store (with pop) */ ! 518: {"fstp", 1, 0xddd8, _, ShortForm, FloatReg, 0, 0}, /* register */ ! 519: {"fstps", 1, 0xd9, 3, Modrm, Mem, 0, 0}, /* %st0 --> mem float */ ! 520: {"fistpl", 1, 0xdb, 3, Modrm, Mem, 0, 0}, /* %st0 --> mem word */ ! 521: {"fstpl", 1, 0xdd, 3, Modrm, Mem, 0, 0}, /* %st0 --> mem double */ ! 522: {"fstpl", 1, 0xddd8, _, ShortForm, FloatReg, 0, 0}, /* register */ ! 523: {"fistps", 1, 0xdf, 3, Modrm, Mem, 0, 0}, /* %st0 --> mem dword */ ! 524: {"fistpq", 1, 0xdf, 7, Modrm, Mem, 0, 0}, /* %st0 --> mem qword */ ! 525: {"fstpt", 1, 0xdb, 7, Modrm, Mem, 0, 0}, /* %st0 --> mem efloat */ ! 526: {"fbstp", 1, 0xdf, 6, Modrm, Mem, 0, 0}, /* %st0 --> mem bcd */ ! 527: ! 528: /* exchange %st<n> with %st0 */ ! 529: {"fxch", 1, 0xd9c8, _, ShortForm, FloatReg, 0, 0}, ! 530: ! 531: /* comparison (without pop) */ ! 532: {"fcom", 0, 0xd8d1, _, ShortForm, 0, 0, 0}, /* compare %st0, %st1 */ ! 533: {"fcom", 1, 0xd8d0, _, ShortForm, FloatReg, 0, 0}, ! 534: {"fcoms", 1, 0xd8, 2, Modrm, Mem, 0, 0}, /* compare %st0, mem float */ ! 535: {"ficoml", 1, 0xda, 2, Modrm, Mem, 0, 0}, /* compare %st0, mem word */ ! 536: {"fcoml", 1, 0xdc, 2, Modrm, Mem, 0, 0}, /* compare %st0, mem double */ ! 537: {"fcoml", 1, 0xd8d0, _, ShortForm, FloatReg, 0, 0}, ! 538: {"ficoms", 1, 0xde, 2, Modrm, Mem, 0, 0}, /* compare %st0, mem dword */ ! 539: ! 540: /* comparison (with pop) */ ! 541: {"fcomp", 0, 0xd8d9, _, ShortForm, 0, 0, 0}, /* compare %st0, %st1 & pop */ ! 542: {"fcomp", 1, 0xd8d8, _, ShortForm, FloatReg, 0, 0}, ! 543: {"fcomps", 1, 0xd8, 3, Modrm, Mem, 0, 0}, /* compare %st0, mem float */ ! 544: {"ficompl", 1, 0xda, 3, Modrm, Mem, 0, 0}, /* compare %st0, mem word */ ! 545: {"fcompl", 1, 0xdc, 3, Modrm, Mem, 0, 0}, /* compare %st0, mem double */ ! 546: {"fcompl", 1, 0xd8d8, _, ShortForm, FloatReg, 0, 0}, ! 547: {"ficomps", 1, 0xde, 3, Modrm, Mem, 0, 0}, /* compare %st0, mem dword */ ! 548: {"fcompp", 0, 0xded9, _, NoModrm, 0, 0, 0}, /* compare %st0, %st1 & pop twice */ ! 549: ! 550: /* unordered comparison (with pop) */ ! 551: {"fucom", 1, 0xdde0, _, ShortForm, FloatReg, 0, 0}, ! 552: {"fucom", 0, 0xdde1, _, NoModrm, 0, 0, 0}, /* alias for fucom %st(1) */ ! 553: {"fucomp", 1, 0xdde8, _, ShortForm, FloatReg, 0, 0}, ! 554: {"fucomp", 0, 0xdde9, _, NoModrm, 0, 0, 0}, /* alias for fucomp %st(1) */ ! 555: {"fucompp", 0, 0xdae9, _, NoModrm, 0, 0, 0}, /* ucompare %st0, %st1 & pop twice */ ! 556: ! 557: {"ftst", 0, 0xd9e4, _, NoModrm, 0, 0, 0}, /* test %st0 */ ! 558: {"fxam", 0, 0xd9e5, _, NoModrm, 0, 0, 0}, /* examine %st0 */ ! 559: ! 560: /* load constants into %st0 */ ! 561: {"fld1", 0, 0xd9e8, _, NoModrm, 0, 0, 0}, /* %st0 <-- 1.0 */ ! 562: {"fldl2t", 0, 0xd9e9, _, NoModrm, 0, 0, 0}, /* %st0 <-- log2(10) */ ! 563: {"fldl2e", 0, 0xd9ea, _, NoModrm, 0, 0, 0}, /* %st0 <-- log2(e) */ ! 564: {"fldpi", 0, 0xd9eb, _, NoModrm, 0, 0, 0}, /* %st0 <-- pi */ ! 565: {"fldlg2", 0, 0xd9ec, _, NoModrm, 0, 0, 0}, /* %st0 <-- log10(2) */ ! 566: {"fldln2", 0, 0xd9ed, _, NoModrm, 0, 0, 0}, /* %st0 <-- ln(2) */ ! 567: {"fldz", 0, 0xd9ee, _, NoModrm, 0, 0, 0}, /* %st0 <-- 0.0 */ ! 568: ! 569: /* arithmetic */ ! 570: ! 571: /* add */ ! 572: {"fadd", 1, 0xd8c0, _, ShortForm, FloatReg, 0, 0}, ! 573: {"fadd", 2, 0xd8c0, _, ShortForm|FloatD, FloatReg, FloatAcc, 0}, ! 574: {"fadd", 0, 0xdcc1, _, NoModrm, 0, 0, 0}, /* alias for fadd %st, %st(1) */ ! 575: {"faddp", 1, 0xdec0, _, ShortForm, FloatReg, 0, 0}, ! 576: {"faddp", 2, 0xdec0, _, ShortForm, FloatAcc, FloatReg, 0}, ! 577: {"faddp", 0, 0xdec1, _, NoModrm, 0, 0, 0}, /* alias for faddp %st, %st(1) */ ! 578: {"fadds", 1, 0xd8, 0, Modrm, Mem, 0, 0}, ! 579: {"fiaddl", 1, 0xda, 0, Modrm, Mem, 0, 0}, ! 580: {"faddl", 1, 0xdc, 0, Modrm, Mem, 0, 0}, ! 581: {"fiadds", 1, 0xde, 0, Modrm, Mem, 0, 0}, ! 582: ! 583: /* sub */ ! 584: /* Note: intel has decided that certain of these operations are reversed ! 585: in assembler syntax. */ ! 586: {"fsub", 1, 0xd8e0, _, ShortForm, FloatReg, 0, 0}, ! 587: {"fsub", 2, 0xd8e0, _, ShortForm, FloatReg, FloatAcc, 0}, ! 588: #ifdef NON_BROKEN_OPCODES ! 589: {"fsub", 2, 0xdce8, _, ShortForm, FloatAcc, FloatReg, 0}, ! 590: #else ! 591: {"fsub", 2, 0xdce0, _, ShortForm, FloatAcc, FloatReg, 0}, ! 592: #endif ! 593: {"fsub", 0, 0xdce1, _, NoModrm, 0, 0, 0}, ! 594: {"fsubp", 1, 0xdee0, _, ShortForm, FloatReg, 0, 0}, ! 595: {"fsubp", 2, 0xdee0, _, ShortForm, FloatReg, FloatAcc, 0}, ! 596: #ifdef NON_BROKEN_OPCODES ! 597: {"fsubp", 2, 0xdee8, _, ShortForm, FloatAcc, FloatReg, 0}, ! 598: #else ! 599: {"fsubp", 2, 0xdee0, _, ShortForm, FloatAcc, FloatReg, 0}, ! 600: #endif ! 601: {"fsubp", 0, 0xdee1, _, NoModrm, 0, 0, 0}, ! 602: {"fsubs", 1, 0xd8, 4, Modrm, Mem, 0, 0}, ! 603: {"fisubl", 1, 0xda, 4, Modrm, Mem, 0, 0}, ! 604: {"fsubl", 1, 0xdc, 4, Modrm, Mem, 0, 0}, ! 605: {"fisubs", 1, 0xde, 4, Modrm, Mem, 0, 0}, ! 606: ! 607: /* sub reverse */ ! 608: {"fsubr", 1, 0xd8e8, _, ShortForm, FloatReg, 0, 0}, ! 609: {"fsubr", 2, 0xd8e8, _, ShortForm, FloatReg, FloatAcc, 0}, ! 610: #ifdef NON_BROKEN_OPCODES ! 611: {"fsubr", 2, 0xdce0, _, ShortForm, FloatAcc, FloatReg, 0}, ! 612: #else ! 613: {"fsubr", 2, 0xdce8, _, ShortForm, FloatAcc, FloatReg, 0}, ! 614: #endif ! 615: {"fsubr", 0, 0xdce9, _, NoModrm, 0, 0, 0}, ! 616: {"fsubrp", 1, 0xdae8, _, ShortForm, FloatReg, 0, 0}, ! 617: {"fsubrp", 2, 0xdae8, _, ShortForm, FloatReg, FloatAcc, 0}, ! 618: #ifdef NON_BROKEN_OPCODES ! 619: {"fsubrp", 2, 0xdee0, _, ShortForm, FloatAcc, FloatReg, 0}, ! 620: #else ! 621: {"fsubrp", 2, 0xdee8, _, ShortForm, FloatAcc, FloatReg, 0}, ! 622: #endif ! 623: {"fsubrp", 0, 0xdee9, _, NoModrm, 0, 0, 0}, ! 624: {"fsubrs", 1, 0xd8, 5, Modrm, Mem, 0, 0}, ! 625: {"fisubrl", 1, 0xda, 5, Modrm, Mem, 0, 0}, ! 626: {"fsubrl", 1, 0xdc, 5, Modrm, Mem, 0, 0}, ! 627: {"fisubrs", 1, 0xde, 5, Modrm, Mem, 0, 0}, ! 628: ! 629: /* mul */ ! 630: {"fmul", 1, 0xd8c8, _, ShortForm, FloatReg, 0, 0}, ! 631: {"fmul", 2, 0xd8c8, _, ShortForm|FloatD, FloatReg, FloatAcc, 0}, ! 632: {"fmul", 0, 0xdcc9, _, NoModrm, 0, 0, 0}, ! 633: {"fmulp", 1, 0xdec8, _, ShortForm, FloatReg, 0, 0}, ! 634: {"fmulp", 2, 0xdec8, _, ShortForm, FloatAcc, FloatReg, 0}, ! 635: {"fmulp", 0, 0xdec9, _, NoModrm, 0, 0, 0}, ! 636: {"fmuls", 1, 0xd8, 1, Modrm, Mem, 0, 0}, ! 637: {"fimull", 1, 0xda, 1, Modrm, Mem, 0, 0}, ! 638: {"fmull", 1, 0xdc, 1, Modrm, Mem, 0, 0}, ! 639: {"fimuls", 1, 0xde, 1, Modrm, Mem, 0, 0}, ! 640: ! 641: /* div */ ! 642: /* Note: intel has decided that certain of these operations are reversed ! 643: in assembler syntax. */ ! 644: {"fdiv", 1, 0xd8f0, _, ShortForm, FloatReg, 0, 0}, ! 645: {"fdiv", 2, 0xd8f0, _, ShortForm, FloatReg, FloatAcc, 0}, ! 646: #ifdef NON_BROKEN_OPCODES ! 647: {"fdiv", 2, 0xdcf8, _, ShortForm, FloatAcc, FloatReg, 0}, ! 648: #else ! 649: {"fdiv", 2, 0xdcf0, _, ShortForm, FloatAcc, FloatReg, 0}, ! 650: #endif ! 651: {"fdiv", 0, 0xdcf1, _, NoModrm, 0, 0, 0}, ! 652: {"fdivp", 1, 0xdef0, _, ShortForm, FloatReg, 0, 0}, ! 653: {"fdivp", 2, 0xdef0, _, ShortForm, FloatReg, FloatAcc, 0}, ! 654: #ifdef NON_BROKEN_OPCODES ! 655: {"fdivp", 2, 0xdef8, _, ShortForm, FloatAcc, FloatReg, 0}, ! 656: #else ! 657: {"fdivp", 2, 0xdef0, _, ShortForm, FloatAcc, FloatReg, 0}, ! 658: #endif ! 659: {"fdivp", 0, 0xdef1, _, NoModrm, 0, 0, 0}, ! 660: {"fdivs", 1, 0xd8, 6, Modrm, Mem, 0, 0}, ! 661: {"fidivl", 1, 0xda, 6, Modrm, Mem, 0, 0}, ! 662: {"fdivl", 1, 0xdc, 6, Modrm, Mem, 0, 0}, ! 663: {"fidivs", 1, 0xde, 6, Modrm, Mem, 0, 0}, ! 664: ! 665: /* div reverse */ ! 666: {"fdivr", 1, 0xd8f8, _, ShortForm, FloatReg, 0, 0}, ! 667: {"fdivr", 2, 0xd8f8, _, ShortForm, FloatReg, FloatAcc, 0}, ! 668: #ifdef NON_BROKEN_OPCODES ! 669: {"fdivr", 2, 0xdcf0, _, ShortForm, FloatAcc, FloatReg, 0}, ! 670: #else ! 671: {"fdivr", 2, 0xdcf8, _, ShortForm, FloatAcc, FloatReg, 0}, ! 672: #endif ! 673: {"fdivr", 0, 0xdcf9, _, NoModrm, 0, 0, 0}, ! 674: {"fdivrp", 1, 0xdef8, _, ShortForm, FloatReg, 0, 0}, ! 675: {"fdivrp", 2, 0xdef8, _, ShortForm, FloatReg, FloatAcc, 0}, ! 676: #ifdef NON_BROKEN_OPCODES ! 677: {"fdivrp", 2, 0xdef0, _, ShortForm, FloatAcc, FloatReg, 0}, ! 678: #else ! 679: {"fdivrp", 2, 0xdef8, _, ShortForm, FloatAcc, FloatReg, 0}, ! 680: #endif ! 681: {"fdivrp", 0, 0xdef9, _, NoModrm, 0, 0, 0}, ! 682: {"fdivrs", 1, 0xd8, 7, Modrm, Mem, 0, 0}, ! 683: {"fidivrl", 1, 0xda, 7, Modrm, Mem, 0, 0}, ! 684: {"fdivrl", 1, 0xdc, 7, Modrm, Mem, 0, 0}, ! 685: {"fidivrs", 1, 0xde, 7, Modrm, Mem, 0, 0}, ! 686: ! 687: {"f2xm1", 0, 0xd9f0, _, NoModrm, 0, 0, 0}, ! 688: {"fyl2x", 0, 0xd9f1, _, NoModrm, 0, 0, 0}, ! 689: {"fptan", 0, 0xd9f2, _, NoModrm, 0, 0, 0}, ! 690: {"fpatan", 0, 0xd9f3, _, NoModrm, 0, 0, 0}, ! 691: {"fxtract", 0, 0xd9f4, _, NoModrm, 0, 0, 0}, ! 692: {"fprem1", 0, 0xd9f5, _, NoModrm, 0, 0, 0}, ! 693: {"fdecstp", 0, 0xd9f6, _, NoModrm, 0, 0, 0}, ! 694: {"fincstp", 0, 0xd9f7, _, NoModrm, 0, 0, 0}, ! 695: {"fprem", 0, 0xd9f8, _, NoModrm, 0, 0, 0}, ! 696: {"fyl2xp1", 0, 0xd9f9, _, NoModrm, 0, 0, 0}, ! 697: {"fsqrt", 0, 0xd9fa, _, NoModrm, 0, 0, 0}, ! 698: {"fsincos", 0, 0xd9fb, _, NoModrm, 0, 0, 0}, ! 699: {"frndint", 0, 0xd9fc, _, NoModrm, 0, 0, 0}, ! 700: {"fscale", 0, 0xd9fd, _, NoModrm, 0, 0, 0}, ! 701: {"fsin", 0, 0xd9fe, _, NoModrm, 0, 0, 0}, ! 702: {"fcos", 0, 0xd9ff, _, NoModrm, 0, 0, 0}, ! 703: ! 704: {"fchs", 0, 0xd9e0, _, NoModrm, 0, 0, 0}, ! 705: {"fabs", 0, 0xd9e1, _, NoModrm, 0, 0, 0}, ! 706: ! 707: /* processor control */ ! 708: {"fninit", 0, 0xdbe3, _, NoModrm, 0, 0, 0}, ! 709: {"finit", 0, 0x9bdbe3, _, NoModrm, 0, 0, 0}, ! 710: {"fldcw", 1, 0xd9, 5, Modrm, Mem, 0, 0}, ! 711: {"fnstcw", 1, 0xd9, 7, Modrm, Mem, 0, 0}, ! 712: {"fstcw", 1, 0x9bd9, 7, Modrm, Mem, 0, 0}, ! 713: {"fnstsw", 1, 0xdfe0, _, NoModrm, Acc, 0, 0}, ! 714: {"fnstsw", 1, 0xdd, 7, Modrm, Mem, 0, 0}, ! 715: {"fnstsw", 0, 0xdfe0, _, NoModrm, 0, 0, 0}, ! 716: {"fstsw", 1, 0x9bdfe0, _, NoModrm, Acc, 0, 0}, ! 717: {"fstsw", 1, 0xdd, 7, Modrm, Mem, 0, 0}, ! 718: {"fstsw", 0, 0x9bdfe0, _, NoModrm, 0, 0, 0}, ! 719: {"fnclex", 0, 0xdbe2, _, NoModrm, 0, 0, 0}, ! 720: {"fclex", 0, 0x9bdbe2, _, NoModrm, 0, 0, 0}, ! 721: /* ! 722: We ignore the short format (287) versions of fstenv/fldenv & fsave/frstor ! 723: instructions; i'm not sure how to add them or how they are different. ! 724: My 386/387 book offers no details about this. ! 725: */ ! 726: {"fnstenv", 1, 0xd9, 6, Modrm, Mem, 0, 0}, ! 727: {"fstenv", 1, 0x9bd9, 6, Modrm, Mem, 0, 0}, ! 728: {"fldenv", 1, 0xd9, 4, Modrm, Mem, 0, 0}, ! 729: {"fnsave", 1, 0xdd, 6, Modrm, Mem, 0, 0}, ! 730: {"fsave", 1, 0x9bdd, 6, Modrm, Mem, 0, 0}, ! 731: {"frstor", 1, 0xdd, 4, Modrm, Mem, 0, 0}, ! 732: ! 733: {"ffree", 1, 0xddc0, _, ShortForm, FloatReg, 0, 0}, ! 734: {"fnop", 0, 0xd9d0, _, NoModrm, 0, 0, 0}, ! 735: {"fwait", 0, 0x9b, _, NoModrm, 0, 0, 0}, ! 736: ! 737: /* ! 738: opcode prefixes; we allow them as seperate insns too ! 739: (see prefix table below) ! 740: */ ! 741: {"aword", 0, 0x67, _, NoModrm, 0, 0, 0}, ! 742: {"word", 0, 0x66, _, NoModrm, 0, 0, 0}, ! 743: {"lock", 0, 0xf0, _, NoModrm, 0, 0, 0}, ! 744: {"cs", 0, 0x2e, _, NoModrm, 0, 0, 0}, ! 745: {"ds", 0, 0x3e, _, NoModrm, 0, 0, 0}, ! 746: {"es", 0, 0x26, _, NoModrm, 0, 0, 0}, ! 747: {"fs", 0, 0x64, _, NoModrm, 0, 0, 0}, ! 748: {"gs", 0, 0x65, _, NoModrm, 0, 0, 0}, ! 749: {"ss", 0, 0x36, _, NoModrm, 0, 0, 0}, ! 750: {"rep", 0, 0xf3, _, NoModrm, 0, 0, 0}, ! 751: {"repe", 0, 0xf3, _, NoModrm, 0, 0, 0}, ! 752: {"repz", 0, 0xf3, _, NoModrm, 0, 0, 0}, ! 753: { "repne", 0, 0xf2, _, NoModrm, 0, 0, 0}, ! 754: { "repnz", 0, 0xf2, _, NoModrm, 0, 0, 0}, ! 755: ! 756: {"", 0, 0, 0, 0, 0, 0, 0} /* sentinal */ ! 757: }; ! 758: #undef _ ! 759: ! 760: static const template *i386_optab_end ! 761: = i386_optab + sizeof (i386_optab)/sizeof(i386_optab[0]); ! 762: ! 763: /* 386 register table */ ! 764: ! 765: static const reg_entry i386_regtab[] = { ! 766: /* 8 bit regs */ ! 767: {"al", Reg8|Acc, 0}, {"cl", Reg8|ShiftCount, 1}, {"dl", Reg8, 2}, ! 768: {"bl", Reg8, 3}, ! 769: {"ah", Reg8, 4}, {"ch", Reg8, 5}, {"dh", Reg8, 6}, {"bh", Reg8, 7}, ! 770: /* 16 bit regs */ ! 771: {"ax", Reg16|Acc, 0}, {"cx", Reg16, 1}, {"dx", Reg16|InOutPortReg, 2}, {"bx", Reg16, 3}, ! 772: {"sp", Reg16, 4}, {"bp", Reg16, 5}, {"si", Reg16, 6}, {"di", Reg16, 7}, ! 773: /* 32 bit regs */ ! 774: {"eax", Reg32|Acc, 0}, {"ecx", Reg32, 1}, {"edx", Reg32, 2}, {"ebx", Reg32, 3}, ! 775: {"esp", Reg32, 4}, {"ebp", Reg32, 5}, {"esi", Reg32, 6}, {"edi", Reg32, 7}, ! 776: /* segment registers */ ! 777: {"es", SReg2, 0}, {"cs", SReg2, 1}, {"ss", SReg2, 2}, ! 778: {"ds", SReg2, 3}, {"fs", SReg3, 4}, {"gs", SReg3, 5}, ! 779: /* control registers */ ! 780: {"cr0", Control, 0}, {"cr2", Control, 2}, {"cr3", Control, 3}, ! 781: #ifdef i586 ! 782: {"cr4", Control, 4}, ! 783: #endif /* i586 */ ! 784: /* debug registers */ ! 785: {"db0", Debug, 0}, {"db1", Debug, 1}, {"db2", Debug, 2}, ! 786: {"db3", Debug, 3}, {"db6", Debug, 6}, {"db7", Debug, 7}, ! 787: /* test registers */ ! 788: #ifndef STRICT_i586 ! 789: #if defined(i486) || defined(i586) ! 790: {"tr3", Test, 3}, {"tr4", Test, 4}, {"tr5", Test, 5}, ! 791: #endif /* defined(i486) || defined(i586) */ ! 792: {"tr6", Test, 6}, {"tr7", Test, 7}, ! 793: #endif /* !defined(STRICT_i586) */ ! 794: /* float registers */ ! 795: {"st(0)", FloatReg|FloatAcc, 0}, ! 796: {"st", FloatReg|FloatAcc, 0}, ! 797: {"st(1)", FloatReg, 1}, {"st(2)", FloatReg, 2}, ! 798: {"st(3)", FloatReg, 3}, {"st(4)", FloatReg, 4}, {"st(5)", FloatReg, 5}, ! 799: {"st(6)", FloatReg, 6}, {"st(7)", FloatReg, 7} ! 800: }; ! 801: ! 802: #define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */ ! 803: ! 804: static const reg_entry *i386_regtab_end ! 805: = i386_regtab + sizeof(i386_regtab)/sizeof(i386_regtab[0]); ! 806: ! 807: /* segment stuff */ ! 808: static const seg_entry cs = { "cs", 0x2e }; ! 809: static const seg_entry ds = { "ds", 0x3e }; ! 810: static const seg_entry ss = { "ss", 0x36 }; ! 811: static const seg_entry es = { "es", 0x26 }; ! 812: static const seg_entry fs = { "fs", 0x64 }; ! 813: static const seg_entry gs = { "gs", 0x65 }; ! 814: static const seg_entry null = { "", 0x0 }; ! 815: ! 816: /* ! 817: This table is used to store the default segment register implied by all ! 818: possible memory addressing modes. ! 819: It is indexed by the mode & modrm entries of the modrm byte as follows: ! 820: index = (mode<<3) | modrm; ! 821: */ ! 822: static const seg_entry *one_byte_segment_defaults[] = { ! 823: /* mode 0 */ ! 824: &ds, &ds, &ds, &ds, &null, &ds, &ds, &ds, ! 825: /* mode 1 */ ! 826: &ds, &ds, &ds, &ds, &null, &ss, &ds, &ds, ! 827: /* mode 2 */ ! 828: &ds, &ds, &ds, &ds, &null, &ss, &ds, &ds, ! 829: /* mode 3 --- not a memory reference; never referenced */ ! 830: }; ! 831: ! 832: static const seg_entry *two_byte_segment_defaults[] = { ! 833: /* mode 0 */ ! 834: &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds, ! 835: /* mode 1 */ ! 836: &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds, ! 837: /* mode 2 */ ! 838: &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds, ! 839: /* mode 3 --- not a memory reference; never referenced */ ! 840: }; ! 841: ! 842: static const prefix_entry i386_prefixtab[] = { ! 843: { "addr16", 0x67 }, /* address size prefix ==> 16bit addressing ! 844: * (How is this useful?) */ ! 845: #define WORD_PREFIX_OPCODE 0x66 ! 846: { "data16", 0x66 }, /* operand size prefix */ ! 847: { "lock", 0xf0 }, /* bus lock prefix */ ! 848: { "wait", 0x9b }, /* wait for coprocessor */ ! 849: { "cs", 0x2e }, { "ds", 0x3e }, /* segment overrides ... */ ! 850: { "es", 0x26 }, { "fs", 0x64 }, ! 851: { "gs", 0x65 }, { "ss", 0x36 }, ! 852: /* REPE & REPNE used to detect rep/repne with a non-string instruction */ ! 853: #define REPNE 0xf2 ! 854: #define REPE 0xf3 ! 855: { "rep", 0xf3 }, { "repe", 0xf3 }, /* repeat string instructions */ ! 856: { "repne", 0xf2 } ! 857: }; ! 858: ! 859: static const prefix_entry *i386_prefixtab_end ! 860: = i386_prefixtab + sizeof(i386_prefixtab)/sizeof(i386_prefixtab[0]);
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