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1.1 ! root 1: /* ! 2: * The 88110 implemention assumes signed immediate mode. ! 3: */ ! 4: ! 5: /* m88k-opcode.h -- Instruction information for the 88100 ! 6: Copyright (C) 1989 Free Software Foundation, Inc. ! 7: ! 8: This file is not yet part of GAS, the GNU Assembler. ! 9: ! 10: GAS is free software; you can redistribute it and/or modify ! 11: it under the terms of the GNU General Public License as published by ! 12: the Free Software Foundation; either version 1, or (at your option) ! 13: any later version. ! 14: ! 15: GAS is distributed in the hope that it will be useful, ! 16: but WITHOUT ANY WARRANTY; without even the implied warranty of ! 17: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ! 18: GNU General Public License for more details. ! 19: ! 20: You should have received a copy of the GNU General Public License ! 21: along with GAS; see the file COPYING. If not, write to ! 22: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ ! 23: ! 24: /* macros for shifting operand fields */ ! 25: ! 26: #define UEXT(src,off,wid) ((((unsigned int)src)>>off) & ((1<<wid) - 1)) ! 27: #define SEXT(src,off,wid) (((((int)src)<<(32-(off+wid))) >>(32-wid)) ) ! 28: ! 29: /* operand decriptor structure */ ! 30: ! 31: struct opspec { ! 32: unsigned int offset:5; ! 33: unsigned int width:6; ! 34: unsigned int type:5; ! 35: }; ! 36: ! 37: /* operands types */ ! 38: ! 39: #define NIL 0 /* invalid parameter */ ! 40: #define CNST 1 /* 16-bit constant */ ! 41: #define REG 2 /* register */ ! 42: #define BF 4 /* bit field */ ! 43: #define REGSC 5 /* scaled register */ ! 44: #define CRREG 6 /* control register */ ! 45: #define FCRREG 7 /* floating point control register */ ! 46: #define PCREL 8 /* PC relative (branch offset) */ ! 47: #define CONDMASK 9 /* bcnd mask */ ! 48: #define CMPRSLT 10 /* result of cmp instruction (bb0/1, tb0/1) */ ! 49: #define ROT 11 /* 5 bit value for rotation (rot instruction only)*/ ! 50: #ifdef m88110 ! 51: #define E4ROT 12 /* even multiple of 4 value for pixel rotation */ ! 52: #define EREG 13 /* even register from general register */ ! 53: #define XREG 14 /* register from extended register file */ ! 54: #endif m88110 ! 55: ! 56: /* instruction descriptor structure */ ! 57: ! 58: struct m88k_opcode { ! 59: unsigned int opcode; ! 60: char *name; ! 61: struct opspec op[3]; ! 62: #ifdef NeXT ! 63: long delay_slot; ! 64: #endif ! 65: }; ! 66: ! 67: /* and introducing... the Motorola 88100 instruction set... */ ! 68: ! 69: static const struct m88k_opcode m88k_opcodes[] = { ! 70: ! 71: /* Opcode Mnemonic Op 1 Spec Op 2 Spec Op 3 Spec */ ! 72: ! 73: { 0x70000000, "add", { {21,5,REG}, {16,5,REG}, {0,16,CNST} } }, ! 74: { 0xf4007000, "add", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 75: { 0xf4007200, "add.ci", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 76: { 0xf4007300, "add.cio", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 77: { 0xf4007100, "add.co", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 78: { 0x60000000, "addu", { {21,5,REG}, {16,5,REG}, {0,16,CNST} } }, ! 79: { 0xf4006000, "addu", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 80: { 0xf4006200, "addu.ci", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 81: { 0xf4006300, "addu.cio", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 82: { 0xf4006100, "addu.co", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 83: { 0x40000000, "and", { {21,5,REG}, {16,5,REG}, {0,16,CNST} } }, ! 84: { 0xf4004000, "and", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 85: { 0xf4004400, "and.c", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 86: { 0x44000000, "and.u", { {21,5,REG}, {16,5,REG}, {0,16,CNST} } }, ! 87: { 0xd0000000, "bb0", { {21,5,CMPRSLT}, {16,5,REG}, {0,16,PCREL}} }, ! 88: { 0xd4000000, "bb0.n", { {21,5,CMPRSLT}, {16,5,REG}, {0,16,PCREL}},1}, ! 89: { 0xd8000000, "bb1", { {21,5,CMPRSLT}, {16,5,REG}, {0,16,PCREL}} }, ! 90: { 0xdc000000, "bb1.n", { {21,5,CMPRSLT}, {16,5,REG}, {0,16,PCREL}},1}, ! 91: { 0xe8000000, "bcnd", { {21,5,CONDMASK}, {16,5,REG}, {0,16,PCREL}} }, ! 92: { 0xec000000, "bcnd.n", { {21,5,CONDMASK}, {16,5,REG}, {0,16,PCREL}},1}, ! 93: { 0xc0000000, "br", { {0,26,PCREL}, {0,0,NIL}, {0,0,NIL} } }, ! 94: { 0xc4000000, "br.n", { {0,26,PCREL}, {0,0,NIL}, {0,0,NIL} },1}, ! 95: { 0xc8000000, "bsr", { {0,26,PCREL}, {0,0,NIL}, {0,0,NIL} } }, ! 96: { 0xcc000000, "bsr.n", { {0,26,PCREL}, {0,0,NIL}, {0,0,NIL} },1}, ! 97: { 0XF0008000, "clr", { {21,5,REG}, {16,5,REG}, {0,10,BF} } }, ! 98: { 0XF4008000, "clr", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 99: { 0x7c000000, "cmp", { {21,5,REG}, {16,5,REG}, {0,16,CNST} } }, ! 100: { 0xf4007c00, "cmp", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 101: { 0x78000000, "div", { {21,5,REG}, {16,5,REG}, {0,16,CNST} } }, ! 102: { 0xf4007800, "div", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 103: #ifdef m88110 ! 104: { 0x78000000, "divs", { {21,5,REG}, {16,5,REG}, {0,16,CNST} } }, ! 105: { 0xf4007800, "divs", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 106: #endif m88110 ! 107: { 0x68000000, "divu", { {21,5,REG}, {16,5,REG}, {0,16,CNST} } }, ! 108: { 0xf4006800, "divu", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 109: #ifdef m88110 ! 110: { 0xf4006900, "divu.d", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 111: #endif m88110 ! 112: { 0XF0009000, "ext", { {21,5,REG}, {16,5,REG}, {0,10,BF} } }, ! 113: { 0XF4009000, "ext", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 114: { 0XF0009800, "extu", { {21,5,REG}, {16,5,REG}, {0,10,BF} } }, ! 115: { 0XF4009800, "extu", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 116: { 0X84002AA0, "fadd.ddd", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 117: #ifdef m88110 ! 118: { 0X8400AAA0, "fadd.ddd", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 119: #endif m88110 ! 120: { 0X84002A20, "fadd.dds", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 121: #ifdef m88110 ! 122: { 0X8400AA20, "fadd.dds", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 123: { 0X8400AB20, "fadd.ddx", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 124: #endif m88110 ! 125: { 0X840028A0, "fadd.dsd", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 126: #ifdef m88110 ! 127: { 0X8400A8A0, "fadd.dsd", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 128: #endif m88110 ! 129: { 0X84002820, "fadd.dss", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 130: #ifdef m88110 ! 131: { 0X8400A820, "fadd.dss", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 132: { 0X8400A920, "fadd.dsx", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 133: { 0X8400ACA0, "fadd.dxd", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 134: { 0X8400AC20, "fadd.dxs", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 135: { 0X8400AD20, "fadd.dxx", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 136: #endif m88110 ! 137: { 0X84002A80, "fadd.sdd", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 138: #ifdef m88110 ! 139: { 0X8400AA80, "fadd.sdd", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 140: #endif m88110 ! 141: { 0X84002A00, "fadd.sds", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 142: #ifdef m88110 ! 143: { 0X8400AA00, "fadd.sds", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 144: { 0X8400AB00, "fadd.sdx", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 145: #endif m88110 ! 146: { 0X84002880, "fadd.ssd", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 147: #ifdef m88110 ! 148: { 0X8400A880, "fadd.ssd", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 149: #endif m88110 ! 150: { 0X84002800, "fadd.sss", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 151: #ifdef m88110 ! 152: { 0X8400A800, "fadd.sss", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 153: { 0X8400A900, "fadd.ssx", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 154: { 0X8400AC80, "fadd.sxd", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 155: { 0X8400AC00, "fadd.sxs", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 156: { 0X8400AD00, "fadd.sxx", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 157: { 0X8400AAC0, "fadd.xdd", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 158: { 0X8400AA40, "fadd.xds", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 159: { 0X8400AB40, "fadd.xdx", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 160: { 0X8400A8C0, "fadd.xsd", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 161: { 0X8400A840, "fadd.xss", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 162: { 0X8400A940, "fadd.xsx", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 163: { 0X8400ACC0, "fadd.xxd", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 164: { 0X8400AC40, "fadd.xxs", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 165: { 0X8400AD40, "fadd.xxx", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 166: #endif m88110 ! 167: { 0x84003a80, "fcmp.sdd", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 168: #ifdef m88110 ! 169: { 0X8400BA80, "fcmp.sdd", { {21,5,REG}, {16,5,XREG}, {0,5,XREG} } }, ! 170: #endif m88110 ! 171: { 0x84003a00, "fcmp.sds", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 172: #ifdef m88110 ! 173: { 0X8400BA00, "fcmp.sds", { {21,5,REG}, {16,5,XREG}, {0,5,XREG} } }, ! 174: { 0X8400BB00, "fcmp.sdx", { {21,5,REG}, {16,5,XREG}, {0,5,XREG} } }, ! 175: #endif m88110 ! 176: { 0x84003880, "fcmp.ssd", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 177: #ifdef m88110 ! 178: { 0X8400B880, "fcmp.ssd", { {21,5,REG}, {16,5,XREG}, {0,5,XREG} } }, ! 179: #endif m88110 ! 180: { 0x84003800, "fcmp.sss", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 181: #ifdef m88110 ! 182: { 0X8400B800, "fcmp.sss", { {21,5,REG}, {16,5,XREG}, {0,5,XREG} } }, ! 183: { 0X8400B900, "fcmp.ssx", { {21,5,REG}, {16,5,XREG}, {0,5,XREG} } }, ! 184: { 0X8400BC80, "fcmp.sxd", { {21,5,REG}, {16,5,XREG}, {0,5,XREG} } }, ! 185: { 0X8400BC00, "fcmp.sxs", { {21,5,REG}, {16,5,XREG}, {0,5,XREG} } }, ! 186: { 0X8400BD00, "fcmp.sxx", { {21,5,REG}, {16,5,XREG}, {0,5,XREG} } }, ! 187: { 0X84003AA0, "fcmpu.sdd", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 188: { 0X8400BAA0, "fcmpu.sdd", { {21,5,REG}, {16,5,XREG}, {0,5,XREG} } }, ! 189: { 0X84003A20, "fcmpu.sds", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 190: { 0X8400BA20, "fcmpu.sds", { {21,5,REG}, {16,5,XREG}, {0,5,XREG} } }, ! 191: { 0X8400BB20, "fcmpu.sdx", { {21,5,REG}, {16,5,XREG}, {0,5,XREG} } }, ! 192: { 0X840038A0, "fcmpu.ssd", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 193: { 0X8400B8A0, "fcmpu.ssd", { {21,5,REG}, {16,5,XREG}, {0,5,XREG} } }, ! 194: { 0X84003820, "fcmpu.sss", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 195: { 0X8400B820, "fcmpu.sss", { {21,5,REG}, {16,5,XREG}, {0,5,XREG} } }, ! 196: { 0X8400B920, "fcmpu.ssx", { {21,5,REG}, {16,5,XREG}, {0,5,XREG} } }, ! 197: { 0X8400BCA0, "fcmpu.sxd", { {21,5,REG}, {16,5,XREG}, {0,5,XREG} } }, ! 198: { 0X8400BC20, "fcmpu.sxs", { {21,5,REG}, {16,5,XREG}, {0,5,XREG} } }, ! 199: { 0X8400BD20, "fcmpu.sxx", { {21,5,REG}, {16,5,XREG}, {0,5,XREG} } }, ! 200: { 0X84000820, "fcvt.ds", { {21,5,REG}, {0,5,REG}, {0,0,NIL} } }, ! 201: { 0X84008820, "fcvt.ds", { {21,5,XREG}, {0,5,XREG}, {0,0,NIL} } }, ! 202: { 0X84008920, "fcvt.dx", { {21,5,XREG}, {0,5,XREG}, {0,0,NIL} } }, ! 203: { 0X84000880, "fcvt.sd", { {21,5,REG}, {0,5,REG}, {0,0,NIL} } }, ! 204: { 0X84008880, "fcvt.sd", { {21,5,XREG}, {0,5,XREG}, {0,0,NIL} } }, ! 205: { 0X84008900, "fcvt.sx", { {21,5,XREG}, {0,5,XREG}, {0,0,NIL} } }, ! 206: { 0X840088C0, "fcvt.xd", { {21,5,XREG}, {0,5,XREG}, {0,0,NIL} } }, ! 207: { 0X84008840, "fcvt.xs", { {21,5,XREG}, {0,5,XREG}, {0,0,NIL} } }, ! 208: #endif m88110 ! 209: { 0x840072a0, "fdiv.ddd", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 210: #ifdef m88110 ! 211: { 0x8400f2a0, "fdiv.ddd", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 212: #endif m88110 ! 213: { 0x84007220, "fdiv.dds", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 214: #ifdef m88110 ! 215: { 0x8400f220, "fdiv.dds", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 216: { 0x8400f320, "fdiv.ddx", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 217: #endif m88110 ! 218: { 0x840070a0, "fdiv.dsd", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 219: #ifdef m88110 ! 220: { 0x8400f0a0, "fdiv.dsd", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 221: #endif m88110 ! 222: { 0x84007020, "fdiv.dss", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 223: #ifdef m88110 ! 224: { 0x8400f020, "fdiv.dss", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 225: { 0x8400f120, "fdiv.dsx", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 226: { 0x8400f4a0, "fdiv.dxd", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 227: { 0x8400f420, "fdiv.dxs", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 228: { 0x8400f520, "fdiv.dxx", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 229: #endif m88110 ! 230: { 0x84007280, "fdiv.sdd", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 231: #ifdef m88110 ! 232: { 0x8400f280, "fdiv.sdd", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 233: #endif m88110 ! 234: { 0x84007200, "fdiv.sds", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 235: #ifdef m88110 ! 236: { 0x8400f200, "fdiv.sds", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 237: { 0x8400f300, "fdiv.sdx", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 238: #endif m88110 ! 239: { 0x84007080, "fdiv.ssd", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 240: #ifdef m88110 ! 241: { 0x8400f080, "fdiv.ssd", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 242: #endif m88110 ! 243: { 0X84007000, "fdiv.sss", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 244: #ifdef m88110 ! 245: { 0x8400f000, "fdiv.sss", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 246: { 0x8400f100, "fdiv.ssx", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 247: { 0x8400f480, "fdiv.sxd", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 248: { 0x8400f400, "fdiv.sxs", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 249: { 0x8400f500, "fdiv.sxx", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 250: { 0x8400f2c0, "fdiv.xdd", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 251: { 0x8400f240, "fdiv.xds", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 252: { 0x8400f340, "fdiv.xdx", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 253: { 0x8400f0c0, "fdiv.xsd", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 254: { 0x8400f040, "fdiv.xss", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 255: { 0x8400f140, "fdiv.xsx", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 256: { 0x8400f4c0, "fdiv.xxd", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 257: { 0x8400f440, "fdiv.xxs", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 258: { 0x8400f540, "fdiv.xxx", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 259: #endif m88110 ! 260: { 0XF400EC00, "ff0", { {21,5,REG}, {0,5,REG}, {0,0,NIL} } }, ! 261: { 0XF400E800, "ff1", { {21,5,REG}, {0,5,REG}, {0,0,NIL} } }, ! 262: { 0x80004800, "fldcr", { {21,5,REG}, {5,6,FCRREG}, {0,0,NIL} } }, ! 263: { 0X84002020, "flt.ds", { {21,5,REG}, {0,5,REG}, {0,0,NIL} } }, ! 264: #ifdef m88110 ! 265: { 0X84002220, "flt.ds", { {21,5,XREG}, {0,5,REG}, {0,0,NIL} } }, ! 266: #endif m88110 ! 267: { 0X84002000, "flt.ss", { {21,5,REG}, {0,5,REG}, {0,0,NIL} } }, ! 268: #ifdef m88110 ! 269: { 0X84002200, "flt.ss", { {21,5,XREG}, {0,5,REG}, {0,0,NIL} } }, ! 270: { 0X84002240, "flt.xs", { {21,5,XREG}, {0,5,REG}, {0,0,NIL} } }, ! 271: #endif m88110 ! 272: { 0X840002A0, "fmul.ddd", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 273: #ifdef m88110 ! 274: { 0X840082A0, "fmul.ddd", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 275: #endif m88110 ! 276: { 0X84000220, "fmul.dds", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 277: #ifdef m88110 ! 278: { 0X84008220, "fmul.dds", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 279: { 0X84008320, "fmul.ddx", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 280: #endif m88110 ! 281: { 0X840000A0, "fmul.dsd", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 282: #ifdef m88110 ! 283: { 0X840080A0, "fmul.dsd", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 284: #endif m88110 ! 285: { 0X84000020, "fmul.dss", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 286: #ifdef m88110 ! 287: { 0X84008020, "fmul.dss", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 288: { 0X84008120, "fmul.dsx", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 289: { 0X840084A0, "fmul.dxd", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 290: { 0X84008420, "fmul.dxs", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 291: { 0X84008520, "fmul.dxx", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 292: #endif m88110 ! 293: { 0X84000280, "fmul.sdd", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 294: #ifdef m88110 ! 295: { 0X84008280, "fmul.sdd", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 296: #endif m88110 ! 297: { 0X84000200, "fmul.sds", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 298: #ifdef m88110 ! 299: { 0X84008200, "fmul.sds", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 300: { 0X84008300, "fmul.sdx", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 301: #endif m88110 ! 302: { 0X84000080, "fmul.ssd", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 303: #ifdef m88110 ! 304: { 0X84008080, "fmul.ssd", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 305: #endif m88110 ! 306: { 0X84000000, "fmul.sss", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 307: #ifdef m88110 ! 308: { 0X84008000, "fmul.sss", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 309: { 0X84008100, "fmul.ssx", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 310: { 0X84008480, "fmul.sxd", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 311: { 0X84008400, "fmul.sxs", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 312: { 0X84008500, "fmul.sxx", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 313: { 0X840082C0, "fmul.xdd", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 314: { 0X84008240, "fmul.xds", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 315: { 0X84008340, "fmul.xdx", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 316: { 0X840080C0, "fmul.xsd", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 317: { 0X84008040, "fmul.xss", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 318: { 0X84008140, "fmul.xsx", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 319: { 0X840084C0, "fmul.xxd", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 320: { 0X84008440, "fmul.xxs", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 321: { 0X84008540, "fmul.xxx", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 322: { 0X840078A0, "fsqrt.dd", { {21,5,REG}, {0,5,REG}, {0,0,NIL} } }, ! 323: { 0X8400F8A0, "fsqrt.dd", { {21,5,XREG}, {0,5,XREG}, {0,0,NIL} } }, ! 324: { 0X84007820, "fsqrt.ds", { {21,5,REG}, {0,5,REG}, {0,0,NIL} } }, ! 325: { 0X8400F820, "fsqrt.ds", { {21,5,XREG}, {0,5,XREG}, {0,0,NIL} } }, ! 326: { 0X8400F920, "fsqrt.dx", { {21,5,XREG}, {0,5,XREG}, {0,0,NIL} } }, ! 327: { 0X84007880, "fsqrt.sd", { {21,5,REG}, {0,5,REG}, {0,0,NIL} } }, ! 328: { 0X8400F880, "fsqrt.sd", { {21,5,XREG}, {0,5,XREG}, {0,0,NIL} } }, ! 329: { 0X84007800, "fsqrt.ss", { {21,5,REG}, {0,5,REG}, {0,0,NIL} } }, ! 330: { 0X8400F800, "fsqrt.ss", { {21,5,XREG}, {0,5,XREG}, {0,0,NIL} } }, ! 331: { 0X8400F900, "fsqrt.sx", { {21,5,XREG}, {0,5,XREG}, {0,0,NIL} } }, ! 332: { 0X8400F8C0, "fsqrt.xd", { {21,5,XREG}, {0,5,XREG}, {0,0,NIL} } }, ! 333: { 0X8400F840, "fsqrt.xs", { {21,5,XREG}, {0,5,XREG}, {0,0,NIL} } }, ! 334: { 0X8400F940, "fsqrt.xx", { {21,5,XREG}, {0,5,XREG}, {0,0,NIL} } }, ! 335: #endif m88110 ! 336: { 0x80008800, "fstcr", { {16,5,REG}, {5,6,FCRREG}, {0,0,NIL} } }, ! 337: { 0X840032A0, "fsub.ddd", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 338: #ifdef m88110 ! 339: { 0X8400B2A0, "fsub.ddd", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 340: #endif m88110 ! 341: { 0X84003220, "fsub.dds", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 342: #ifdef m88110 ! 343: { 0X8400B220, "fsub.dds", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 344: { 0X8400B320, "fsub.ddx", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 345: #endif m88110 ! 346: { 0X840030A0, "fsub.dsd", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 347: #ifdef m88110 ! 348: { 0X8400B0A0, "fsub.dsd", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 349: #endif m88110 ! 350: { 0X84003020, "fsub.dss", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 351: #ifdef m88110 ! 352: { 0X8400B020, "fsub.dss", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 353: { 0X8400B120, "fsub.dsx", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 354: { 0X8400B4A0, "fsub.dxd", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 355: { 0X8400B420, "fsub.dxs", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 356: { 0X8400B520, "fsub.dxx", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 357: #endif m88110 ! 358: { 0X84003280, "fsub.sdd", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 359: #ifdef m88110 ! 360: { 0X8400B280, "fsub.sdd", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 361: #endif m88110 ! 362: { 0X84003200, "fsub.sds", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 363: #ifdef m88110 ! 364: { 0X8400B200, "fsub.sds", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 365: { 0X8400B300, "fsub.sdx", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 366: #endif m88110 ! 367: { 0X84003080, "fsub.ssd", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 368: #ifdef m88110 ! 369: { 0X8400B080, "fsub.ssd", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 370: #endif m88110 ! 371: { 0X84003000, "fsub.sss", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 372: #ifdef m88110 ! 373: { 0X8400B000, "fsub.sss", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 374: { 0X8400B100, "fsub.ssx", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 375: { 0X8400B480, "fsub.sxd", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 376: { 0X8400B400, "fsub.sxs", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 377: { 0X8400B500, "fsub.sxx", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 378: { 0X8400B2C0, "fsub.xdd", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 379: { 0X8400B240, "fsub.xds", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 380: { 0X8400B340, "fsub.xdx", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 381: { 0X8400B0C0, "fsub.xsd", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 382: { 0X8400B040, "fsub.xss", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 383: { 0X8400B140, "fsub.xsx", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 384: { 0X8400B4C0, "fsub.xxd", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 385: { 0X8400B440, "fsub.xxs", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 386: { 0X8400B540, "fsub.xxx", { {21,5,XREG}, {16,5,XREG}, {0,5,XREG} } }, ! 387: #endif m88110 ! 388: { 0x8000c800, "fxcr", { {21,5,REG}, {16,5,REG}, {5,6,FCRREG}} }, ! 389: { 0xf400fc01, "illop1", { {0,0,NIL}, {0,0,NIL}, {0,0,NIL} } }, ! 390: { 0xf400fc02, "illop2", { {0,0,NIL}, {0,0,NIL}, {0,0,NIL} } }, ! 391: { 0xf400fc03, "illop3", { {0,0,NIL}, {0,0,NIL}, {0,0,NIL} } }, ! 392: { 0x84004880, "int.sd", { {21,5,REG}, {0,5,REG}, {0,0,NIL} } }, ! 393: #ifdef m88110 ! 394: { 0x8400c880, "int.sd", { {21,5,REG}, {0,5,XREG}, {0,0,NIL} } }, ! 395: #endif m88110 ! 396: { 0x84004800, "int.ss", { {21,5,REG}, {0,5,REG}, {0,0,NIL} } }, ! 397: #ifdef m88110 ! 398: { 0x8400c800, "int.ss", { {21,5,REG}, {0,5,XREG}, {0,0,NIL} } }, ! 399: { 0x8400c900, "int.sx", { {21,5,REG}, {0,5,XREG}, {0,0,NIL} } }, ! 400: #endif m88110 ! 401: { 0xf400c000, "jmp", { {0,5,REG}, {0,0,NIL}, {0,0,NIL} } }, ! 402: { 0xf400c400, "jmp.n", { {0,5,REG}, {0,0,NIL}, {0,0,NIL} },1}, ! 403: { 0xf400c800, "jsr", { {0,5,REG}, {0,0,NIL}, {0,0,NIL} } }, ! 404: { 0xf400cc00, "jsr.n", { {0,5,REG}, {0,0,NIL}, {0,0,NIL} },1}, ! 405: { 0x14000000, "ld", { {21,5,REG}, {16,5,REG}, {0,16,CNST} } }, ! 406: { 0xf4001600, "ld", { {21,5,REG}, {16,5,REG}, {0,5,REGSC} } }, ! 407: { 0xf4001400, "ld", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 408: #ifdef m88110 ! 409: { 0x04000000, "ld", { {21,5,XREG}, {16,5,REG}, {0,16,CNST} } }, ! 410: { 0xf0001600, "ld", { {21,5,XREG}, {16,5,REG}, {0,5,REGSC} } }, ! 411: { 0xf0001400, "ld", { {21,5,XREG}, {16,5,REG}, {0,5,REG} } }, ! 412: #endif m88110 ! 413: { 0x1c000000, "ld.b", { {21,5,REG}, {16,5,REG}, {0,16,CNST} } }, ! 414: { 0xf4001e00, "ld.b", { {21,5,REG}, {16,5,REG}, {0,5,REGSC} } }, ! 415: { 0xf4001c00, "ld.b", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 416: { 0xf4001f00, "ld.b.usr", { {21,5,REG}, {16,5,REG}, {0,5,REGSC} } }, ! 417: { 0xf4001d00, "ld.b.usr", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 418: { 0x0c000000, "ld.bu", { {21,5,REG}, {16,5,REG}, {0,16,CNST} } }, ! 419: { 0xf4000e00, "ld.bu", { {21,5,REG}, {16,5,REG}, {0,5,REGSC} } }, ! 420: { 0xf4000c00, "ld.bu", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 421: { 0xf4000f00, "ld.bu.usr", { {21,5,REG}, {16,5,REG}, {0,5,REGSC} } }, ! 422: { 0xf4000d00, "ld.bu.usr", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 423: { 0x10000000, "ld.d", { {21,5,REG}, {16,5,REG}, {0,16,CNST} } }, ! 424: { 0xf4001200, "ld.d", { {21,5,REG}, {16,5,REG}, {0,5,REGSC} } }, ! 425: { 0xf4001000, "ld.d", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 426: #ifdef m88110 ! 427: { 0x00000000, "ld.d", { {21,5,XREG}, {16,5,REG}, {0,16,CNST} } }, ! 428: { 0xf0001200, "ld.d", { {21,5,XREG}, {16,5,REG}, {0,5,REGSC} } }, ! 429: { 0xf0001000, "ld.d", { {21,5,XREG}, {16,5,REG}, {0,5,REG} } }, ! 430: #endif m88110 ! 431: { 0xf4001300, "ld.d.usr", { {21,5,REG}, {16,5,REG}, {0,5,REGSC} } }, ! 432: #ifdef m88110 ! 433: { 0xf0001300, "ld.d.usr", { {21,5,XREG}, {16,5,REG}, {0,5,REGSC} } }, ! 434: #endif m88110 ! 435: { 0xf4001100, "ld.d.usr", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 436: #ifdef m88110 ! 437: { 0xf0001100, "ld.d.usr", { {21,5,XREG}, {16,5,REG}, {0,5,REG} } }, ! 438: #endif m88110 ! 439: { 0x18000000, "ld.h", { {21,5,REG}, {16,5,REG}, {0,16,CNST} } }, ! 440: { 0xf4001a00, "ld.h", { {21,5,REG}, {16,5,REG}, {0,5,REGSC} } }, ! 441: { 0xf4001800, "ld.h", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 442: { 0xf4001b00, "ld.h.usr", { {21,5,REG}, {16,5,REG}, {0,5,REGSC} } }, ! 443: { 0xf4001900, "ld.h.usr", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 444: { 0x08000000, "ld.hu", { {21,5,REG}, {16,5,REG}, {0,16,CNST} } }, ! 445: { 0xf4000a00, "ld.hu", { {21,5,REG}, {16,5,REG}, {0,5,REGSC} } }, ! 446: { 0xf4000800, "ld.hu", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 447: { 0xf4000b00, "ld.hu.usr", { {21,5,REG}, {16,5,REG}, {0,5,REGSC} } }, ! 448: { 0xf4000900, "ld.hu.usr", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 449: { 0xf4001700, "ld.usr", { {21,5,REG}, {16,5,REG}, {0,5,REGSC} } }, ! 450: #ifdef m88110 ! 451: { 0xf0001700, "ld.usr", { {21,5,XREG}, {16,5,REG}, {0,5,REGSC} } }, ! 452: #endif m88110 ! 453: { 0xf4001500, "ld.usr", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 454: #ifdef m88110 ! 455: { 0xf0001500, "ld.usr", { {21,5,XREG}, {16,5,REG}, {0,5,REG} } }, ! 456: { 0x3c000000, "ld.x", { {21,5,XREG}, {16,5,REG}, {0,16,CNST} } }, ! 457: { 0xf0001a00, "ld.x", { {21,5,XREG}, {16,5,REG}, {0,5,REGSC} } }, ! 458: { 0xf0001800, "ld.x", { {21,5,XREG}, {16,5,REG}, {0,5,REG} } }, ! 459: { 0xf0001b00, "ld.x.usr", { {21,5,XREG}, {16,5,REG}, {0,5,REGSC} } }, ! 460: { 0xf0001900, "ld.x.usr", { {21,5,XREG}, {16,5,REG}, {0,5,REG} } }, ! 461: #endif m88110 ! 462: #ifndef m88110 ! 463: { 0x34000000, "lda", { {21,5,REG}, {16,5,REG}, {0,16,CNST} } }, ! 464: #endif !defined(m88110) ! 465: { 0xf4003600, "lda", { {21,5,REG}, {16,5,REG}, {0,5,REGSC} } }, ! 466: #ifndef m88110 ! 467: { 0xf4003400, "lda", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 468: { 0x3c000000, "lda.b", { {21,5,REG}, {16,5,REG}, {0,16,CNST} } }, ! 469: { 0xf4003e00, "lda.b", { {21,5,REG}, {16,5,REG}, {0,5,REGSC} } }, ! 470: { 0xf4003c00, "lda.b", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 471: { 0x30000000, "lda.d", { {21,5,REG}, {16,5,REG}, {0,16,CNST} } }, ! 472: #endif !defined(m88110) ! 473: { 0xf4003200, "lda.d", { {21,5,REG}, {16,5,REG}, {0,5,REGSC} } }, ! 474: #ifndef m88110 ! 475: { 0xf4003000, "lda.d", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 476: { 0x38000000, "lda.h", { {21,5,REG}, {16,5,REG}, {0,16,CNST} } }, ! 477: #endif !defined(m88110) ! 478: { 0xf4003a00, "lda.h", { {21,5,REG}, {16,5,REG}, {0,5,REGSC} } }, ! 479: #ifndef m88110 ! 480: { 0xf4003800, "lda.h", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 481: #endif !defined(m88110) ! 482: #ifdef m88110 ! 483: { 0xf4003e00, "lda.x", { {21,5,REG}, {16,5,REG}, {0,5,REGSC} } }, ! 484: #endif m88110 ! 485: { 0x80004000, "ldcr", { {21,5,REG}, {5,6,CRREG}, {0,0,NIL} } }, ! 486: { 0XF000A000, "mak", { {21,5,REG}, {16,5,REG}, {0,10,BF} } }, ! 487: { 0XF400A000, "mak", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 488: { 0X48000000, "mask", { {21,5,REG}, {16,5,REG}, {0,16,CNST} } }, ! 489: { 0X4C000000, "mask.u", { {21,5,REG}, {16,5,REG}, {0,16,CNST} } }, ! 490: #ifdef m88110 ! 491: { 0X8400C080, "mov.d", { {21,5,REG}, {0,5,XREG}, {0,0,NIL} } }, ! 492: { 0X84004280, "mov.d", { {21,5,XREG}, {0,5,REG}, {0,0,NIL} } }, ! 493: { 0X8400C000, "mov.s", { {21,5,REG}, {0,5,XREG}, {0,0,NIL} } }, ! 494: { 0X84004200, "mov.s", { {21,5,XREG}, {0,5,REG}, {0,0,NIL} } }, ! 495: { 0X8400C300, "mov", { {21,5,XREG}, {0,5,XREG}, {0,0,NIL} } }, ! 496: #endif m88110 ! 497: { 0x6c000000, "mul", { {21,5,REG}, {16,5,REG}, {0,16,CNST} } }, ! 498: { 0xf4006c00, "mul", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 499: #ifdef m88110 ! 500: { 0xf4006e00, "muls", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 501: { 0x6c000000, "mulu", { {21,5,REG}, {16,5,REG}, {0,16,CNST} } }, ! 502: { 0xf4006c00, "mulu", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 503: { 0xf4006d00, "mulu.d", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 504: #endif m88110 ! 505: { 0x84005080, "nint.sd", { {21,5,REG}, {0,5,REG}, {0,0,NIL} } }, ! 506: #ifdef m88110 ! 507: { 0x8400d080, "nint.sd", { {21,5,REG}, {0,5,XREG}, {0,0,NIL} } }, ! 508: #endif m88110 ! 509: { 0x84005000, "nint.ss", { {21,5,REG}, {0,5,REG}, {0,0,NIL} } }, ! 510: #ifdef m88110 ! 511: { 0x8400d000, "nint.ss", { {21,5,REG}, {0,5,XREG}, {0,0,NIL} } }, ! 512: { 0x8400d100, "nint.sx", { {21,5,REG}, {0,5,XREG}, {0,0,NIL} } }, ! 513: #endif m88110 ! 514: { 0X58000000, "or", { {21,5,REG}, {16,5,REG}, {0,16,CNST} } }, ! 515: { 0xf4005800, "or", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 516: { 0xf4005c00, "or.c", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 517: { 0X5C000000, "or.u", { {21,5,REG}, {16,5,REG}, {0,16,CNST} } }, ! 518: #ifdef m88110 ! 519: { 0x88002060, "padd", { {21,5,EREG}, {16,5,EREG}, {0,5,EREG} } }, ! 520: { 0x88002020, "padd.b", { {21,5,EREG}, {16,5,EREG}, {0,5,EREG} } }, ! 521: { 0x88002040, "padd.h", { {21,5,EREG}, {16,5,EREG}, {0,5,EREG} } }, ! 522: { 0x880021e0, "padds.s", { {21,5,EREG}, {16,5,EREG}, {0,5,EREG} } }, ! 523: { 0x880021a0, "padds.s.b", { {21,5,EREG}, {16,5,EREG}, {0,5,EREG} } }, ! 524: { 0x880021c0, "padds.s.h", { {21,5,EREG}, {16,5,EREG}, {0,5,EREG} } }, ! 525: { 0x880020e0, "padds.u", { {21,5,EREG}, {16,5,EREG}, {0,5,EREG} } }, ! 526: { 0x880020a0, "padds.u.b", { {21,5,EREG}, {16,5,EREG}, {0,5,EREG} } }, ! 527: { 0x880020c0, "padds.u.h", { {21,5,EREG}, {16,5,EREG}, {0,5,EREG} } }, ! 528: { 0x88002160, "padds.us", { {21,5,EREG}, {16,5,EREG}, {0,5,EREG} } }, ! 529: { 0x88002120, "padds.us.b", { {21,5,EREG}, {16,5,EREG}, {0,5,EREG} } }, ! 530: { 0x88002140, "padds.us.h", { {21,5,EREG}, {16,5,EREG}, {0,5,EREG} } }, ! 531: { 0x88003860, "pcmp", { {21,5,REG}, {16,5,EREG}, {0,5,EREG} } }, ! 532: { 0x88000000, "pmul", { {21,5,EREG}, {16,5,EREG}, {0,5,REG} } }, ! 533: { 0x88006260, "ppack.16", { {21,5,EREG}, {16,5,EREG}, {0,5,EREG} } }, ! 534: { 0x88006240, "ppack.16.h", { {21,5,EREG}, {16,5,EREG}, {0,5,EREG} } }, ! 535: { 0x88006460, "ppack.32", { {21,5,EREG}, {16,5,EREG}, {0,5,EREG} } }, ! 536: { 0x88006420, "ppack.32.b", { {21,5,EREG}, {16,5,EREG}, {0,5,EREG} } }, ! 537: { 0x88006440, "ppack.32.h", { {21,5,EREG}, {16,5,EREG}, {0,5,EREG} } }, ! 538: { 0x88006160, "ppack.8", { {21,5,EREG}, {16,5,EREG}, {0,5,EREG} } }, ! 539: { 0x88007800, "prot", { {21,5,EREG}, {16,5,EREG}, {0,5,EREG} } }, ! 540: { 0x88007000, "prot", { {21,5,EREG}, {16,5,EREG}, {7,4,E4ROT} } }, ! 541: { 0x88003060, "psub", { {21,5,EREG}, {16,5,EREG}, {0,5,EREG} } }, ! 542: { 0x88003020, "psub.b", { {21,5,EREG}, {16,5,EREG}, {0,5,EREG} } }, ! 543: { 0x88003040, "psub.h", { {21,5,EREG}, {16,5,EREG}, {0,5,EREG} } }, ! 544: { 0x880031e0, "psubs.s", { {21,5,EREG}, {16,5,EREG}, {0,5,EREG} } }, ! 545: { 0x880031a0, "psubs.s.b", { {21,5,EREG}, {16,5,EREG}, {0,5,EREG} } }, ! 546: { 0x880031c0, "psubs.s.h", { {21,5,EREG}, {16,5,EREG}, {0,5,EREG} } }, ! 547: { 0x880030e0, "psubs.u", { {21,5,EREG}, {16,5,EREG}, {0,5,EREG} } }, ! 548: { 0x880030a0, "psubs.u.b", { {21,5,EREG}, {16,5,EREG}, {0,5,EREG} } }, ! 549: { 0x880030c0, "psubs.u.h", { {21,5,EREG}, {16,5,EREG}, {0,5,EREG} } }, ! 550: { 0x88003160, "psubs.us", { {21,5,EREG}, {16,5,EREG}, {0,5,EREG} } }, ! 551: { 0x88003120, "psubs.us.b", { {21,5,EREG}, {16,5,EREG}, {0,5,EREG} } }, ! 552: { 0x88003140, "psubs.us.h", { {21,5,EREG}, {16,5,EREG}, {0,5,EREG} } }, ! 553: { 0x88006820, "punpk.b", { {21,5,EREG}, {16,5,REG}, {0,0,NIL} } }, ! 554: { 0x88006840, "punpk.h", { {21,5,EREG}, {16,5,REG}, {0,0,NIL} } }, ! 555: { 0x88006800, "punpk.n", { {21,5,EREG}, {16,5,REG}, {0,0,NIL} } }, ! 556: #endif m88110 ! 557: { 0XF000A800, "rot", { {21,5,REG}, {16,5,REG}, {0,5,ROT} } }, ! 558: { 0XF400A800, "rot", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 559: { 0xf400fc00, "rte", { {0,0,NIL}, {0,0,NIL}, {0,0,NIL} } }, ! 560: { 0XF0008800, "set", { {21,5,REG}, {16,5,REG}, {0,10,BF} } }, ! 561: { 0XF4008800, "set", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 562: { 0x24000000, "st", { {21,5,REG}, {16,5,REG}, {0,16,CNST} } }, ! 563: { 0xf4002600, "st", { {21,5,REG}, {16,5,REG}, {0,5,REGSC} } }, ! 564: { 0xf4002400, "st", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 565: #ifdef m88110 ! 566: { 0x34000000, "st", { {21,5,XREG}, {16,5,REG}, {0,16,CNST} } }, ! 567: { 0xf0002600, "st", { {21,5,XREG}, {16,5,REG}, {0,5,REGSC} } }, ! 568: { 0xf0002400, "st", { {21,5,XREG}, {16,5,REG}, {0,5,REG} } }, ! 569: { 0xf4002680, "st.wt", { {21,5,REG}, {16,5,REG}, {0,5,REGSC} } }, ! 570: { 0xf4002480, "st.wt", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 571: { 0xf0002680, "st.wt", { {21,5,XREG}, {16,5,REG}, {0,5,REGSC} } }, ! 572: { 0xf0002480, "st.wt", { {21,5,XREG}, {16,5,REG}, {0,5,REG} } }, ! 573: #endif m88110 ! 574: { 0x2c000000, "st.b", { {21,5,REG}, {16,5,REG}, {0,16,CNST} } }, ! 575: { 0xf4002e00, "st.b", { {21,5,REG}, {16,5,REG}, {0,5,REGSC} } }, ! 576: { 0xf4002c00, "st.b", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 577: #ifdef m88110 ! 578: { 0xf4002e80, "st.b.wt", { {21,5,REG}, {16,5,REG}, {0,5,REGSC} } }, ! 579: { 0xf4002c80, "st.b.wt", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 580: #endif m88110 ! 581: { 0xf4002f00, "st.b.usr", { {21,5,REG}, {16,5,REG}, {0,5,REGSC} } }, ! 582: { 0xf4002d00, "st.b.usr", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 583: #ifdef m88110 ! 584: { 0xf4002f80, "st.b.usr.wt", { {21,5,REG}, {16,5,REG}, {0,5,REGSC} } }, ! 585: { 0xf4002d80, "st.b.usr.wt", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 586: #endif m88110 ! 587: { 0x20000000, "st.d", { {21,5,REG}, {16,5,REG}, {0,16,CNST} } }, ! 588: { 0xf4002200, "st.d", { {21,5,REG}, {16,5,REG}, {0,5,REGSC} } }, ! 589: { 0xf4002000, "st.d", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 590: #ifdef m88110 ! 591: { 0x30000000, "st.d", { {21,5,XREG}, {16,5,REG}, {0,16,CNST} } }, ! 592: { 0xf0002200, "st.d", { {21,5,XREG}, {16,5,REG}, {0,5,REGSC} } }, ! 593: { 0xf0002000, "st.d", { {21,5,XREG}, {16,5,REG}, {0,5,REG} } }, ! 594: { 0xf4002280, "st.d.wt", { {21,5,REG}, {16,5,REG}, {0,5,REGSC} } }, ! 595: { 0xf4002080, "st.d.wt", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 596: { 0xf0002280, "st.d.wt", { {21,5,XREG}, {16,5,REG}, {0,5,REGSC} } }, ! 597: { 0xf0002080, "st.d.wt", { {21,5,XREG}, {16,5,REG}, {0,5,REG} } }, ! 598: #endif m88110 ! 599: { 0xf4002300, "st.d.usr", { {21,5,REG}, {16,5,REG}, {0,5,REGSC} } }, ! 600: { 0xf4002100, "st.d.usr", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 601: #ifdef m88110 ! 602: { 0xf0002300, "st.d.usr", { {21,5,XREG}, {16,5,REG}, {0,5,REGSC} } }, ! 603: { 0xf0002100, "st.d.usr", { {21,5,XREG}, {16,5,REG}, {0,5,REG} } }, ! 604: { 0xf4002380, "st.d.usr.wt", { {21,5,REG}, {16,5,REG}, {0,5,REGSC} } }, ! 605: { 0xf0002180, "st.d.usr.wt", { {21,5,XREG}, {16,5,REG}, {0,5,REG} } }, ! 606: { 0xf0002380, "st.d.usr.wt", { {21,5,XREG}, {16,5,REG}, {0,5,REGSC} } }, ! 607: { 0xf4002180, "st.d.usr.wt", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 608: #endif m88110 ! 609: { 0x28000000, "st.h", { {21,5,REG}, {16,5,REG}, {0,16,CNST} } }, ! 610: { 0xf4002a00, "st.h", { {21,5,REG}, {16,5,REG}, {0,5,REGSC} } }, ! 611: { 0xf4002800, "st.h", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 612: #ifdef m88110 ! 613: { 0xf4002a80, "st.h.wt", { {21,5,REG}, {16,5,REG}, {0,5,REGSC} } }, ! 614: { 0xf4002880, "st.h.wt", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 615: #endif m88110 ! 616: { 0xf4002b00, "st.h.usr", { {21,5,REG}, {16,5,REG}, {0,5,REGSC} } }, ! 617: { 0xf4002900, "st.h.usr", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 618: #ifdef m88110 ! 619: { 0xf4002b80, "st.h.usr.wt", { {21,5,REG}, {16,5,REG}, {0,5,REGSC} } }, ! 620: { 0xf4002980, "st.h.usr.wt", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 621: #endif m88110 ! 622: { 0xf4002700, "st.usr", { {21,5,REG}, {16,5,REG}, {0,5,REGSC} } }, ! 623: { 0xf4002500, "st.usr", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 624: #ifdef m88110 ! 625: { 0xf0002700, "st.usr", { {21,5,XREG}, {16,5,REG}, {0,5,REGSC} } }, ! 626: { 0xf0002500, "st.usr", { {21,5,XREG}, {16,5,REG}, {0,5,REG} } }, ! 627: { 0xf4002780, "st.usr.wt", { {21,5,REG}, {16,5,REG}, {0,5,REGSC} } }, ! 628: { 0xf4002580, "st.usr.wt", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 629: { 0xf0002780, "st.usr.wt", { {21,5,XREG}, {16,5,REG}, {0,5,REGSC} } }, ! 630: { 0xf0002580, "st.usr.wt", { {21,5,XREG}, {16,5,REG}, {0,5,REG} } }, ! 631: { 0x38000000, "st.x", { {21,5,XREG}, {16,5,REG}, {0,16,CNST} } }, ! 632: { 0xf0002a00, "st.x", { {21,5,XREG}, {16,5,REG}, {0,5,REGSC} } }, ! 633: { 0xf0002800, "st.x", { {21,5,XREG}, {16,5,REG}, {0,5,REG} } }, ! 634: { 0xf0002a80, "st.x.wt", { {21,5,XREG}, {16,5,REG}, {0,5,REGSC} } }, ! 635: { 0xf0002880, "st.x.wt", { {21,5,XREG}, {16,5,REG}, {0,5,REG} } }, ! 636: { 0xf0002b00, "st.x.usr", { {21,5,XREG}, {16,5,REG}, {0,5,REGSC} } }, ! 637: { 0xf0002900, "st.x.usr", { {21,5,XREG}, {16,5,REG}, {0,5,REG} } }, ! 638: { 0xf0002b80, "st.x.usr.wt", { {21,5,XREG}, {16,5,REG}, {0,5,REGSC} } }, ! 639: { 0xf0002980, "st.x.usr.wt", { {21,5,XREG}, {16,5,REG}, {0,5,REG} } }, ! 640: #endif m88110 ! 641: { 0x80008000, "stcr", { {16,5,REG}, {5,6,CRREG}, {0,0,NIL} } }, ! 642: { 0x74000000, "sub", { {21,5,REG}, {16,5,REG}, {0,16,CNST} } }, ! 643: { 0xf4007400, "sub", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 644: { 0xf4007600, "sub.ci", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 645: { 0xf4007700, "sub.cio", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 646: { 0xf4007500, "sub.co", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 647: { 0x64000000, "subu", { {21,5,REG}, {16,5,REG}, {0,16,CNST} } }, ! 648: { 0xf4006400, "subu", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 649: { 0xf4006600, "subu.ci", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 650: { 0xf4006700, "subu.cio", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 651: { 0xf4006500, "subu.co", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 652: { 0xf000d000, "tb0", { {21,5,CMPRSLT}, {16,5,REG}, {0,9,CNST} } }, ! 653: { 0xf000d800, "tb1", { {21,5,CMPRSLT}, {16,5,REG}, {0,9,CNST} } }, ! 654: { 0xf8000000, "tbnd", { {16,5,REG}, {0,16,CNST}, {0,0,NIL} } }, ! 655: { 0xf400f800, "tbnd", { {16,5,REG}, {0,5,REG}, {0,0,NIL} } }, ! 656: { 0xf000e800, "tcnd", { {21,5,CONDMASK}, {16,5,REG}, {0,9,CNST} } }, ! 657: { 0x84005880, "trnc.sd", { {21,5,REG}, {0,5,REG}, {0,0,NIL} } }, ! 658: #ifdef m88110 ! 659: { 0x8400d880, "trnc.sd", { {21,5,REG}, {0,5,XREG}, {0,0,NIL} } }, ! 660: #endif m88110 ! 661: { 0x84005800, "trnc.ss", { {21,5,REG}, {0,5,REG}, {0,0,NIL} } }, ! 662: #ifdef m88110 ! 663: { 0x8400d800, "trnc.ss", { {21,5,REG}, {0,5,XREG}, {0,0,NIL} } }, ! 664: { 0x8400d900, "trnc.sx", { {21,5,REG}, {0,5,XREG}, {0,0,NIL} } }, ! 665: #endif m88110 ! 666: { 0x8000c000, "xcr", { {21,5,REG}, {16,5,REG}, {5,6,CRREG} } }, ! 667: #ifndef m88110 ! 668: { 0x04000000, "xmem", { {21,5,REG}, {16,5,REG}, {0,16,CNST} } }, ! 669: #endif !defined(m88110) ! 670: { 0xf4000600, "xmem", { {21,5,REG}, {16,5,REG}, {0,5,REGSC} } }, ! 671: { 0xf4000400, "xmem", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 672: #ifndef m88110 ! 673: { 0x00000000, "xmem.bu", { {21,5,REG}, {16,5,REG}, {0,16,CNST} } }, ! 674: #endif !defined(m88110) ! 675: { 0xf4000200, "xmem.bu", { {21,5,REG}, {16,5,REG}, {0,5,REGSC} } }, ! 676: { 0xf4000000, "xmem.bu", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 677: { 0xf4000300, "xmem.bu.usr", { {21,5,REG}, {16,5,REG}, {0,5,REGSC} } }, ! 678: { 0xf4000100, "xmem.bu.usr", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 679: { 0xf4000700, "xmem.usr", { {21,5,REG}, {16,5,REG}, {0,5,REGSC} } }, ! 680: { 0xf4000500, "xmem.usr", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 681: { 0X50000000, "xor", { {21,5,REG}, {16,5,REG}, {0,16,CNST} } }, ! 682: { 0XF4005000, "xor", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 683: { 0XF4005400, "xor.c", { {21,5,REG}, {16,5,REG}, {0,5,REG} } }, ! 684: { 0X54000000, "xor.u", { {21,5,REG}, {16,5,REG}, {0,16,CNST} } }, ! 685: { 0x00000000, "", { {0,0,NIL}, {0,0,NIL}, {0,0,NIL} } }, ! 686: }; ! 687: ! 688: #define NUMOPCODES ((sizeof m88k_opcodes)/(sizeof m88k_opcodes[0]))
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