Return to sparc-opcode.h CVS log

Up to [Apple XNU] / GNUtools / cctools / as

Annotation of GNUtools/cctools/as/sparc-opcode.h, revision 1.1

1.1     ! root        1: 
        !             2: /* Table of opcodes for the sparc.
        !             3:        Copyright 1989, 1991, 1992 Free Software Foundation, Inc.
        !             4: 
        !             5: This file is part of the BFD library.
        !             6: 
        !             7: BFD is free software; you can redistribute it and/or modify it under
        !             8: the terms of the GNU General Public License as published by the Free
        !             9: Software Foundation; either version 2, or (at your option) any later
        !            10: version.
        !            11: 
        !            12: BFD is distributed in the hope that it will be useful, but WITHOUT ANY
        !            13: WARRANTY; without even the implied warranty of MERCHANTABILITY or
        !            14: FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
        !            15: for more details.
        !            16: 
        !            17: You should have received a copy of the GNU General Public License
        !            18: along with this software; see the file COPYING.  If not, write to
        !            19: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
        !            20: 
        !            21: /* FIXME-someday: perhaps the ,a's and such should be embedded in the
        !            22:    instruction's name rather than the args.  This would make gas faster, pinsn
        !            23:    slower, but would mess up some macros a bit.  xoxorich. */
        !            24: 
        !            25: 
        !            26: /* The SPARC opcode table (and other related data) is defined in
        !            27:    the opcodes library in sparc-opc.c.  If you change anything here, make
        !            28:    sure you fix up that file, and vice versa.  */
        !            29: 
        !            30:  /* FIXME-someday: perhaps the ,a's and such should be embedded in the
        !            31:     instruction's name rather than the args.  This would make gas faster, pinsn
        !            32:     slower, but would mess up some macros a bit.  xoxorich. */
        !            33: 
        !            34: #define sparc_architecture     bfd_sparc_architecture
        !            35: #define architecture_pname     bfd_sparc_architecture_pname
        !            36: #define sparc_opcode           bfd_sparc_opcode
        !            37: #define sparc_opcodes          bfd_sparc_opcodes
        !            38: 
        !            39: /*
        !            40:  * Structure of an opcode table entry.
        !            41:  * This enumerator must parallel the architecture_pname array
        !            42:  * in bfd/opc-sparc.c.
        !            43:  */
        !            44: enum sparc_architecture {
        !            45:        v6 = 0,
        !            46:        v7,
        !            47:        v8,
        !            48:        sparclite
        !            49: };
        !            50: 
        !            51: extern const char *architecture_pname[];
        !            52: 
        !            53: 
        !            54: 
        !            55: struct sparc_opcode {
        !            56:        const char *name;
        !            57:        unsigned long match;    /* Bits that must be set. */
        !            58:        unsigned long lose;     /* Bits that must not be set. */
        !            59:        const char *args;
        !            60:  /* This was called "delayed" in versions before the flags. */
        !            61:        char flags;
        !            62:        enum sparc_architecture architecture;
        !            63: };
        !            64: 
        !            65: #define        F_DELAYED       1       /* Delayed branch */
        !            66: #define        F_ALIAS         2       /* Alias for a "real" instruction */
        !            67: #define        F_UNBR          4       /* Unconditional branch */
        !            68: #define        F_CONDBR        8       /* Conditional branch */
        !            69: #define        F_JSR           16      /* Subroutine call */
        !            70: 
        !            71: /*
        !            72: 
        !            73: All sparc opcodes are 32 bits, except for the `set' instruction (really a
        !            74: macro), which is 64 bits. It is handled as a special case.
        !            75: 
        !            76: The match component is a mask saying which bits must match a particular
        !            77: opcode in order for an instruction to be an instance of that opcode.
        !            78: 
        !            79: The args component is a string containing one character for each operand of the
        !            80: instruction.
        !            81: 
        !            82: Kinds of operands:
        !            83:        #       Number used by optimizer.       It is ignored.
        !            84:        1       rs1 register.
        !            85:        2       rs2 register.
        !            86:        d       rd register.
        !            87:        e       frs1 floating point register.
        !            88:        v       frs1 floating point register (double/even).
        !            89:        V       frs1 floating point register (quad/multiple of 4).
        !            90:        f       frs2 floating point register.
        !            91:        B       frs2 floating point register (double/even).
        !            92:        R       frs2 floating point register (quad/multiple of 4).
        !            93:        g       frsd floating point register.
        !            94:        H       frsd floating point register (double/even).
        !            95:        J       frsd floating point register (quad/multiple of 4).
        !            96:        b       crs1 coprocessor register
        !            97:        c       crs2 coprocessor register
        !            98:        D       crsd coprocessor register
        !            99:        m       alternate space register (asr) in rd
        !           100:        M       alternate space register (asr) in rs1
        !           101:        h       22 high bits.
        !           102:        i       13 bit Immediate.
        !           103:        n       22 bit immediate.
        !           104:        l       22 bit PC relative immediate.
        !           105:        L       30 bit PC relative immediate.
        !           106:        a       Annul.  The annul bit is set.
        !           107:        A       Alternate address space. Stored as 8 bits.
        !           108:        C       Coprocessor state register.
        !           109:        F       floating point state register.
        !           110:        p       Processor state register.
        !           111:        q       Floating point queue.
        !           112:        r       Single register that is both rs1 and rsd.
        !           113:        u       Single register that is both rs2 and rsd.
        !           114:        Q       Coprocessor queue.
        !           115:        S       Special case.
        !           116:        t       Trap base register.
        !           117:        w       Window invalid mask register.
        !           118:        y       Y register.
        !           119: 
        !           120: The following chars are unused: (note: ,[] are used as punctuation)
        !           121: [xOUXY3450]
        !           122: 
        !           123: */
        !           124: 
        !           125: #define OP2(x)         (((x)&0x7) << 22) /* op2 field of format2 insns */
        !           126: #define OP3(x)         (((x)&0x3f) << 19) /* op3 field of format3 insns */
        !           127: #define OP(x)          ((unsigned)((x)&0x3) << 30) /* op field of all insns */
        !           128: #define OPF(x)         (((x)&0x1ff) << 5) /* opf field of float insns */
        !           129: #define F3F(x, y, z)   (OP(x) | OP3(y) | OPF(z)) /* format3 float insns */
        !           130: #define F3I(x)         (((x)&0x1) << 13) /* immediate field of format 3 insns */
        !           131: #define F2(x, y)       (OP(x) | OP2(y)) /* format 2 insns */
        !           132: #define F3(x, y, z)    (OP(x) | OP3(y) | F3I(z)) /* format3 insns */
        !           133: #define F1(x)          (OP(x))
        !           134: #define DISP30(x)      ((x)&0x3fffffff)
        !           135: #define ASI(x)         (((x)&0xff) << 5) /* asi field of format3 insns */
        !           136: #define RS2(x)         ((x)&0x1f) /* rs2 field */
        !           137: #define SIMM13(x)      ((x)&0x1fff) /* simm13 field */
        !           138: #define RD(x)          (((x)&0x1f) << 25) /* destination register field */
        !           139: #define RS1(x)         (((x)&0x1f) << 14) /* rs1 field */
        !           140: #define ASI_RS2(x)     (SIMM13(x))
        !           141: 
        !           142: #define ANNUL  (1<<29)
        !           143: #define        IMMED   F3I(1)
        !           144: #define RD_G0  RD(~0)
        !           145: #define        RS1_G0  RS1(~0)
        !           146: #define        RS2_G0  RS2(~0)
        !           147: 
        !           148: extern struct sparc_opcode sparc_opcodes[];
        !           149: extern const int bfd_sparc_num_opcodes;
        !           150: 
        !           151: #define NUMOPCODES bfd_sparc_num_opcodes
        !           152: 
        !           153: /*
        !           154:  * Local Variables:
        !           155:  * fill-column: 131
        !           156:  * comment-column: 0
        !           157:  * End:
        !           158:  */
        !           159: 
        !           160: 
        !           161: const char *architecture_pname[] = {
        !           162:        "v6",
        !           163:        "v7",
        !           164:        "v8",
        !           165:        "sparclite",
        !           166:        NULL,
        !           167: };
        !           168: 
        !           169: 
        !           170: /* Branch condition field.  */
        !           171: #define COND(x)                (((x)&0xf)<<25)
        !           172: 
        !           173: 
        !           174: 
        !           175: #define CONDA  (COND(0x8))
        !           176: #define CONDCC (COND(0xd))
        !           177: #define CONDCS (COND(0x5))
        !           178: #define CONDE  (COND(0x1))
        !           179: #define CONDG  (COND(0xa))
        !           180: #define CONDGE (COND(0xb))
        !           181: #define CONDGU (COND(0xc))
        !           182: #define CONDL  (COND(0x3))
        !           183: #define CONDLE (COND(0x2))
        !           184: #define CONDLEU        (COND(0x4))
        !           185: #define CONDN  (COND(0x0))
        !           186: #define CONDNE (COND(0x9))
        !           187: #define CONDNEG        (COND(0x6))
        !           188: #define CONDPOS        (COND(0xe))
        !           189: #define CONDVC (COND(0xf))
        !           190: #define CONDVS (COND(0x7))
        !           191: 
        !           192: #define CONDNZ CONDNE
        !           193: #define CONDZ  CONDE
        !           194: #define CONDGEU        CONDCC
        !           195: #define CONDLU CONDCS
        !           196: 
        !           197: #define FCONDA         (COND(0x8))
        !           198: #define FCONDE         (COND(0x9))
        !           199: #define FCONDG         (COND(0x6))
        !           200: #define FCONDGE                (COND(0xb))
        !           201: #define FCONDL         (COND(0x4))
        !           202: #define FCONDLE                (COND(0xd))
        !           203: #define FCONDLG                (COND(0x2))
        !           204: #define FCONDN         (COND(0x0))
        !           205: #define FCONDNE                (COND(0x1))
        !           206: #define FCONDO         (COND(0xf))
        !           207: #define FCONDU         (COND(0x7))
        !           208: #define FCONDUE                (COND(0xa))
        !           209: #define FCONDUG                (COND(0x5))
        !           210: #define FCONDUGE       (COND(0xc))
        !           211: #define FCONDUL                (COND(0x3))
        !           212: #define FCONDULE       (COND(0xe))
        !           213: 
        !           214: #define FCONDNZ        FCONDNE
        !           215: #define FCONDZ FCONDE
        !           216: 
        !           217: 
        !           218: /* The order of the opcodes in the table is significant:
        !           219:        
        !           220:        * The assembler requires that all instances of the same mnemonic must
        !           221:        be consecutive. If they aren't, the assembler will bomb at runtime.
        !           222: 
        !           223:        * The disassembler should not care about the order of the opcodes.
        !           224: 
        !           225: */
        !           226: 
        !           227: struct sparc_opcode sparc_opcodes[] = {
        !           228: 
        !           229: { "ld",        F3(3, 0x00, 0), F3(~3, ~0x00, ~0),              "[1+2],d", 0, v6 },
        !           230: { "ld",        F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0,       "[1],d", 0, v6 }, /* ld [rs1+%g0],d */
        !           231: { "ld",        F3(3, 0x00, 1), F3(~3, ~0x00, ~1),              "[1+i],d", 0, v6 },
        !           232: { "ld",        F3(3, 0x00, 1), F3(~3, ~0x00, ~1),              "[i+1],d", 0, v6 },
        !           233: { "ld",        F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0,       "[i],d", 0, v6 },
        !           234: { "ld",        F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0),   "[1],d", 0, v6 }, /* ld [rs1+0],d */
        !           235: { "ld",        F3(3, 0x20, 0), F3(~3, ~0x20, ~0),              "[1+2],g", 0, v6 },
        !           236: { "ld",        F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0,       "[1],g", 0, v6 }, /* ld [rs1+%g0],d */
        !           237: { "ld",        F3(3, 0x20, 1), F3(~3, ~0x20, ~1),              "[1+i],g", 0, v6 },
        !           238: { "ld",        F3(3, 0x20, 1), F3(~3, ~0x20, ~1),              "[i+1],g", 0, v6 },
        !           239: { "ld",        F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|RS1_G0,       "[i],g", 0, v6 },
        !           240: { "ld",        F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|SIMM13(~0),   "[1],g", 0, v6 }, /* ld [rs1+0],d */
        !           241: 
        !           242: { "ld",        F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RD(~0),       "[1+2],F", 0, v6 },
        !           243: { "ld",        F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RS2_G0|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+%g0],d */
        !           244: { "ld",        F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0),       "[1+i],F", 0, v6 },
        !           245: { "ld",        F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0),       "[i+1],F", 0, v6 },
        !           246: { "ld",        F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~0),"[i],F", 0, v6 },
        !           247: { "ld",        F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+0],d */
        !           248: 
        !           249: { "ld",        F3(3, 0x30, 0), F3(~3, ~0x30, ~0),              "[1+2],D", F_ALIAS, v6 },
        !           250: { "ld",        F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0,       "[1],D", F_ALIAS, v6 }, /* ld [rs1+%g0],d */
        !           251: { "ld",        F3(3, 0x30, 1), F3(~3, ~0x30, ~1),              "[1+i],D", F_ALIAS, v6 },
        !           252: { "ld",        F3(3, 0x30, 1), F3(~3, ~0x30, ~1),              "[i+1],D", F_ALIAS, v6 },
        !           253: { "ld",        F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0,       "[i],D", F_ALIAS, v6 },
        !           254: { "ld",        F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0),   "[1],D", F_ALIAS, v6 }, /* ld [rs1+0],d */
        !           255: { "ld",        F3(3, 0x31, 0), F3(~3, ~0x31, ~0),              "[1+2],C", 0, v6 },
        !           256: { "ld",        F3(3, 0x31, 0), F3(~3, ~0x31, ~0)|RS2_G0,       "[1],C", 0, v6 }, /* ld [rs1+%g0],d */
        !           257: { "ld",        F3(3, 0x31, 1), F3(~3, ~0x31, ~1),              "[1+i],C", 0, v6 },
        !           258: { "ld",        F3(3, 0x31, 1), F3(~3, ~0x31, ~1),              "[i+1],C", 0, v6 },
        !           259: { "ld",        F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|RS1_G0,       "[i],C", 0, v6 },
        !           260: { "ld",        F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|SIMM13(~0),   "[1],C", 0, v6 }, /* ld [rs1+0],d */
        !           261: 
        !           262: 
        !           263: { "ldd",       F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0),      "[1+2],d", 0, v6 },
        !           264: { "ldd",       F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0),  "[1],d", 0, v6 }, /* ldd [rs1+%g0],d */
        !           265: { "ldd",       F3(3, 0x03, 1), F3(~3, ~0x03, ~1),              "[1+i],d", 0, v6 },
        !           266: { "ldd",       F3(3, 0x03, 1), F3(~3, ~0x03, ~1),              "[i+1],d", 0, v6 },
        !           267: { "ldd",       F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0,       "[i],d", 0, v6 },
        !           268: { "ldd",       F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0),   "[1],d", 0, v6 }, /* ldd [rs1+0],d */
        !           269: { "ldd",       F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI(~0),      "[1+2],H", 0, v6 },
        !           270: { "ldd",       F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI_RS2(~0),  "[1],H", 0, v6 }, /* ldd [rs1+%g0],d */
        !           271: { "ldd",       F3(3, 0x23, 1), F3(~3, ~0x23, ~1),              "[1+i],H", 0, v6 },
        !           272: { "ldd",       F3(3, 0x23, 1), F3(~3, ~0x23, ~1),              "[i+1],H", 0, v6 },
        !           273: { "ldd",       F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|RS1_G0,       "[i],H", 0, v6 },
        !           274: { "ldd",       F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|SIMM13(~0),   "[1],H", 0, v6 }, /* ldd [rs1+0],d */
        !           275: { "ldd",       F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI(~0),      "[1+2],D", F_ALIAS, v6 },
        !           276: { "ldd",       F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI_RS2(~0),  "[1],D", F_ALIAS, v6 }, /* ldd [rs1+%g0],d */
        !           277: { "ldd",       F3(3, 0x33, 1), F3(~3, ~0x33, ~1),              "[1+i],D", F_ALIAS, v6 },
        !           278: { "ldd",       F3(3, 0x33, 1), F3(~3, ~0x33, ~1),              "[i+1],D", F_ALIAS, v6 },
        !           279: { "ldd",       F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0,       "[i],D", F_ALIAS, v6 },
        !           280: { "ldd",       F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0),   "[1],D", F_ALIAS, v6 }, /* ldd [rs1+0],d */
        !           281: 
        !           282: 
        !           283: { "ldsb",      F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI(~0),      "[1+2],d", 0, v6 },
        !           284: { "ldsb",      F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI_RS2(~0),  "[1],d", 0, v6 }, /* ldsb [rs1+%g0],d */
        !           285: { "ldsb",      F3(3, 0x09, 1), F3(~3, ~0x09, ~1),              "[1+i],d", 0, v6 },
        !           286: { "ldsb",      F3(3, 0x09, 1), F3(~3, ~0x09, ~1),              "[i+1],d", 0, v6 },
        !           287: { "ldsb",      F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|RS1_G0,       "[i],d", 0, v6 },
        !           288: { "ldsb",      F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|SIMM13(~0),   "[1],d", 0, v6 }, /* ldsb [rs1+0],d */
        !           289: 
        !           290: { "ldsh",      F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI_RS2(~0),  "[1],d", 0, v6 }, /* ldsh [rs1+%g0],d */
        !           291: { "ldsh",      F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI(~0),      "[1+2],d", 0, v6 },
        !           292: { "ldsh",      F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1),              "[1+i],d", 0, v6 },
        !           293: { "ldsh",      F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1),              "[i+1],d", 0, v6 },
        !           294: { "ldsh",      F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|RS1_G0,       "[i],d", 0, v6 },
        !           295: { "ldsh",      F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|SIMM13(~0),   "[1],d", 0, v6 }, /* ldsh [rs1+0],d */
        !           296: 
        !           297: { "ldstub",    F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI(~0),      "[1+2],d", 0, v6 },
        !           298: { "ldstub",    F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI_RS2(~0),  "[1],d", 0, v6 }, /* ldstub [rs1+%g0],d */
        !           299: { "ldstub",    F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1),              "[1+i],d", 0, v6 },
        !           300: { "ldstub",    F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1),              "[i+1],d", 0, v6 },
        !           301: { "ldstub",    F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|RS1_G0,       "[i],d", 0, v6 },
        !           302: { "ldstub",    F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|SIMM13(~0),   "[1],d", 0, v6 }, /* ldstub [rs1+0],d */
        !           303: 
        !           304: 
        !           305: { "ldub",      F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI(~0),      "[1+2],d", 0, v6 },
        !           306: { "ldub",      F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI_RS2(~0),  "[1],d", 0, v6 }, /* ldub [rs1+%g0],d */
        !           307: { "ldub",      F3(3, 0x01, 1), F3(~3, ~0x01, ~1),              "[1+i],d", 0, v6 },
        !           308: { "ldub",      F3(3, 0x01, 1), F3(~3, ~0x01, ~1),              "[i+1],d", 0, v6 },
        !           309: { "ldub",      F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|RS1_G0,       "[i],d", 0, v6 },
        !           310: { "ldub",      F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|SIMM13(~0),   "[1],d", 0, v6 }, /* ldub [rs1+0],d */
        !           311: 
        !           312: { "lduh",      F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI(~0),      "[1+2],d", 0, v6 },
        !           313: { "lduh",      F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI_RS2(~0),  "[1],d", 0, v6 }, /* lduh [rs1+%g0],d */
        !           314: { "lduh",      F3(3, 0x02, 1), F3(~3, ~0x02, ~1),              "[1+i],d", 0, v6 },
        !           315: { "lduh",      F3(3, 0x02, 1), F3(~3, ~0x02, ~1),              "[i+1],d", 0, v6 },
        !           316: { "lduh",      F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|RS1_G0,       "[i],d", 0, v6 },
        !           317: { "lduh",      F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|SIMM13(~0),   "[1],d", 0, v6 }, /* lduh [rs1+0],d */
        !           318: 
        !           319: 
        !           320: 
        !           321: { "lda",       F3(3, 0x10, 0), F3(~3, ~0x10, ~0),              "[1+2]A,d", 0, v6 },
        !           322: { "lda",       F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0,       "[1]A,d", 0, v6 }, /* lda [rs1+%g0],d */
        !           323: 
        !           324: { "ldda",      F3(3, 0x13, 0), F3(~3, ~0x13, ~0),              "[1+2]A,d", 0, v6 },
        !           325: { "ldda",      F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0,       "[1]A,d", 0, v6 }, /* ldda [rs1+%g0],d */
        !           326: 
        !           327: 
        !           328: 
        !           329: { "ldsba",     F3(3, 0x19, 0), F3(~3, ~0x19, ~0),              "[1+2]A,d", 0, v6 },
        !           330: { "ldsba",     F3(3, 0x19, 0), F3(~3, ~0x19, ~0)|RS2_G0,       "[1]A,d", 0, v6 }, /* ldsba [rs1+%g0],d */
        !           331: 
        !           332: { "ldsha",     F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0),              "[1+2]A,d", 0, v6 },
        !           333: { "ldsha",     F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0)|RS2_G0,       "[1]A,d", 0, v6 }, /* ldsha [rs1+%g0],d */
        !           334: 
        !           335: { "ldstuba",   F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0),              "[1+2]A,d", 0, v6 },
        !           336: { "ldstuba",   F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0)|RS2_G0,       "[1]A,d", 0, v6 }, /* ldstuba [rs1+%g0],d */
        !           337: 
        !           338: 
        !           339: { "lduba",     F3(3, 0x11, 0), F3(~3, ~0x11, ~0),              "[1+2]A,d", 0, v6 },
        !           340: { "lduba",     F3(3, 0x11, 0), F3(~3, ~0x11, ~0)|RS2_G0,       "[1]A,d", 0, v6 }, /* lduba [rs1+%g0],d */
        !           341: 
        !           342: { "lduha",     F3(3, 0x12, 0), F3(~3, ~0x12, ~0),              "[1+2]A,d", 0, v6 },
        !           343: { "lduha",     F3(3, 0x12, 0), F3(~3, ~0x12, ~0)|RS2_G0,       "[1]A,d", 0, v6 }, /* lduha [rs1+%g0],d */
        !           344: 
        !           345: 
        !           346: 
        !           347: { "st",        F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0),              "d,[1+2]", 0, v6 },
        !           348: { "st",        F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0),          "d,[1]", 0, v6 }, /* st d,[rs1+%g0] */
        !           349: { "st",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1),                      "d,[1+i]", 0, v6 },
        !           350: { "st",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1),                      "d,[i+1]", 0, v6 },
        !           351: { "st",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0,               "d,[i]", 0, v6 },
        !           352: { "st",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0),           "d,[1]", 0, v6 }, /* st d,[rs1+0] */
        !           353: { "st",        F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI(~0),              "g,[1+2]", 0, v6 },
        !           354: { "st",        F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI_RS2(~0),          "g,[1]", 0, v6 }, /* st d[rs1+%g0] */
        !           355: { "st",        F3(3, 0x24, 1), F3(~3, ~0x24, ~1),                      "g,[1+i]", 0, v6 },
        !           356: { "st",        F3(3, 0x24, 1), F3(~3, ~0x24, ~1),                      "g,[i+1]", 0, v6 },
        !           357: { "st",        F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|RS1_G0,               "g,[i]", 0, v6 },
        !           358: { "st",        F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|SIMM13(~0),           "g,[1]", 0, v6 }, /* st d,[rs1+0] */
        !           359: { "st",        F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI(~0),              "D,[1+2]", F_ALIAS, v6 },
        !           360: { "st",        F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI_RS2(~0),          "D,[1]", F_ALIAS, v6 }, /* st d,[rs1+%g0] */
        !           361: { "st",        F3(3, 0x34, 1), F3(~3, ~0x34, ~1),                      "D,[1+i]", F_ALIAS, v6 },
        !           362: { "st",        F3(3, 0x34, 1), F3(~3, ~0x34, ~1),                      "D,[i+1]", F_ALIAS, v6 },
        !           363: { "st",        F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0,               "D,[i]", F_ALIAS, v6 },
        !           364: { "st",        F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0),           "D,[1]", F_ALIAS, v6 }, /* st d,[rs1+0] */
        !           365: { "st",        F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI(~0),              "C,[1+2]", 0, v6 },
        !           366: { "st",        F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI_RS2(~0),          "C,[1]", 0, v6 }, /* st d,[rs1+%g0] */
        !           367: { "st",        F3(3, 0x35, 1), F3(~3, ~0x35, ~1),                      "C,[1+i]", 0, v6 },
        !           368: { "st",        F3(3, 0x35, 1), F3(~3, ~0x35, ~1),                      "C,[i+1]", 0, v6 },
        !           369: { "st",        F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|RS1_G0,               "C,[i]", 0, v6 },
        !           370: { "st",        F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|SIMM13(~0),           "C,[1]", 0, v6 }, /* st d,[rs1+0] */
        !           371: 
        !           372: { "st",        F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI(~0),        "F,[1+2]", 0, v6 },
        !           373: { "st",        F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI_RS2(~0),    "F,[1]", 0, v6 }, /* st d,[rs1+%g0] */
        !           374: { "st",        F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0,                "F,[1+i]", 0, v6 },
        !           375: { "st",        F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0,                "F,[i+1]", 0, v6 },
        !           376: { "st",        F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|RS1_G0,         "F,[i]", 0, v6 },
        !           377: { "st",        F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|SIMM13(~0),     "F,[1]", 0, v6 }, /* st d,[rs1+0] */
        !           378: 
        !           379: 
        !           380: { "sta",       F3(3, 0x14, 0), F3(~3, ~0x14, ~0),              "d,[1+2]A", 0, v6 },
        !           381: { "sta",       F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0),      "d,[1]A", 0, v6 }, /* sta d,[rs1+%g0] */
        !           382: 
        !           383: 
        !           384: 
        !           385: { "stb",       F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0),      "d,[1+2]", 0, v6 },
        !           386: { "stb",       F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0),  "d,[1]", 0, v6 }, /* stb d,[rs1+%g0] */
        !           387: { "stb",       F3(3, 0x05, 1), F3(~3, ~0x05, ~1),              "d,[1+i]", 0, v6 },
        !           388: { "stb",       F3(3, 0x05, 1), F3(~3, ~0x05, ~1),              "d,[i+1]", 0, v6 },
        !           389: { "stb",       F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0,       "d,[i]", 0, v6 },
        !           390: { "stb",       F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0),   "d,[1]", 0, v6 }, /* stb d,[rs1+0] */
        !           391: 
        !           392: { "stba",      F3(3, 0x15, 0), F3(~3, ~0x15, ~0),              "d,[1+2]A", 0, v6 },
        !           393: { "stba",      F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0),      "d,[1]A", 0, v6 }, /* stba d,[rs1+%g0] */
        !           394: 
        !           395: { "std",       F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0),      "d,[1+2]", 0, v6 },
        !           396: { "std",       F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0),  "d,[1]", 0, v6 }, /* std d,[rs1+%g0] */
        !           397: { "std",       F3(3, 0x07, 1), F3(~3, ~0x07, ~1),              "d,[1+i]", 0, v6 },
        !           398: { "std",       F3(3, 0x07, 1), F3(~3, ~0x07, ~1),              "d,[i+1]", 0, v6 },
        !           399: { "std",       F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0,       "d,[i]", 0, v6 },
        !           400: { "std",       F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0),   "d,[1]", 0, v6 }, /* std d,[rs1+0] */
        !           401: { "std",       F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0),      "q,[1+2]", F_ALIAS, v6 },
        !           402: { "std",       F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0),  "q,[1]", F_ALIAS, v6 }, /* std d,[rs1+%g0] */
        !           403: { "std",       F3(3, 0x26, 1), F3(~3, ~0x26, ~1),              "q,[1+i]", F_ALIAS, v6 },
        !           404: { "std",       F3(3, 0x26, 1), F3(~3, ~0x26, ~1),              "q,[i+1]", F_ALIAS, v6 },
        !           405: { "std",       F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0,       "q,[i]", F_ALIAS, v6 },
        !           406: { "std",       F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0),   "q,[1]", F_ALIAS, v6 }, /* std d,[rs1+0] */
        !           407: { "std",       F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI(~0),      "H,[1+2]", 0, v6 },
        !           408: { "std",       F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI_RS2(~0),  "H,[1]", 0, v6 }, /* std d,[rs1+%g0] */
        !           409: { "std",       F3(3, 0x27, 1), F3(~3, ~0x27, ~1),              "H,[1+i]", 0, v6 },
        !           410: { "std",       F3(3, 0x27, 1), F3(~3, ~0x27, ~1),              "H,[i+1]", 0, v6 },
        !           411: { "std",       F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|RS1_G0,       "H,[i]", 0, v6 },
        !           412: { "std",       F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|SIMM13(~0),   "H,[1]", 0, v6 }, /* std d,[rs1+0] */
        !           413: { "std",       F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0),      "Q,[1+2]", F_ALIAS, v6 },
        !           414: { "std",       F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0),  "Q,[1]", F_ALIAS, v6 }, /* std d,[rs1+%g0] */
        !           415: { "std",       F3(3, 0x36, 1), F3(~3, ~0x36, ~1),              "Q,[1+i]", F_ALIAS, v6 },
        !           416: { "std",       F3(3, 0x36, 1), F3(~3, ~0x36, ~1),              "Q,[i+1]", F_ALIAS, v6 },
        !           417: { "std",       F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0,       "Q,[i]", F_ALIAS, v6 },
        !           418: { "std",       F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0),   "Q,[1]", F_ALIAS, v6 }, /* std d,[rs1+0] */
        !           419: { "std",       F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI(~0),      "D,[1+2]", F_ALIAS, v6 },
        !           420: { "std",       F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI_RS2(~0),  "D,[1]", F_ALIAS, v6 }, /* std d,[rs1+%g0] */
        !           421: { "std",       F3(3, 0x37, 1), F3(~3, ~0x37, ~1),              "D,[1+i]", F_ALIAS, v6 },
        !           422: { "std",       F3(3, 0x37, 1), F3(~3, ~0x37, ~1),              "D,[i+1]", F_ALIAS, v6 },
        !           423: { "std",       F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0,       "D,[i]", F_ALIAS, v6 },
        !           424: { "std",       F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0),   "D,[1]", F_ALIAS, v6 }, /* std d,[rs1+0] */
        !           425: 
        !           426: { "stda",      F3(3, 0x17, 0), F3(~3, ~0x17, ~0),              "d,[1+2]A", 0, v6 },
        !           427: { "stda",      F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0),      "d,[1]A", 0, v6 }, /* stda d,[rs1+%g0] */
        !           428: 
        !           429: { "sth",       F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0),      "d,[1+2]", 0, v6 },
        !           430: { "sth",       F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0),  "d,[1]", 0, v6 }, /* sth d,[rs1+%g0] */
        !           431: { "sth",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1),              "d,[1+i]", 0, v6 },
        !           432: { "sth",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1),              "d,[i+1]", 0, v6 },
        !           433: { "sth",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0,       "d,[i]", 0, v6 },
        !           434: { "sth",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0),   "d,[1]", 0, v6 }, /* sth d,[+] */
        !           435: 
        !           436: { "stha",      F3(3, 0x16, 0), F3(~3, ~0x16, ~0),              "d,[1+2]A", 0, v6 },
        !           437: { "stha",      F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0),      "d,[1]A", 0, v6 }, /* stha ,[+%] */
        !           438: 
        !           439: 
        !           440: 
        !           441: 
        !           442: 
        !           443: 
        !           444: { "swap",      F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI(~0),      "[1+2],d", 0, v7 },
        !           445: { "swap",      F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI_RS2(~0),  "[1],d", 0, v7 }, /* swap [rs1+%g0],d */
        !           446: { "swap",      F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1),              "[1+i],d", 0, v7 },
        !           447: { "swap",      F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1),              "[i+1],d", 0, v7 },
        !           448: { "swap",      F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|RS1_G0,       "[i],d", 0, v7 },
        !           449: { "swap",      F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|SIMM13(~0),   "[1],d", 0, v7 }, /* swap [rs1+0],d */
        !           450: 
        !           451: { "swapa",     F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0),              "[1+2]A,d", 0, v7 },
        !           452: { "swapa",     F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0)|RS2(~0),      "[1]A,d", 0, v7 }, /* swapa [rs1+%g0],d */
        !           453: 
        !           454: { "restore",   F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|ASI(~0),                      "1,2,d", 0, v6 },
        !           455: { "restore",   F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|RD_G0|RS1_G0|ASI_RS2(~0),     "", 0, v6 }, /* restore %g0,%g0,%g0 */
        !           456: { "restore",   F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1),                              "1,i,d", 0, v6 },
        !           457: { "restore",   F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1)|RD_G0|RS1_G0|SIMM13(~0),      "", 0, v6 }, /* restore %g0,0,%g0 */
        !           458: 
        !           459: { "rett",      F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI(~0),        "1+2", F_UNBR|F_DELAYED, v6 }, /* rett rs1+rs2 */
        !           460: { "rett",      F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI_RS2(~0),    "1", F_UNBR|F_DELAYED, v6 },    /* rett rs1,%g0 */
        !           461: { "rett",      F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0,        "1+i", F_UNBR|F_DELAYED, v6 }, /* rett rs1+X */
        !           462: { "rett",      F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0,        "i+1", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */
        !           463: { "rett",      F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0,"i", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */
        !           464: { "rett",      F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 },    /* rett X */
        !           465: { "rett",      F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|SIMM13(~0),     "1", F_UNBR|F_DELAYED, v6 },    /* rett rs1+0 */
        !           466: 
        !           467: { "save",      F3(2, 0x3c, 0), F3(~2, ~0x3c, ~0)|ASI(~0),      "1,2,d", 0, v6 },
        !           468: { "save",      F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1),              "1,i,d", 0, v6 },
        !           469: { "save",      0x81e00000,     ~0x81e00000,    "", F_ALIAS, v6 },
        !           470: 
        !           471: { "ret",  F3(2, 0x38, 1)|RS1(0x1f)|SIMM13(8), F3(~2, ~0x38, ~1)|SIMM13(~8),           "", F_UNBR|F_DELAYED, v6 }, /* jmpl %i7+8,%g0 */
        !           472: { "retl", F3(2, 0x38, 1)|RS1(0x0f)|SIMM13(8), F3(~2, ~0x38, ~1)|RS1(~0x0f)|SIMM13(~8), "", F_UNBR|F_DELAYED, v6 }, /* jmpl %o7+8,%g0 */
        !           473: 
        !           474: { "jmpl",      F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI(~0),      "1+2,d", F_JSR|F_DELAYED, v6 },
        !           475: { "jmpl",      F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI_RS2(~0),  "1,d", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,d */
        !           476: { "jmpl",      F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|SIMM13(~0),   "1,d", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,d */
        !           477: { "jmpl",      F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RS1_G0,       "i,d", F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,d */
        !           478: { "jmpl",      F3(2, 0x38, 1), F3(~2, ~0x38, ~1),              "1+i,d", F_JSR|F_DELAYED, v6 },
        !           479: { "jmpl",      F3(2, 0x38, 1), F3(~2, ~0x38, ~1),              "i+1,d", F_JSR|F_DELAYED, v6 },
        !           480: 
        !           481: 
        !           482: { "flush",     F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0),      "1+2", 0, v8 },
        !           483: { "flush",     F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0),  "1", 0, v8 }, /* flush rs1+%g0 */
        !           484: { "flush",     F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0),   "1", 0, v8 }, /* flush rs1+0 */
        !           485: { "flush",     F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0,       "i", 0, v8 }, /* flush %g0+i */
        !           486: { "flush",     F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),              "1+i", 0, v8 },
        !           487: { "flush",     F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),              "i+1", 0, v8 },
        !           488: 
        !           489: /* IFLUSH was renamed to FLUSH in v8.  */
        !           490: { "iflush",    F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0),      "1+2", F_ALIAS, v6 },
        !           491: { "iflush",    F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0),  "1", F_ALIAS, v6 }, /* flush rs1+%g0 */
        !           492: { "iflush",    F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0),   "1", F_ALIAS, v6 }, /* flush rs1+0 */
        !           493: { "iflush",    F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0,       "i", F_ALIAS, v6 },
        !           494: { "iflush",    F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),              "1+i", F_ALIAS, v6 },
        !           495: { "iflush",    F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),              "i+1", F_ALIAS, v6 },
        !           496: 
        !           497: 
        !           498: 
        !           499: { "stbar",     F3(2, 0x28, 0)|RS1(0xf), F3(~2, ~0x28, ~0)|RD_G0|RS1(~0xf)|SIMM13(~0),  "", 0, v8 },
        !           500: 
        !           501: 
        !           502:  /* The 1<<12 is a long story.  It is necessary.  For more info, please contact [email protected] */
        !           503: { "sll",       F3(2, 0x25, 0), F3(~2, ~0x25, ~0)|(1<<12)|ASI(~0),      "1,2,d", 0, v6 },
        !           504: { "sll",       F3(2, 0x25, 1), F3(~2, ~0x25, ~1)|(1<<12),              "1,i,d", 0, v6 },
        !           505: { "sra",       F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0),      "1,2,d", 0, v6 },
        !           506: { "sra",       F3(2, 0x27, 1), F3(~2, ~0x27, ~1)|(1<<12),              "1,i,d", 0, v6 },
        !           507: { "srl",       F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0),      "1,2,d", 0, v6 },
        !           508: { "srl",       F3(2, 0x26, 1), F3(~2, ~0x26, ~1)|(1<<12),              "1,i,d", 0, v6 },
        !           509: 
        !           510: 
        !           511: { "mulscc",    F3(2, 0x24, 0), F3(~2, ~0x24, ~0)|ASI(~0),      "1,2,d", 0, v6 },
        !           512: { "mulscc",    F3(2, 0x24, 1), F3(~2, ~0x24, ~1),              "1,i,d", 0, v6 },
        !           513: 
        !           514: { "divscc",    F3(2, 0x1d, 0), F3(~2, ~0x1d, ~0)|ASI(~0),      "1,2,d", 0, sparclite },
        !           515: { "divscc",    F3(2, 0x1d, 1), F3(~2, ~0x1d, ~1),              "1,i,d", 0, sparclite },
        !           516: 
        !           517: { "scan",      F3(2, 0x2c, 0), F3(~2, ~0x2c, ~0)|ASI(~0),      "1,2,d", 0, sparclite },
        !           518: { "scan",      F3(2, 0x2c, 1), F3(~2, ~0x2c, ~1),              "1,i,d", 0, sparclite },
        !           519: 
        !           520: 
        !           521: { "clr",       F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RD_G0|RS1_G0|ASI_RS2(~0),     "d", F_ALIAS, v6 }, /* or %g0,%g0,d */
        !           522: { "clr",       F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0|SIMM13(~0),            "d", F_ALIAS, v6 }, /* or %g0,0,d       */
        !           523: { "clr",       F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI(~0),                "[1+2]", F_ALIAS, v6 },
        !           524: { "clr",       F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI_RS2(~0),            "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+%g0] */
        !           525: { "clr",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0,                        "[1+i]", F_ALIAS, v6 },
        !           526: { "clr",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0,                        "[i+1]", F_ALIAS, v6 },
        !           527: { "clr",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|RS1_G0,         "[i]", F_ALIAS, v6 },
        !           528: { "clr",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|SIMM13(~0),             "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+0] */
        !           529: 
        !           530: { "clrb",      F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI(~0),        "[1+2]", F_ALIAS, v6 },
        !           531: { "clrb",      F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI_RS2(~0),    "[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+%g0] */
        !           532: { "clrb",      F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0,                "[1+i]", F_ALIAS, v6 },
        !           533: { "clrb",      F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0,                "[i+1]", F_ALIAS, v6 },
        !           534: { "clrb",      F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 },
        !           535: { "clrb",      F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|SIMM13(~0),     "[1]", F_ALIAS, v6 }, /* clrb [rs1+0],d */
        !           536: 
        !           537: { "clrh",      F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI(~0),        "[1+2]", F_ALIAS, v6 },
        !           538: { "clrh",      F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI_RS2(~0),    "[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+%g0] */
        !           539: { "clrh",      F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0,                "[1+i]", F_ALIAS, v6 },
        !           540: { "clrh",      F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0,                "[i+1]", F_ALIAS, v6 },
        !           541: { "clrh",      F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 },
        !           542: { "clrh",      F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|SIMM13(~0),     "[1]", F_ALIAS, v6 }, /* clrb [rs1+0],d */
        !           543: 
        !           544: { "orcc",      F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|ASI(~0),      "1,2,d", 0, v6 },
        !           545: { "orcc",      F3(2, 0x12, 1), F3(~2, ~0x12, ~1),              "1,i,d", 0, v6 },
        !           546: { "orcc",      F3(2, 0x12, 1), F3(~2, ~0x12, ~1),              "i,1,d", 0, v6 },
        !           547: 
        !           548: /* This is not a commutative instruction.  */
        !           549: { "orncc",     F3(2, 0x16, 0), F3(~2, ~0x16, ~0)|ASI(~0),      "1,2,d", 0, v6 },
        !           550: { "orncc",     F3(2, 0x16, 1), F3(~2, ~0x16, ~1),              "1,i,d", 0, v6 },
        !           551: 
        !           552: /* This is not a commutative instruction.  */
        !           553: { "orn",       F3(2, 0x06, 0), F3(~2, ~0x06, ~0)|ASI(~0),      "1,2,d", 0, v6 },
        !           554: { "orn",       F3(2, 0x06, 1), F3(~2, ~0x06, ~1),              "1,i,d", 0, v6 },
        !           555: 
        !           556: { "tst",       F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|ASI_RS2(~0),    "1", 0, v6 }, /* orcc rs1, %g0, %g0 */
        !           557: { "tst",       F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|RS1_G0|ASI(~0), "2", 0, v6 }, /* orcc %g0, rs2, %g0 */
        !           558: { "tst",       F3(2, 0x12, 1), F3(~2, ~0x12, ~1)|RD_G0|SIMM13(~0),     "1", 0, v6 }, /* orcc rs1, 0, %g0 */
        !           559: 
        !           560: { "wr",        F3(2, 0x30, 0),         F3(~2, ~0x30, ~0)|ASI(~0),              "1,2,m", 0, v8 }, /* wr r,r,%asrX */
        !           561: { "wr",        F3(2, 0x30, 0),         F3(~2, ~0x30, ~0)|RD_G0|ASI(~0),        "1,2,y", 0, v6 }, /* wr r,r,%y */
        !           562: { "wr",        F3(2, 0x30, 1),         F3(~2, ~0x30, ~1),                      "1,i,m", 0, v8 }, /* wr r,i,%asrX */
        !           563: { "wr",        F3(2, 0x30, 1),         F3(~2, ~0x30, ~1)|RD_G0,                "1,i,y", 0, v6 }, /* wr r,i,%y */
        !           564: { "wr",        F3(2, 0x31, 0),         F3(~2, ~0x31, ~0)|RD_G0|ASI(~0),        "1,2,p", F_ALIAS, v6 }, /* wr r,r,%psr */
        !           565: { "wr",        F3(2, 0x31, 1),         F3(~2, ~0x31, ~1)|RD_G0,                "1,i,p", F_ALIAS, v6 }, /* wr r,i,%psr */
        !           566: { "wr",        F3(2, 0x32, 0),         F3(~2, ~0x32, ~0)|RD_G0|ASI(~0),        "1,2,w", F_ALIAS, v6 }, /* wr r,r,%wim */
        !           567: { "wr",        F3(2, 0x32, 1),         F3(~2, ~0x32, ~1)|RD_G0,                "1,i,w", F_ALIAS, v6 }, /* wr r,i,%wim */
        !           568: { "wr",        F3(2, 0x33, 0),         F3(~2, ~0x33, ~0)|RD_G0|ASI(~0),        "1,2,t", F_ALIAS, v6 }, /* wr r,r,%tbr */
        !           569: { "wr",        F3(2, 0x33, 1),         F3(~2, ~0x33, ~1)|RD_G0,                "1,i,t", F_ALIAS, v6 }, /* wr r,i,%tbr */
        !           570: 
        !           571: 
        !           572: { "rd",        F3(2, 0x28, 0),                 F3(~2, ~0x28, ~0)|SIMM13(~0),           "M,d", 0, v8 }, /* rd %asrX,r */
        !           573: { "rd",        F3(2, 0x28, 0),                 F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0),    "y,d", 0, v6 }, /* rd %y,r */
        !           574: { "rd",        F3(2, 0x29, 0),                 F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0),    "p,d", F_ALIAS, v6 }, /* rd %psr,r */
        !           575: { "rd",        F3(2, 0x2a, 0),                 F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0),    "w,d", F_ALIAS, v6 }, /* rd %wim,r */
        !           576: { "rd",        F3(2, 0x2b, 0),                 F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0),    "t,d", F_ALIAS, v6 }, /* rd %tbr,r */
        !           577: 
        !           578: 
        !           579: 
        !           580: { "mov",       F3(2, 0x30, 0),         F3(~2, ~0x30, ~0)|ASI(~0),              "1,2,m", F_ALIAS, v8 }, /* wr r,r,%asrX */
        !           581: { "mov",       F3(2, 0x30, 0),         F3(~2, ~0x30, ~0)|RD_G0|ASI(~0),        "1,2,y", F_ALIAS, v6 }, /* wr r,r,%y */
        !           582: { "mov",       F3(2, 0x30, 1),         F3(~2, ~0x30, ~1),                      "1,i,m", F_ALIAS, v8 }, /* wr r,i,%asrX */
        !           583: { "mov",       F3(2, 0x30, 1),         F3(~2, ~0x30, ~1)|RD_G0,                "1,i,y", F_ALIAS, v6 }, /* wr r,i,%y */
        !           584: { "mov",       F3(2, 0x31, 0),         F3(~2, ~0x31, ~0)|RD_G0|ASI(~0),        "1,2,p", F_ALIAS, v6 }, /* wr r,r,%psr */
        !           585: { "mov",       F3(2, 0x31, 1),         F3(~2, ~0x31, ~1)|RD_G0,                "1,i,p", F_ALIAS, v6 }, /* wr r,i,%psr */
        !           586: { "mov",       F3(2, 0x32, 0),         F3(~2, ~0x32, ~0)|RD_G0|ASI(~0),        "1,2,w", F_ALIAS, v6 }, /* wr r,r,%wim */
        !           587: { "mov",       F3(2, 0x32, 1),         F3(~2, ~0x32, ~1)|RD_G0,                "1,i,w", F_ALIAS, v6 }, /* wr r,i,%wim */
        !           588: { "mov",       F3(2, 0x33, 0),         F3(~2, ~0x33, ~0)|RD_G0|ASI(~0),        "1,2,t", F_ALIAS, v6 }, /* wr r,r,%tbr */
        !           589: { "mov",       F3(2, 0x33, 1),         F3(~2, ~0x33, ~1)|RD_G0,                "1,i,t", F_ALIAS, v6 }, /* wr r,i,%tbr */
        !           590: 
        !           591: { "mov",       F3(2, 0x28, 0),          F3(~2, ~0x28, ~0)|SIMM13(~0),                  "M,d", F_ALIAS, v8 }, /* rd %asr1,r */
        !           592: { "mov",       F3(2, 0x28, 0),          F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0),           "y,d", F_ALIAS, v6 }, /* rd %y,r */
        !           593: { "mov",       F3(2, 0x29, 0),          F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0),           "p,d", F_ALIAS, v6 }, /* rd %psr,r */
        !           594: { "mov",       F3(2, 0x2a, 0),          F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0),           "w,d", F_ALIAS, v6 }, /* rd %wim,r */
        !           595: { "mov",       F3(2, 0x2b, 0),          F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0),           "t,d", F_ALIAS, v6 }, /* rd %tbr,r */
        !           596: 
        !           597: { "mov",       F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0),  "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */
        !           598: { "mov",       F3(2, 0x30, 1), F3(~2, ~0x30, ~1),              "i,y", F_ALIAS, v6 },
        !           599: { "mov",       F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|SIMM13(~0),   "1,y", F_ALIAS, v6 }, /* wr rs1,0,%y */
        !           600: { "mov",       F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|ASI_RS2(~0),  "1,p", F_ALIAS, v6 }, /* wr rs1,%g0,%psr */
        !           601: { "mov",       F3(2, 0x31, 1), F3(~2, ~0x31, ~1),              "i,p", F_ALIAS, v6 },
        !           602: { "mov",       F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|SIMM13(~0),   "1,p", F_ALIAS, v6 }, /* wr rs1,0,%psr */
        !           603: { "mov",       F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|ASI_RS2(~0),  "1,w", F_ALIAS, v6 }, /* wr rs1,%g0,%wim */
        !           604: { "mov",       F3(2, 0x32, 1), F3(~2, ~0x32, ~1),              "i,w", F_ALIAS, v6 },
        !           605: { "mov",       F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|SIMM13(~0),   "1,w", F_ALIAS, v6 }, /* wr rs1,0,%wim */
        !           606: { "mov",       F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|ASI_RS2(~0),  "1,t", F_ALIAS, v6 }, /* wr rs1,%g0,%tbr */
        !           607: { "mov",       F3(2, 0x33, 1), F3(~2, ~0x33, ~1),              "i,t", F_ALIAS, v6 },
        !           608: { "mov",       F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|SIMM13(~0),   "1,t", F_ALIAS, v6 }, /* wr rs1,0,%tbr */
        !           609: 
        !           610: { "mov",       F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RS1_G0|ASI(~0),       "2,d", 0, v6 }, /* or %g0,rs2,d */
        !           611: { "mov",       F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0,               "i,d", 0, v6 }, /* or %g0,i,d   */
        !           612: { "mov",        F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI_RS2(~0),         "1,d", 0, v6 }, /* or rs1,%g0,d   */
        !           613: { "mov",        F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|SIMM13(~0),          "1,d", 0, v6 }, /* or rs1,0,d */
        !           614: 
        !           615: { "or",        F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0),      "1,2,d", 0, v6 },
        !           616: { "or",        F3(2, 0x02, 1), F3(~2, ~0x02, ~1),              "1,i,d", 0, v6 },
        !           617: { "or",        F3(2, 0x02, 1), F3(~2, ~0x02, ~1),              "i,1,d", 0, v6 },
        !           618: 
        !           619: { "bset",      F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0),      "2,r", F_ALIAS, v6 },   /* or rd,rs2,rd */
        !           620: { "bset",      F3(2, 0x02, 1), F3(~2, ~0x02, ~1),              "i,r", F_ALIAS, v6 },   /* or rd,i,rd */
        !           621: 
        !           622: /* This is not a commutative instruction.  */
        !           623: { "andn",      F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0),      "1,2,d", 0, v6 },
        !           624: { "andn",      F3(2, 0x05, 1), F3(~2, ~0x05, ~1),              "1,i,d", 0, v6 },
        !           625: 
        !           626: /* This is not a commutative instruction.  */
        !           627: { "andncc",    F3(2, 0x15, 0), F3(~2, ~0x15, ~0)|ASI(~0),      "1,2,d", 0, v6 },
        !           628: { "andncc",    F3(2, 0x15, 1), F3(~2, ~0x15, ~1),              "1,i,d", 0, v6 },
        !           629: 
        !           630: { "bclr",      F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0),      "2,r", F_ALIAS, v6 },   /* andn rd,rs2,rd */
        !           631: { "bclr",      F3(2, 0x05, 1), F3(~2, ~0x05, ~1),              "i,r", F_ALIAS, v6 },   /* andn rd,i,rd */
        !           632: 
        !           633: { "cmp",       F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|RD_G0|ASI(~0),        "1,2", 0, v6 }, /* subcc rs1,rs2,%g0 */
        !           634: { "cmp",       F3(2, 0x14, 1), F3(~2, ~0x14, ~1)|RD_G0,                "1,i", 0, v6 }, /* subcc rs1,i,%g0 */
        !           635: 
        !           636: { "sub",       F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|ASI(~0),      "1,2,d", 0, v6 },
        !           637: { "sub",       F3(2, 0x04, 1), F3(~2, ~0x04, ~1),              "1,i,d", 0, v6 },
        !           638: 
        !           639: { "subcc",     F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|ASI(~0),      "1,2,d", 0, v6 },
        !           640: { "subcc",     F3(2, 0x14, 1), F3(~2, ~0x14, ~1),              "1,i,d", 0, v6 },
        !           641: 
        !           642: { "subx",      F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0),      "1,2,d", F_ALIAS, v6 },
        !           643: { "subx",      F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1),              "1,i,d", F_ALIAS, v6 },
        !           644: 
        !           645: { "subxcc",    F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0),      "1,2,d", F_ALIAS, v6 },
        !           646: { "subxcc",    F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1),              "1,i,d", F_ALIAS, v6 },
        !           647: 
        !           648: { "and",       F3(2, 0x01, 0), F3(~2, ~0x01, ~0)|ASI(~0),      "1,2,d", 0, v6 },
        !           649: { "and",       F3(2, 0x01, 1), F3(~2, ~0x01, ~1),              "1,i,d", 0, v6 },
        !           650: { "and",       F3(2, 0x01, 1), F3(~2, ~0x01, ~1),              "i,1,d", 0, v6 },
        !           651: 
        !           652: { "andcc",     F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|ASI(~0),      "1,2,d", 0, v6 },
        !           653: { "andcc",     F3(2, 0x11, 1), F3(~2, ~0x11, ~1),              "1,i,d", 0, v6 },
        !           654: { "andcc",     F3(2, 0x11, 1), F3(~2, ~0x11, ~1),              "i,1,d", 0, v6 },
        !           655: 
        !           656: { "dec",       F3(2, 0x04, 1)|SIMM13(0x1), F3(~2, ~0x04, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 },      /* sub rd,1,rd */
        !           657: { "dec",       F3(2, 0x04, 1),             F3(~2, ~0x04, ~1),                 "i,r", F_ALIAS, v8 },    /* sub rd,imm,rd */
        !           658: { "deccc",     F3(2, 0x14, 1)|SIMM13(0x1), F3(~2, ~0x14, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 },      /* subcc rd,1,rd */
        !           659: { "deccc",     F3(2, 0x14, 1),             F3(~2, ~0x14, ~1),                 "i,r", F_ALIAS, v8 },    /* subcc rd,imm,rd */
        !           660: { "inc",       F3(2, 0x00, 1)|SIMM13(0x1), F3(~2, ~0x00, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 },      /* add rd,1,rd */
        !           661: { "inc",       F3(2, 0x00, 1),             F3(~2, ~0x00, ~1),                 "i,r", F_ALIAS, v8 },    /* add rd,imm,rd */
        !           662: { "inccc",     F3(2, 0x10, 1)|SIMM13(0x1), F3(~2, ~0x10, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 },      /* addcc rd,1,rd */
        !           663: { "inccc",     F3(2, 0x10, 1),             F3(~2, ~0x10, ~1),                 "i,r", F_ALIAS, v8 },    /* addcc rd,imm,rd */
        !           664: 
        !           665: { "btst",      F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|RD_G0|ASI(~0), "1,2", F_ALIAS, v6 },  /* andcc rs1,rs2,%g0 */
        !           666: { "btst",      F3(2, 0x11, 1), F3(~2, ~0x11, ~1)|RD_G0, "i,1", F_ALIAS, v6 },  /* andcc rs1,i,%g0 */
        !           667: 
        !           668: { "neg",       F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "2,d", F_ALIAS, v6 }, /* sub %g0,rs2,rd */
        !           669: { "neg",       F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "u", F_ALIAS, v6 }, /* sub %g0,rd,rd */
        !           670: 
        !           671: { "add",       F3(2, 0x00, 0), F3(~2, ~0x00, ~0)|ASI(~0),      "1,2,d", 0, v6 },
        !           672: { "add",       F3(2, 0x00, 1), F3(~2, ~0x00, ~1),              "1,i,d", 0, v6 },
        !           673: { "add",       F3(2, 0x00, 1), F3(~2, ~0x00, ~1),              "i,1,d", 0, v6 },
        !           674: { "addcc",     F3(2, 0x10, 0), F3(~2, ~0x10, ~0)|ASI(~0),      "1,2,d", 0, v6 },
        !           675: { "addcc",     F3(2, 0x10, 1), F3(~2, ~0x10, ~1),              "1,i,d", 0, v6 },
        !           676: { "addcc",     F3(2, 0x10, 1), F3(~2, ~0x10, ~1),              "i,1,d", 0, v6 },
        !           677: { "addx",      F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0),      "1,2,d", F_ALIAS, v6 },
        !           678: { "addx",      F3(2, 0x08, 1), F3(~2, ~0x08, ~1),              "1,i,d", F_ALIAS, v6 },
        !           679: { "addx",      F3(2, 0x08, 1), F3(~2, ~0x08, ~1),              "i,1,d", F_ALIAS, v6 },
        !           680: { "addxcc",    F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0),      "1,2,d", F_ALIAS, v6 },
        !           681: { "addxcc",    F3(2, 0x18, 1), F3(~2, ~0x18, ~1),              "1,i,d", F_ALIAS, v6 },
        !           682: { "addxcc",    F3(2, 0x18, 1), F3(~2, ~0x18, ~1),              "i,1,d", F_ALIAS, v6 },
        !           683: 
        !           684: { "smul",      F3(2, 0x0b, 0), F3(~2, ~0x0b, ~0)|ASI(~0),      "1,2,d", 0, v8 },
        !           685: { "smul",      F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1),              "1,i,d", 0, v8 },
        !           686: { "smul",      F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1),              "i,1,d", 0, v8 },
        !           687: { "smulcc",    F3(2, 0x1b, 0), F3(~2, ~0x1b, ~0)|ASI(~0),      "1,2,d", 0, v8 },
        !           688: { "smulcc",    F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1),              "1,i,d", 0, v8 },
        !           689: { "smulcc",    F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1),              "i,1,d", 0, v8 },
        !           690: { "umul",      F3(2, 0x0a, 0), F3(~2, ~0x0a, ~0)|ASI(~0),      "1,2,d", 0, v8 },
        !           691: { "umul",      F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1),              "1,i,d", 0, v8 },
        !           692: { "umul",      F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1),              "i,1,d", 0, v8 },
        !           693: { "umulcc",    F3(2, 0x1a, 0), F3(~2, ~0x1a, ~0)|ASI(~0),      "1,2,d", 0, v8 },
        !           694: { "umulcc",    F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1),              "1,i,d", 0, v8 },
        !           695: { "umulcc",    F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1),              "i,1,d", 0, v8 },
        !           696: { "sdiv",      F3(2, 0x0f, 0), F3(~2, ~0x0f, ~0)|ASI(~0),      "1,2,d", 0, v8 },
        !           697: { "sdiv",      F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1),              "1,i,d", 0, v8 },
        !           698: { "sdiv",      F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1),              "i,1,d", 0, v8 },
        !           699: { "sdivcc",    F3(2, 0x1f, 0), F3(~2, ~0x1f, ~0)|ASI(~0),      "1,2,d", 0, v8 },
        !           700: { "sdivcc",    F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1),              "1,i,d", 0, v8 },
        !           701: { "sdivcc",    F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1),              "i,1,d", 0, v8 },
        !           702: { "udiv",      F3(2, 0x0e, 0), F3(~2, ~0x0e, ~0)|ASI(~0),      "1,2,d", 0, v8 },
        !           703: { "udiv",      F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1),              "1,i,d", 0, v8 },
        !           704: { "udiv",      F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1),              "i,1,d", 0, v8 },
        !           705: { "udivcc",    F3(2, 0x1e, 0), F3(~2, ~0x1e, ~0)|ASI(~0),      "1,2,d", 0, v8 },
        !           706: { "udivcc",    F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1),              "1,i,d", 0, v8 },
        !           707: { "udivcc",    F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1),              "i,1,d", 0, v8 },
        !           708: 
        !           709: 
        !           710: { "call",      F1(0x1), F1(~0x1), "L", F_JSR|F_DELAYED, v6 },
        !           711: { "call",      F1(0x1), F1(~0x1), "L,#", F_JSR|F_DELAYED, v6 },
        !           712: 
        !           713: { "call",      F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0),     "1+2", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%o7 */
        !           714: { "call",      F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0),     "1+2,#", F_JSR|F_DELAYED, v6 },
        !           715: { "call",      F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%o7 */
        !           716: { "call",      F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1,#", F_JSR|F_DELAYED, v6 },
        !           717: { "call",      F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf),             "1+i", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+i,%o7 */
        !           718: { "call",      F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf),             "1+i,#", F_JSR|F_DELAYED, v6 },
        !           719: { "call",      F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf),             "i+1", F_JSR|F_DELAYED, v6 }, /* jmpl i+rs1,%o7 */
        !           720: { "call",      F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf),             "i+1,#", F_JSR|F_DELAYED, v6 },
        !           721: { "call",      F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0,      "i", F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,%o7 */
        !           722: { "call",      F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0,      "i,#", F_JSR|F_DELAYED, v6 },
        !           723: { "call",      F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0),  "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,%o7 */
        !           724: { "call",      F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0),  "1,#", F_JSR|F_DELAYED, v6 },
        !           725: 
        !           726: 
        !           727: /* Conditional instructions.
        !           728: 
        !           729:    Because this part of the table was such a mess earlier, I have
        !           730:    macrofied it so that all the branches and traps are generated from
        !           731:    a single-line description of each condition value.  John Gilmore. */
        !           732: 
        !           733: /* Define branches -- one annulled, one without, etc. */
        !           734: #define br(opcode, mask, lose, flags) \
        !           735:  { opcode, (mask)|ANNUL, (lose),       ",a l",   (flags), v6 }, \
        !           736:  { opcode, (mask)      , (lose)|ANNUL, "l",     (flags), v6 }
        !           737: 
        !           738: 
        !           739: /* Define four traps: reg+reg, reg + immediate, immediate alone, reg alone. */
        !           740: #define tr(opcode, mask, lose, flags) \
        !           741:  { opcode, (mask)|IMMED, (lose)|RS1_G0,                "i",     (flags), v6 }, /* %g0 + imm */ \
        !           742:  { opcode, (mask)|IMMED, (lose),               "1+i",   (flags), v6 }, /* rs1 + imm */ \
        !           743:  { opcode, (mask), IMMED|(lose),               "1+2",   (flags), v6 }, /* rs1 + rs2 */ \
        !           744:  { opcode, (mask), IMMED|(lose)|RS2_G0,                "1",     (flags), v6 } /* rs1 + %g0 */
        !           745: 
        !           746: 
        !           747: /* Define both branches and traps based on condition mask */
        !           748: #define cond(bop, top, mask, flags) \
        !           749:   br(bop,  F2(0, 2)|(mask), F2(~0, ~2)|((~mask)&COND(~0)), F_DELAYED|(flags)), \
        !           750:   tr(top,  F3(2, 0x3a, 0)|(mask), F3(~2, ~0x3a, 0)|((~mask)&COND(~0)), ((flags) & ~(F_UNBR|F_CONDBR)))
        !           751: 
        !           752: /* Define all the conditions, all the branches, all the traps.  */
        !           753: 
        !           754: /* Standard branch, trap mnemonics */
        !           755: cond ("b",     "ta",   CONDA, F_UNBR),
        !           756: /* Alternative form (just for assembly, not for disassembly) */
        !           757: cond ("ba",    "t",    CONDA, F_UNBR|F_ALIAS),
        !           758: 
        !           759: cond ("bcc",   "tcc",  CONDCC, F_CONDBR),
        !           760: cond ("bcs",   "tcs",  CONDCS, F_CONDBR),
        !           761: cond ("be",    "te",   CONDE, F_CONDBR),
        !           762: cond ("bg",    "tg",   CONDG, F_CONDBR),
        !           763: cond ("bgt",   "tgt",   CONDG, F_CONDBR|F_ALIAS),
        !           764: cond ("bge",   "tge",  CONDGE, F_CONDBR),
        !           765: cond ("bgeu",  "tgeu", CONDGEU, F_CONDBR|F_ALIAS), /* for cc */
        !           766: cond ("bgu",   "tgu",  CONDGU, F_CONDBR),
        !           767: cond ("bl",    "tl",   CONDL, F_CONDBR),
        !           768: cond ("blt",   "tlt",   CONDL, F_CONDBR|F_ALIAS),
        !           769: cond ("ble",   "tle",  CONDLE, F_CONDBR),
        !           770: cond ("bleu",  "tleu", CONDLEU, F_CONDBR),
        !           771: cond ("blu",   "tlu",  CONDLU, F_CONDBR|F_ALIAS), /* for cs */
        !           772: cond ("bn",    "tn",   CONDN, F_CONDBR),
        !           773: cond ("bne",   "tne",  CONDNE, F_CONDBR),
        !           774: cond ("bneg",  "tneg", CONDNEG, F_CONDBR),
        !           775: cond ("bnz",   "tnz",  CONDNZ, F_CONDBR|F_ALIAS), /* for ne */
        !           776: cond ("bpos",  "tpos", CONDPOS, F_CONDBR),
        !           777: cond ("bvc",   "tvc",  CONDVC, F_CONDBR),
        !           778: cond ("bvs",   "tvs",  CONDVS, F_CONDBR),
        !           779: cond ("bz",    "tz",   CONDZ, F_CONDBR|F_ALIAS), /* for e */
        !           780: 
        !           781: #undef cond
        !           782: #undef br
        !           783: #undef tr
        !           784: 
        !           785: 
        !           786: 
        !           787: 
        !           788: 
        !           789: 
        !           790: 
        !           791: 
        !           792: 
        !           793: 
        !           794: 
        !           795: 
        !           796: 
        !           797: 
        !           798: 
        !           799: 
        !           800: 
        !           801: 
        !           802: 
        !           803: 
        !           804: 
        !           805: 
        !           806: 
        !           807: 
        !           808: #define brfc(opcode, mask, lose, flags) \
        !           809:  { opcode, (mask), ANNUL|(lose), "l",    flags|F_DELAYED, v6 }, \
        !           810:  { opcode, (mask)|ANNUL, (lose), ",a l", flags|F_DELAYED, v6 }
        !           811: 
        !           812: 
        !           813: 
        !           814: #define condfc(fop, cop, mask, flags) \
        !           815:   brfc(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \
        !           816:   brfc(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags)
        !           817: 
        !           818: #define condf(fop, mask, flags) \
        !           819:   brfc(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags)
        !           820: 
        !           821: condfc("fb",   "cb",    0x8, 0),
        !           822: condfc("fba",  "cba",   0x8, F_ALIAS),
        !           823: condfc("fbe",  "cb0",   0x9, 0),
        !           824: condf("fbz",            0x9, F_ALIAS),
        !           825: condfc("fbg",  "cb2",   0x6, 0),
        !           826: condfc("fbge", "cb02",  0xb, 0),
        !           827: condfc("fbl",  "cb1",   0x4, 0),
        !           828: condfc("fble", "cb01",  0xd, 0),
        !           829: condfc("fblg", "cb12",  0x2, 0),
        !           830: condfc("fbn",  "cbn",   0x0, 0),
        !           831: condfc("fbne", "cb123", 0x1, 0),
        !           832: condf("fbnz",           0x1, F_ALIAS),
        !           833: condfc("fbo",  "cb012", 0xf, 0),
        !           834: condfc("fbu",  "cb3",   0x7, 0),
        !           835: condfc("fbue", "cb03",  0xa, 0),
        !           836: condfc("fbug", "cb23",  0x5, 0),
        !           837: condfc("fbuge",        "cb023", 0xc, 0),
        !           838: condfc("fbul", "cb13",  0x3, 0),
        !           839: condfc("fbule",        "cb013", 0xe, 0),
        !           840: 
        !           841: #undef condfc
        !           842: #undef brfc
        !           843: 
        !           844: { "jmp",       F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI(~0),        "1+2", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%g0 */
        !           845: { "jmp",       F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI_RS2(~0),    "1", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%g0 */
        !           846: { "jmp",       F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0,                "1+i", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+i,%g0 */
        !           847: { "jmp",       F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0,                "i+1", F_UNBR|F_DELAYED, v6 }, /* jmpl i+rs1,%g0 */
        !           848: { "jmp",       F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|RS1_G0,         "i", F_UNBR|F_DELAYED, v6 }, /* jmpl %g0+i,%g0 */
        !           849: { "jmp",       F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|SIMM13(~0),     "1", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+0,%g0 */
        !           850: 
        !           851: { "nop",       F2(0, 4), 0xfeffffff, "", 0, v6 }, /* sethi 0, %g0 */
        !           852: 
        !           853: { "set",       F2(0x0, 0x4), F2(~0x0, ~0x4), "Sh,d", F_ALIAS, v6 },
        !           854: 
        !           855: { "sethi",     F2(0x0, 0x4), F2(~0x0, ~0x4), "h,d", 0, v6 },
        !           856: 
        !           857: { "taddcc",    F3(2, 0x20, 0), F3(~2, ~0x20, ~0)|ASI(~0),      "1,2,d", 0, v6 },
        !           858: { "taddcc",    F3(2, 0x20, 1), F3(~2, ~0x20, ~1),              "1,i,d", 0, v6 },
        !           859: { "taddcc",    F3(2, 0x20, 1), F3(~2, ~0x20, ~1),              "i,1,d", 0, v6 },
        !           860: { "taddcctv",  F3(2, 0x22, 0), F3(~2, ~0x22, ~0)|ASI(~0),      "1,2,d", 0, v6 },
        !           861: { "taddcctv",  F3(2, 0x22, 1), F3(~2, ~0x22, ~1),              "1,i,d", 0, v6 },
        !           862: { "taddcctv",  F3(2, 0x22, 1), F3(~2, ~0x22, ~1),              "i,1,d", 0, v6 },
        !           863: 
        !           864: { "tsubcc",    F3(2, 0x21, 0), F3(~2, ~0x21, ~0)|ASI(~0),      "1,2,d", 0, v6 },
        !           865: { "tsubcc",    F3(2, 0x21, 1), F3(~2, ~0x21, ~1),              "1,i,d", 0, v6 },
        !           866: { "tsubcctv",  F3(2, 0x23, 0), F3(~2, ~0x23, ~0)|ASI(~0),      "1,2,d", 0, v6 },
        !           867: { "tsubcctv",  F3(2, 0x23, 1), F3(~2, ~0x23, ~1),              "1,i,d", 0, v6 },
        !           868: 
        !           869: { "unimp",     F2(0x0, 0x0), 0xffc00000, "n", F_ALIAS, v6 },
        !           870: 
        !           871: /* This *is* a commutative instruction.  */
        !           872: { "xnor",      F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0),      "1,2,d", 0, v6 },
        !           873: { "xnor",      F3(2, 0x07, 1), F3(~2, ~0x07, ~1),              "1,i,d", 0, v6 },
        !           874: { "xnor",      F3(2, 0x07, 1), F3(~2, ~0x07, ~1),              "i,1,d", 0, v6 },
        !           875: /* This *is* a commutative instruction.  */
        !           876: { "xnorcc",    F3(2, 0x17, 0), F3(~2, ~0x17, ~0)|ASI(~0),      "1,2,d", 0, v6 },
        !           877: { "xnorcc",    F3(2, 0x17, 1), F3(~2, ~0x17, ~1),              "1,i,d", 0, v6 },
        !           878: { "xnorcc",    F3(2, 0x17, 1), F3(~2, ~0x17, ~1),              "i,1,d", 0, v6 },
        !           879: { "xor",       F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0),      "1,2,d", 0, v6 },
        !           880: { "xor",       F3(2, 0x03, 1), F3(~2, ~0x03, ~1),              "1,i,d", 0, v6 },
        !           881: { "xor",       F3(2, 0x03, 1), F3(~2, ~0x03, ~1),              "i,1,d", 0, v6 },
        !           882: { "xorcc",     F3(2, 0x13, 0), F3(~2, ~0x13, ~0)|ASI(~0),      "1,2,d", 0, v6 },
        !           883: { "xorcc",     F3(2, 0x13, 1), F3(~2, ~0x13, ~1),              "1,i,d", 0, v6 },
        !           884: { "xorcc",     F3(2, 0x13, 1), F3(~2, ~0x13, ~1),              "i,1,d", 0, v6 },
        !           885: 
        !           886: { "not",       F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,d", F_ALIAS, v6 }, /* xnor rs1,%0,rd */
        !           887: { "not",       F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "r", F_ALIAS, v6 }, /* xnor rd,%0,rd */
        !           888: 
        !           889: { "btog",      F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0),      "2,r", F_ALIAS, v6 }, /* xor rd,rs2,rd */
        !           890: { "btog",      F3(2, 0x03, 1), F3(~2, ~0x03, ~1),              "i,r", F_ALIAS, v6 }, /* xor rd,i,rd */
        !           891: 
        !           892: /* FPop1 and FPop2 are not instructions.  Don't accept them.  */
        !           893: 
        !           894: { "fdtoi",     F3F(2, 0x34, 0x0d2), F3F(~2, ~0x34, ~0x0d2)|RS1_G0, "B,g", 0, v6 },
        !           895: { "fstoi",     F3F(2, 0x34, 0x0d1), F3F(~2, ~0x34, ~0x0d1)|RS1_G0, "f,g", 0, v6 },
        !           896: { "fqtoi",     F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0, "R,g", 0, v8 },
        !           897: 
        !           898: 
        !           899: { "fitod",     F3F(2, 0x34, 0x0c8), F3F(~2, ~0x34, ~0x0c8)|RS1_G0, "f,H", 0, v6 },
        !           900: { "fitos",     F3F(2, 0x34, 0x0c4), F3F(~2, ~0x34, ~0x0c4)|RS1_G0, "f,g", 0, v6 },
        !           901: { "fitoq",     F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0, "f,J", 0, v8 },
        !           902: 
        !           903: 
        !           904: { "fdtoq",     F3F(2, 0x34, 0x0ce), F3F(~2, ~0x34, ~0x0ce)|RS1_G0, "B,J", 0, v8 },
        !           905: { "fdtos",     F3F(2, 0x34, 0x0c6), F3F(~2, ~0x34, ~0x0c6)|RS1_G0, "B,g", 0, v6 },
        !           906: { "fqtod",     F3F(2, 0x34, 0x0cb), F3F(~2, ~0x34, ~0x0cb)|RS1_G0, "R,H", 0, v8 },
        !           907: { "fqtos",     F3F(2, 0x34, 0x0c7), F3F(~2, ~0x34, ~0x0c7)|RS1_G0, "R,g", 0, v8 },
        !           908: { "fstod",     F3F(2, 0x34, 0x0c9), F3F(~2, ~0x34, ~0x0c9)|RS1_G0, "f,H", 0, v6 },
        !           909: { "fstoq",     F3F(2, 0x34, 0x0cd), F3F(~2, ~0x34, ~0x0cd)|RS1_G0, "f,J", 0, v8 },
        !           910: 
        !           911: { "fdivd",     F3F(2, 0x34, 0x04e), F3F(~2, ~0x34, ~0x04e), "v,B,H", 0, v6 },
        !           912: { "fdivq",     F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", 0, v8 },
        !           913: { "fdivs",     F3F(2, 0x34, 0x04d), F3F(~2, ~0x34, ~0x04d), "e,f,g", 0, v6 },
        !           914: { "fmuld",     F3F(2, 0x34, 0x04a), F3F(~2, ~0x34, ~0x04a), "v,B,H", 0, v6 },
        !           915: { "fmulq",     F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", 0, v8 },
        !           916: { "fmuls",     F3F(2, 0x34, 0x049), F3F(~2, ~0x34, ~0x049), "e,f,g", 0, v6 },
        !           917: 
        !           918: { "fdmulq",    F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", 0, v8 },
        !           919: { "fsmuld",    F3F(2, 0x34, 0x069), F3F(~2, ~0x34, ~0x069), "e,f,H", 0, v8 },
        !           920: 
        !           921: { "fsqrtd",    F3F(2, 0x34, 0x02a), F3F(~2, ~0x34, ~0x02a)|RS1_G0, "B,H", 0, v7 },
        !           922: { "fsqrtq",    F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", 0, v8 },
        !           923: { "fsqrts",    F3F(2, 0x34, 0x029), F3F(~2, ~0x34, ~0x029)|RS1_G0, "f,g", 0, v7 },
        !           924: 
        !           925: { "fabss",     F3F(2, 0x34, 0x009), F3F(~2, ~0x34, ~0x009)|RS1_G0, "f,g", 0, v6 },
        !           926: { "fmovs",     F3F(2, 0x34, 0x001), F3F(~2, ~0x34, ~0x001)|RS1_G0, "f,g", 0, v6 },
        !           927: { "fnegs",     F3F(2, 0x34, 0x005), F3F(~2, ~0x34, ~0x005)|RS1_G0, "f,g", 0, v6 },
        !           928: 
        !           929: { "faddd",     F3F(2, 0x34, 0x042), F3F(~2, ~0x34, ~0x042), "v,B,H", 0, v6 },
        !           930: { "faddq",     F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", 0, v8 },
        !           931: { "fadds",     F3F(2, 0x34, 0x041), F3F(~2, ~0x34, ~0x041), "e,f,g", 0, v6 },
        !           932: { "fsubd",     F3F(2, 0x34, 0x046), F3F(~2, ~0x34, ~0x046), "v,B,H", 0, v6 },
        !           933: { "fsubq",     F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", 0, v8 },
        !           934: { "fsubs",     F3F(2, 0x34, 0x045), F3F(~2, ~0x34, ~0x045), "e,f,g", 0, v6 },
        !           935: 
        !           936: #define CMPFCC(x)      (((x)&0x3)<<25)
        !           937: 
        !           938: { "fcmpd",               F3F(2, 0x35, 0x052),            F3F(~2, ~0x35, ~0x052)|RD_G0,  "v,B",   0, v6 },
        !           939: { "fcmped",              F3F(2, 0x35, 0x056),            F3F(~2, ~0x35, ~0x056)|RD_G0,  "v,B",   0, v6 },
        !           940: { "fcmpq",               F3F(2, 0x34, 0x053),            F3F(~2, ~0x34, ~0x053)|RD_G0,  "V,R", 0, v8 },
        !           941: { "fcmpeq",              F3F(2, 0x34, 0x057),            F3F(~2, ~0x34, ~0x057)|RD_G0,  "V,R", 0, v8 },
        !           942: { "fcmps",               F3F(2, 0x35, 0x051),            F3F(~2, ~0x35, ~0x051)|RD_G0, "e,f",   0, v6 },
        !           943: { "fcmpes",              F3F(2, 0x35, 0x055),            F3F(~2, ~0x35, ~0x055)|RD_G0, "e,f",   0, v6 },
        !           944: 
        !           945: { "cpop1",     F3(2, 0x36, 0), F3(~2, ~0x36, ~1), "[1+2],d", F_ALIAS, v6 },
        !           946: { "cpop2",     F3(2, 0x37, 0), F3(~2, ~0x37, ~1), "[1+2],d", F_ALIAS, v6 },
        !           947: 
        !           948:     
        !           949: 
        !           950: };
        !           951: 
        !           952: const int bfd_sparc_num_opcodes = ((sizeof sparc_opcodes)/(sizeof sparc_opcodes[0]));

This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.