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Annotation of GNUtools/cctools/include/architecture/m98k/m98601_regs.h, revision 1.1

1.1     ! root        1: /* Copyright (c) 1992 NeXT Computer, Inc.  All rights reserved.
        !             2:  *
        !             3:  *     File:   architecture/m98k/m98601_regs.h
        !             4:  *     Author: Ben Fathi, NeXT Computer, Inc.
        !             5:  *
        !             6:  *     M98601-specific registers
        !             7:  *
        !             8:  * HISTORY
        !             9:  * 08-Dec-92  Ben Fathi ([email protected])
        !            10:  *     Added interrpt status registers.
        !            11:  *
        !            12:  * 18-Nov-92  Ben Fathi ([email protected])
        !            13:  *     Created.
        !            14:  */
        !            15: 
        !            16: #ifndef _ARCH_M98K_M98601_REGS_H_
        !            17: #define _ARCH_M98K_M98601_REGS_H_
        !            18: 
        !            19: /*
        !            20:  * Software definitions for m98601-specific registers
        !            21:  */
        !            22: #define SR_M98601_MCHECK       hid0    // machine check status
        !            23: #define SR_M98601_RMI_MODES    hid1    // run and fetch modes
        !            24: #define SR_M98601_RMI_ADDR     hid2    // run mode compare address
        !            25: #define SR_M98601_RMI_DABR     hid5    // data address breakpoint
        !            26: #define SR_M98601_PID          pid     // processor ID
        !            27: #define SR_M98601_MQ           mq      // multiply quotient
        !            28: 
        !            29: /*
        !            30:  * Data Breakpoints
        !            31:  */
        !            32: 
        !            33: #define        M98601_N_DATA_BP        1               // 98601 supports 1 data bp
        !            34: 
        !            35: /*
        !            36:  * Data Breakpoint Address Specification (register HID5 aka DABR)
        !            37:  */
        !            38: typedef        struct {
        !            39:        unsigned        addr:BITS_WIDTH(31,3);  // double-word address
        !            40:        unsigned        rsvd:BIT_WIDTH(2);
        !            41:        unsigned        w:BIT_WIDTH(1);         // 1 => compare on store
        !            42:        unsigned        r:BIT_WIDTH(0);         // 1 => compare on load
        !            43: } m98601_data_bp_addr_t;
        !            44: 
        !            45: /*
        !            46:  * Valid values for "run" bits in m98601_data_bp_mode_t
        !            47:  */
        !            48: #define        M98601_RUN_NORMAL               0
        !            49: #define M98601_RUN_LIMITED_ADDR_CMP    2
        !            50: #define M98601_RUN_SINGLE_INSTR_STEP   4
        !            51: #define M98601_RUN_FULL_ADDR_CMP       6
        !            52: #define M98601_RUN_FULL_BRANCH_TARG_CMP        7
        !            53: 
        !            54: /*
        !            55:  * Valid values for "resp" bits in m98601_data_bp_mode_t
        !            56:  */
        !            57: #define        M98601_RESP_HARD_STOP           0
        !            58: #define        M98601_RESP_SOFT_STOP           1
        !            59: #define        M98601_RESP_TRAP                2
        !            60: 
        !            61: /*
        !            62:  * Data Breakpoint Mode Specification (register HID1)
        !            63:  */
        !            64: typedef        struct {
        !            65:        unsigned        :BIT_WIDTH(31);
        !            66:        unsigned        run:BITS_WIDTH(30,28);          // see above
        !            67:        unsigned        :BITS_WIDTH(27,24);
        !            68:        unsigned        resp:BITS_WIDTH(23,22);         // see above
        !            69:        unsigned        scan:BIT_WIDTH(21);             // not for sw use
        !            70:        unsigned        :BITS_WIDTH(20,15);
        !            71:        unsigned        no_brd_tlbi:BIT_WIDTH(14);      // if high, don't
        !            72:                                                        // broadcast tlbie
        !            73:        unsigned        :BITS_WIDTH(13,0);
        !            74: } m98601_data_bp_mode_t;
        !            75: 
        !            76: /*
        !            77:  * M98601-specific:
        !            78:  * Run Mode Interrupt Status Register (really SRR1)
        !            79:  */
        !            80: typedef struct {
        !            81:        unsigned        :BITS_WIDTH(31,18);
        !            82:        unsigned        trace:BIT_WIDTH(17);    // 1 => interrupt caused by
        !            83:                                                // MSR(SE) trace mode
        !            84:        unsigned        :BIT_WIDTH(16);
        !            85:        MSR_BITS;
        !            86: } rmisr_t;
        !            87: 
        !            88: /*
        !            89:  * M98601-specific:
        !            90:  * Machine Check Interrupt Status Register (HID0)
        !            91:  */
        !            92: typedef struct {
        !            93:        unsigned        e:BIT_WIDTH(31);        // master checkstop enable
        !            94:        unsigned        s:BIT_WIDTH(30);        // micro-code self-test latch
        !            95:        unsigned        m:BIT_WIDTH(29);        // checkstop with MSR(me)=0
        !            96:        unsigned        td:BIT_WIDTH(28);       // multi-side hit in tlb
        !            97:        unsigned        cd:BIT_WIDTH(27);       // multi-side hit in cache dir
        !            98:        unsigned        sh:BIT_WIDTH(26);       // sequencer hang
        !            99:        unsigned        dt:BIT_WIDTH(25);       // dispatch timeout
        !           100:        unsigned        ba:BIT_WIDTH(24);       // bus address parity error
        !           101:        unsigned        bd:BIT_WIDTH(23);       // bus data parity error
        !           102:        unsigned        cp:BIT_WIDTH(22);       // cache parity error
        !           103:        unsigned        iu:BIT_WIDTH(21);       // invalid micro-code instr
        !           104:        unsigned        pp:BIT_WIDTH(20);       // pio bus protocol error
        !           105:        unsigned        :BITS_WIDTH(19,17);     // reserved
        !           106:        unsigned        es:BIT_WIDTH(16);       // enable ucode selftest ckstop
        !           107:        unsigned        em:BIT_WIDTH(15);       // enable machine check ckstop
        !           108:        unsigned        etd:BIT_WIDTH(14);      // enable tlb ckstop
        !           109:        unsigned        ecd:BIT_WIDTH(13);      // enable cache dir ckstop
        !           110:        unsigned        esh:BIT_WIDTH(12);      // enable sequencer hang ckstop
        !           111:        unsigned        edt:BIT_WIDTH(11);      // enable disp timeout ckstop
        !           112:        unsigned        eba:BIT_WIDTH(10);      // enable bus addr parity ckstop
        !           113:        unsigned        ebd:BIT_WIDTH(9);       // enable bus data parity ckstop
        !           114:        unsigned        ecp:BIT_WIDTH(8);       // enable cache parity ckstop
        !           115:        unsigned        eiu:BIT_WIDTH(7);       // enable inval ucode ins ckstop
        !           116:        unsigned        epp:BIT_WIDTH(6);       // enable pio bus prot ckstop
        !           117:        unsigned        ddrip:BIT_WIDTH(5);     // disable dynamic reload of
        !           118:                                                // alternate sector for instr
        !           119:                                                // prefecth (>= DD2.0)
        !           120:        unsigned        ddrls:BIT_WIDTH(4);     // disable dynamic reload of
        !           121:                                                // alternate sector for
        !           122:                                                // load/store ops (>= DD2.0)
        !           123:        unsigned        :BIT_WIDTH(3);          // reserved
        !           124:        unsigned        dpc:BIT_WIDTH(2);       // disable precharge for ARTRY
        !           125:                                                // and SHARED signals (>= DD2.0)
        !           126:        unsigned        emc:BIT_WIDTH(1);       // error in main cache
        !           127:        unsigned        ehp:BIT_WIDTH(0);       // enable high pri write queue
        !           128:                                                // for push data (>= DD2.0)
        !           129: } mcisr_t;
        !           130: 
        !           131: #endif _ARCH_M98K_M98601_REGS_H_

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