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1.1 root 1: /* @(#)reg.h 1.16 92/04/28 SMI */
2:
3: /*
4: * Copyright (c) 1985 by Sun Microsystems, Inc.
5: */
6:
7: #ifndef _sparc_reg_h
8: #define _sparc_reg_h
9:
10: /*
11: * Location of the users' stored
12: * registers relative to R0.
13: * Usage is u.u_ar0[XX].
14: */
15: #define PSR (0)
16: #define PC (1)
17: #define nPC (2)
18: #define SPARC_Y (3)
19: #define G1 (4)
20: #define G2 (5)
21: #define G3 (6)
22: #define G4 (7)
23: #define G5 (8)
24: #define G6 (9)
25: #define G7 (10)
26: #define O0 (11)
27: #define O1 (12)
28: #define O2 (13)
29: #define O3 (14)
30: #define O4 (15)
31: #define O5 (16)
32: #define O6 (17)
33: #define O7 (18)
34:
35: /* the following defines are for portability */
36: #define PS PSR
37: #define SP O6
38: #define R0 O0
39: #define R1 O1
40:
41: /*
42: * And now for something completely the same...
43: */
44: #ifndef __ASSEMBLER__
45: struct regs {
46: int r_psr; /* processor status register */
47: int r_pc; /* program counter */
48: int r_npc; /* next program counter */
49: int r_y; /* the y register */
50: int r_g1; /* user global regs */
51: int r_g2;
52: int r_g3;
53: int r_g4;
54: int r_g5;
55: int r_g6;
56: int r_g7;
57: int r_o0;
58: int r_o1;
59: int r_o2;
60: int r_o3;
61: int r_o4;
62: int r_o5;
63: int r_o6;
64: int r_o7;
65: };
66:
67: #define r_ps r_psr /* for portablility */
68: #define r_r0 r_o0
69: #define r_sp r_o6
70:
71: #endif !__ASSEMBLER__
72:
73: /*
74: * Floating point definitions.
75: */
76:
77: #define FPU /* we have an external float unit */
78:
79: #ifndef __ASSEMBLER__
80:
81: #define FQ_DEPTH 16 /* maximum instuctions in FQ */
82:
83: /*
84: * struct fpu_status is the floating point processor state
85: * struct fpu is the sum total of all possible floating point state
86: * which includes the state of external floating point hardware,
87: * fpa registers, etc..., if it exists.
88: */
89: struct fpq {
90: unsigned long *addr; /* address */
91: unsigned long instr; /* instruction */
92: };
93: struct fq {
94: union { /* FPU inst/addr queue */
95: double whole;
96: struct fpq fpq;
97: } FQu;
98: };
99:
100:
101: #define FPU_REGS_TYPE unsigned
102: #define FPU_FSR_TYPE unsigned
103:
104: struct fpu {
105: union { /* FPU floating point regs */
106: FPU_REGS_TYPE Fpu_regs[32]; /* 32 singles */
107: double Fpu_dregs[16]; /* 16 doubles */
108: } fpu_fr;
109: FPU_FSR_TYPE Fpu_fsr; /* FPU status register */
110: unsigned Fpu_flags; /* control flags */
111: unsigned Fpu_extra; /* extra word */
112: unsigned Fpu_qcnt; /* count of valid entries in fps_q */
113: struct fq Fpu_q[FQ_DEPTH]; /* FPU instruction address queue */
114: };
115:
116: #define fpu_regs fpu_fr.Fpu_regs
117: #define fpu_dregs fpu_fr.Fpu_dregs
118: #define fpu_fsr Fpu_fsr
119: #define fpu_flags Fpu_flags
120: #define fpu_extra Fpu_extra
121: #define fpu_q Fpu_q
122: #define fpu_qcnt Fpu_qcnt
123:
124: #endif !__ASSEMBLER__
125:
126:
127: /*
128: * Definition of bits in the Sun-4 FSR (Floating-point Status Register)
129: * ________________________________________________________________________
130: * | RD | RP | TEM | NS | res | vers | FTT | QNE | PR | FCC | AEXC | CEXC |
131: * |-----|---- |-----|----|-----|------|-----|-----|----|-----|------|------|
132: * 31 30 29 28 27 23 22 21 20 19 17 16 14 13 12 11 10 9 5 4 0
133: */
134: #define FSR_CEXC 0x0000001f /* Current Exception */
135: #define FSR_AEXC 0x000003e0 /* ieee accrued exceptions */
136: #define FSR_FCC 0x00000c00 /* Floating-point Condition Codes */
137: #define FSR_PR 0x00001000 /* Partial Remainder */
138: #define FSR_QNE 0x00002000 /* Queue not empty */
139: #define FSR_FTT 0x0001c000 /* Floating-point Trap Type */
140: #define FSR_VERS 0x000e0000 /* version field */
141: #define FSR_RESV 0x00300000 /* reserved */
142: #define FSR_NS 0x00400000 /* non-standard fp */
143: #define FSR_TEM 0x0f800000 /* ieee Trap Enable Mask */
144: #define FSR_RP 0x30000000 /* Rounding Precision */
145: #define FSR_RD 0xc0000000 /* Rounding Direction */
146:
147: #define FSR_VERS_SHIFT (17) /* amount to shift version field */
148:
149: /*
150: * Definition of CEXC (Current EXCeption) bit field of fsr
151: */
152: #define FSR_CEXC_NX 0x00000001 /* inexact */
153: #define FSR_CEXC_DZ 0x00000002 /* divide-by-zero */
154: #define FSR_CEXC_UF 0x00000004 /* underflow */.
155: #define FSR_CEXC_OF 0x00000008 /* overflow */
156: #define FSR_CEXC_NV 0x00000010 /* invalid */
157:
158: /*
159: * Definition of AEXC (Accrued EXCeption) bit field of fsr
160: */
161: #define FSR_AEXC_NX (0x1 << 5) /* inexact */
162: #define FSR_AEXC_DZ (0x2 << 5) /* divide-by-zero */
163: #define FSR_AEXC_UF (0x4 << 5) /* underflow */.
164: #define FSR_AEXC_OF (0x8 << 5) /* overflow */
165: #define FSR_AEXC_NV (0x10 << 5) /* invalid */
166:
167: /*
168: * Defintion of FTT (Floating-point Trap Type) field within the FSR
169: */
170: #define FTT_NONE 0 /* no excepitons */
171: #define FTT_IEEE 1 /* IEEE exception */
172: #define FTT_UNFIN 2 /* unfinished fpop */
173: #define FTT_UNIMP 3 /* unimplemented fpop */
174: #define FTT_SEQ 4 /* sequence error */
175: #define FTT_ALIGN 5 /* alignment, by software convention */
176: #define FTT_DFAULT 6 /* data fault, by software convention */
177: #define FSR_FTT_SHIFT 14 /* shift needed to justfy ftt field */
178: #define FSR_FTT_IEEE (FTT_IEEE << FSR_FTT_SHIFT)
179: #define FSR_FTT_UNFIN (FTT_UNFIN << FSR_FTT_SHIFT)
180: #define FSR_FTT_UNIMP (FTT_UNIMP << FSR_FTT_SHIFT)
181: #define FSR_FTT_SEQ (FTT_SEQ << FSR_FTT_SHIFT)
182: #define FSR_FTT_ALIGN (FTT_ALIGN << FSR_FTT_SHIFT)
183: #define FSR_FTT_DFAULT (FTT_DFAULT << FSR_FTT_SHIFT)
184:
185: /*
186: * Values of VERS (version) field within the FSR
187: * NOTE: these values are overloaded; the cpu type must be used to
188: * further discriminate amongst these. For that reason, no #defines are
189: * provided.
190: *
191: * Version cpu = 21-22, 51-54 cpu = 23-24, 55-57
192: * 0 Weitek 1164/5 (FAB 1-4) TI 8847
193: * 1 Weitek 1164/5 (FAB 5-6) LSI L64814
194: * 2 TI 8847 TI TMS390C602A
195: * 3 Weitek 3170 Weitek 3171
196: * 4 Meiko ?
197: * 5 ? ?
198: * 6 ? ?
199: * 7 No FP Hardware No FP Hardware
200: */
201:
202:
203: /*
204: * Definition of TEM (Trap Enable Mask) bit field of fsr
205: */
206: #define FSR_TEM_NX (0x1 << 23) /* inexact */
207: #define FSR_TEM_DZ (0x2 << 23) /* divide-by-zero */
208: #define FSR_TEM_UF (0x4 << 23) /* underflow */.
209: #define FSR_TEM_OF (0x8 << 23) /* overflow */
210: #define FSR_TEM_NV (0x10 << 23) /* invalid */
211:
212: /*
213: * Definition of RP (Rounding Precision) field of fsr
214: */
215: #define RP_DBLEXT 0 /* double-extended */
216: #define RP_SINGLE 1 /* single */
217: #define RP_DOUBLE 2 /* double */
218: #define RP_RESERVED 3 /* unused and reserved */
219:
220: /*
221: * Defintion of RD (Rounding Direction) field of fsr
222: */
223: #define RD_NEAR 0 /* nearest or even if tie */
224: #define RD_ZER0 1 /* to zero */
225: #define RD_POSINF 2 /* positive infinity */
226: #define RD_NEGINF 3 /* negative infinity */
227:
228: /*
229: * Definition of the FP enable flags of the pcb struct
230: * Normal operation, all flags are zero
231: */
232: #define FP_UNINITIALIZED 1
233: #define FP_STARTSIG 2
234: #define FP_DISABLE 4
235: #define FP_ENABLE 8
236:
237: #ifndef __ASSEMBLER__
238: /*
239: * How a register window looks on the stack.
240: */
241: struct rwindow {
242: int rw_local[8]; /* locals */
243: int rw_in[8]; /* ins */
244: };
245:
246: #define rw_fp rw_in[6] /* frame pointer */
247: #define rw_rtn rw_in[7] /* return address */
248:
249: #endif !__ASSEMBLER__
250:
251:
252: /*
253: * Definition of bits in the Sun-4 PSR (Processor Status Register)
254: * ____________________________________________________________________
255: * | IMPL | VER | ICC | res | EC | EF | PIL | S | PS | ET | CWP |
256: * |-----------|-----|------|-----|----|----|-------|---|----|----|-----|
257: * 31 28 27 24 23 20 19 14 13 12 11 8 7 6 5 4 0
258: */
259:
260:
261: struct p_status {
262: union {
263: unsigned int psr;
264: struct {
265: unsigned int
266: impl:4,
267: ver:4,
268: icc:4,
269: reserved:6,
270: ec:1,
271: ef:1,
272: pil:4,
273: s:1,
274: ps:1,
275: et:1,
276: cwp:5;
277: } psr_bits;
278: } PSRREG;
279: };
280:
281: struct f_status {
282: union {
283: FPU_FSR_TYPE Fpu_fsr; /* FPU status register */
284: struct {
285: unsigned int
286: rd:2,
287: rp:2,
288: tem:5,
289: res:6,
290: ftt:3,
291: qne:1,
292: pr:1,
293: fcc:2,
294: aexc:5,
295: cexc:5;
296: } Fpu_fsr_bits;
297: } FPUREG;
298: };
299:
300: #endif /*!_sparc_reg_h*/
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