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1.1 root 1: /* i386-opcode.h -- Intel 80386 opcode table
2: Copyright 1989, 1991, 1992 Free Software Foundation.
3:
4: This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
5:
6: This program is free software; you can redistribute it and/or modify
7: it under the terms of the GNU General Public License as published by
8: the Free Software Foundation; either version 2 of the License, or
9: (at your option) any later version.
10:
11: This program is distributed in the hope that it will be useful,
12: but WITHOUT ANY WARRANTY; without even the implied warranty of
13: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14: GNU General Public License for more details.
15:
16: You should have received a copy of the GNU General Public License
17: along with this program; if not, write to the Free Software
18: Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
19:
20: static const template i386_optab[] = {
21:
22: #define _ None
23: /* move instructions */
24: { "mov", 2, 0xa0, _, DW|NoModrm, { Disp32, Acc, 0 } },
25: { "mov", 2, 0x88, _, DW|Modrm, { Reg, Reg|Mem, 0 } },
26: { "mov", 2, 0xb0, _, ShortFormW, { Imm, Reg, 0 } },
27: { "mov", 2, 0xc6, _, W|Modrm, { Imm, Reg|Mem, 0 } },
28: { "mov", 2, 0x8c, _, D|Modrm, { SReg3|SReg2, Reg16|Mem, 0 } },
29: /* move to/from control debug registers */
30: { "mov", 2, 0x0f20, _, D|Modrm, { Control, Reg32, 0} },
31: { "mov", 2, 0x0f21, _, D|Modrm, { Debug, Reg32, 0} },
32: { "mov", 2, 0x0f24, _, D|Modrm, { Test, Reg32, 0} },
33:
34: /* move with sign extend */
35: /* "movsbl" & "movsbw" must not be unified into "movsb" to avoid
36: conflict with the "movs" string move instruction. Thus,
37: {"movsb", 2, 0x0fbe, _, ReverseRegRegmem|Modrm, { Reg8|Mem, Reg16|Reg32, 0} },
38: is not kosher; we must seperate the two instructions. */
39: {"movsbl", 2, 0x0fbe, _, ReverseRegRegmem|Modrm, { Reg8|Mem, Reg32, 0} },
40: {"movsbw", 2, 0x660fbe, _, ReverseRegRegmem|Modrm, { Reg8|Mem, Reg16, 0} },
41: {"movswl", 2, 0x0fbf, _, ReverseRegRegmem|Modrm, { Reg16|Mem, Reg32, 0} },
42:
43: /* move with zero extend */
44: {"movzb", 2, 0x0fb6, _, ReverseRegRegmem|Modrm, { Reg8|Mem, Reg16|Reg32, 0} },
45: {"movzwl", 2, 0x0fb7, _, ReverseRegRegmem|Modrm, { Reg16|Mem, Reg32, 0} },
46:
47: /* push instructions */
48: {"push", 1, 0x50, _, ShortForm, { WordReg,0,0 } },
49: {"push", 1, 0xff, 0x6, Modrm, { WordReg|WordMem, 0, 0 } },
50: {"push", 1, 0x6a, _, NoModrm, { Imm8S, 0, 0} },
51: {"push", 1, 0x68, _, NoModrm, { Imm32, 0, 0} },
52: {"push", 1, 0x06, _, Seg2ShortForm, { SReg2,0,0 } },
53: {"push", 1, 0x0fa0, _, Seg3ShortForm, { SReg3,0,0 } },
54: /* push all */
55: {"pusha", 0, 0x60, _, NoModrm, { 0, 0, 0 } },
56:
57: /* pop instructions */
58: {"pop", 1, 0x58, _, ShortForm, { WordReg,0,0 } },
59: {"pop", 1, 0x8f, 0x0, Modrm, { WordReg|WordMem, 0, 0 } },
60: #define POP_SEG_SHORT 0x7
61: {"pop", 1, 0x07, _, Seg2ShortForm, { SReg2,0,0 } },
62: {"pop", 1, 0x0fa1, _, Seg3ShortForm, { SReg3,0,0 } },
63: /* pop all */
64: {"popa", 0, 0x61, _, NoModrm, { 0, 0, 0 } },
65:
66: /* xchg exchange instructions
67: xchg commutes: we allow both operand orders */
68: {"xchg", 2, 0x90, _, ShortForm, { WordReg, Acc, 0 } },
69: {"xchg", 2, 0x90, _, ShortForm, { Acc, WordReg, 0 } },
70: {"xchg", 2, 0x86, _, W|Modrm, { Reg, Reg|Mem, 0 } },
71: {"xchg", 2, 0x86, _, W|Modrm, { Reg|Mem, Reg, 0 } },
72:
73: /* in/out from ports */
74: {"in", 2, 0xe4, _, W|NoModrm, { Imm8, Acc, 0 } },
75: {"in", 2, 0xec, _, W|NoModrm, { InOutPortReg, Acc, 0 } },
76: {"in", 1, 0xe4, _, W|NoModrm, { Imm8, 0, 0 } },
77: {"in", 1, 0xec, _, W|NoModrm, { InOutPortReg, 0, 0 } },
78: {"out", 2, 0xe6, _, W|NoModrm, { Acc, Imm8, 0 } },
79: {"out", 2, 0xee, _, W|NoModrm, { Acc, InOutPortReg, 0 } },
80: {"out", 1, 0xe6, _, W|NoModrm, { Imm8, 0, 0 } },
81: {"out", 1, 0xee, _, W|NoModrm, { InOutPortReg, 0, 0 } },
82:
83: /* load effective address */
84: {"lea", 2, 0x8d, _, Modrm, { WordMem, WordReg, 0 } },
85:
86: /* load segment registers from memory */
87: {"lds", 2, 0xc5, _, Modrm, { Mem, Reg32, 0} },
88: {"les", 2, 0xc4, _, Modrm, { Mem, Reg32, 0} },
89: {"lfs", 2, 0x0fb4, _, Modrm, { Mem, Reg32, 0} },
90: {"lgs", 2, 0x0fb5, _, Modrm, { Mem, Reg32, 0} },
91: {"lss", 2, 0x0fb2, _, Modrm, { Mem, Reg32, 0} },
92:
93: /* flags register instructions */
94: {"clc", 0, 0xf8, _, NoModrm, { 0, 0, 0} },
95: {"cld", 0, 0xfc, _, NoModrm, { 0, 0, 0} },
96: {"cli", 0, 0xfa, _, NoModrm, { 0, 0, 0} },
97: {"clts", 0, 0x0f06, _, NoModrm, { 0, 0, 0} },
98: {"cmc", 0, 0xf5, _, NoModrm, { 0, 0, 0} },
99: {"lahf", 0, 0x9f, _, NoModrm, { 0, 0, 0} },
100: {"sahf", 0, 0x9e, _, NoModrm, { 0, 0, 0} },
101: {"pushf", 0, 0x9c, _, NoModrm, { 0, 0, 0} },
102: {"popf", 0, 0x9d, _, NoModrm, { 0, 0, 0} },
103: {"stc", 0, 0xf9, _, NoModrm, { 0, 0, 0} },
104: {"std", 0, 0xfd, _, NoModrm, { 0, 0, 0} },
105: {"sti", 0, 0xfb, _, NoModrm, { 0, 0, 0} },
106:
107: {"add", 2, 0x0, _, DW|Modrm, { Reg, Reg|Mem, 0} },
108: {"add", 2, 0x83, 0, Modrm, { Imm8S, WordReg|WordMem, 0} },
109: {"add", 2, 0x4, _, W|NoModrm, { Imm, Acc, 0} },
110: {"add", 2, 0x80, 0, W|Modrm, { Imm, Reg|Mem, 0} },
111:
112: {"inc", 1, 0x40, _, ShortForm, { WordReg, 0, 0} },
113: {"inc", 1, 0xfe, 0, W|Modrm, { Reg|Mem, 0, 0} },
114:
115: {"sub", 2, 0x28, _, DW|Modrm, { Reg, Reg|Mem, 0} },
116: {"sub", 2, 0x83, 5, Modrm, { Imm8S, WordReg|WordMem, 0} },
117: {"sub", 2, 0x2c, _, W|NoModrm, { Imm, Acc, 0} },
118: {"sub", 2, 0x80, 5, W|Modrm, { Imm, Reg|Mem, 0} },
119:
120: {"dec", 1, 0x48, _, ShortForm, { WordReg, 0, 0} },
121: {"dec", 1, 0xfe, 1, W|Modrm, { Reg|Mem, 0, 0} },
122:
123: {"sbb", 2, 0x18, _, DW|Modrm, { Reg, Reg|Mem, 0} },
124: {"sbb", 2, 0x83, 3, Modrm, { Imm8S, WordReg|WordMem, 0} },
125: {"sbb", 2, 0x1c, _, W|NoModrm, { Imm, Acc, 0} },
126: {"sbb", 2, 0x80, 3, W|Modrm, { Imm, Reg|Mem, 0} },
127:
128: {"cmp", 2, 0x38, _, DW|Modrm, { Reg, Reg|Mem, 0} },
129: {"cmp", 2, 0x83, 7, Modrm, { Imm8S, WordReg|WordMem, 0} },
130: {"cmp", 2, 0x3c, _, W|NoModrm, { Imm, Acc, 0} },
131: {"cmp", 2, 0x80, 7, W|Modrm, { Imm, Reg|Mem, 0} },
132:
133: {"test", 2, 0x84, _, W|Modrm, { Reg|Mem, Reg, 0} },
134: {"test", 2, 0x84, _, W|Modrm, { Reg, Reg|Mem, 0} },
135: {"test", 2, 0xa8, _, W|NoModrm, { Imm, Acc, 0} },
136: {"test", 2, 0xf6, 0, W|Modrm, { Imm, Reg|Mem, 0} },
137:
138: {"and", 2, 0x20, _, DW|Modrm, { Reg, Reg|Mem, 0} },
139: {"and", 2, 0x83, 4, Modrm, { Imm8S, WordReg|WordMem, 0} },
140: {"and", 2, 0x24, _, W|NoModrm, { Imm, Acc, 0} },
141: {"and", 2, 0x80, 4, W|Modrm, { Imm, Reg|Mem, 0} },
142:
143: {"or", 2, 0x08, _, DW|Modrm, { Reg, Reg|Mem, 0} },
144: {"or", 2, 0x83, 1, Modrm, { Imm8S, WordReg|WordMem, 0} },
145: {"or", 2, 0x0c, _, W|NoModrm, { Imm, Acc, 0} },
146: {"or", 2, 0x80, 1, W|Modrm, { Imm, Reg|Mem, 0} },
147:
148: {"xor", 2, 0x30, _, DW|Modrm, { Reg, Reg|Mem, 0} },
149: {"xor", 2, 0x83, 6, Modrm, { Imm8S, WordReg|WordMem, 0} },
150: {"xor", 2, 0x34, _, W|NoModrm, { Imm, Acc, 0} },
151: {"xor", 2, 0x80, 6, W|Modrm, { Imm, Reg|Mem, 0} },
152:
153: {"adc", 2, 0x10, _, DW|Modrm, { Reg, Reg|Mem, 0} },
154: {"adc", 2, 0x83, 2, Modrm, { Imm8S, WordReg|WordMem, 0} },
155: {"adc", 2, 0x14, _, W|NoModrm, { Imm, Acc, 0} },
156: {"adc", 2, 0x80, 2, W|Modrm, { Imm, Reg|Mem, 0} },
157:
158: {"neg", 1, 0xf6, 3, W|Modrm, { Reg|Mem, 0, 0} },
159: {"not", 1, 0xf6, 2, W|Modrm, { Reg|Mem, 0, 0} },
160:
161: {"aaa", 0, 0x37, _, NoModrm, { 0, 0, 0} },
162: {"aas", 0, 0x3f, _, NoModrm, { 0, 0, 0} },
163: {"daa", 0, 0x27, _, NoModrm, { 0, 0, 0} },
164: {"das", 0, 0x2f, _, NoModrm, { 0, 0, 0} },
165: {"aad", 0, 0xd50a, _, NoModrm, { 0, 0, 0} },
166: {"aam", 0, 0xd40a, _, NoModrm, { 0, 0, 0} },
167:
168: /* conversion insns */
169: /* conversion: intel naming */
170: {"cbw", 0, 0x6698, _, NoModrm, { 0, 0, 0} },
171: {"cwd", 0, 0x6699, _, NoModrm, { 0, 0, 0} },
172: {"cwde", 0, 0x98, _, NoModrm, { 0, 0, 0} },
173: {"cdq", 0, 0x99, _, NoModrm, { 0, 0, 0} },
174: /* att naming */
175: {"cbtw", 0, 0x6698, _, NoModrm, { 0, 0, 0} },
176: {"cwtl", 0, 0x98, _, NoModrm, { 0, 0, 0} },
177: {"cwtd", 0, 0x6699, _, NoModrm, { 0, 0, 0} },
178: {"cltd", 0, 0x99, _, NoModrm, { 0, 0, 0} },
179:
180: /* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are
181: expanding 64-bit multiplies, and *cannot* be selected to accomplish
182: 'imul %ebx, %eax' (opcode 0x0faf must be used in this case)
183: These multiplies can only be selected with single opearnd forms. */
184: {"mul", 1, 0xf6, 4, W|Modrm, { Reg|Mem, 0, 0} },
185: {"imul", 1, 0xf6, 5, W|Modrm, { Reg|Mem, 0, 0} },
186:
187:
188:
189:
190: /* imulKludge here is needed to reverse the i.rm.reg & i.rm.regmem fields.
191: These instructions are exceptions: 'imul $2, %eax, %ecx' would put
192: '%eax' in the reg field and '%ecx' in the regmem field if we did not
193: switch them. */
194: {"imul", 2, 0x0faf, _, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} },
195: {"imul", 3, 0x6b, _, Modrm|ReverseRegRegmem, { Imm8S, WordReg|Mem, WordReg} },
196: {"imul", 3, 0x69, _, Modrm|ReverseRegRegmem, { Imm16|Imm32, WordReg|Mem, WordReg} },
197: /*
198: imul with 2 operands mimicks imul with 3 by puting register both
199: in i.rm.reg & i.rm.regmem fields
200: */
201: {"imul", 2, 0x6b, _, Modrm|imulKludge, { Imm8S, WordReg, 0} },
202: {"imul", 2, 0x69, _, Modrm|imulKludge, { Imm16|Imm32, WordReg, 0} },
203: {"div", 1, 0xf6, 6, W|Modrm, { Reg|Mem, 0, 0} },
204: {"div", 2, 0xf6, 6, W|Modrm, { Reg|Mem, Acc, 0} },
205: {"idiv", 1, 0xf6, 7, W|Modrm, { Reg|Mem, 0, 0} },
206: {"idiv", 2, 0xf6, 7, W|Modrm, { Reg|Mem, Acc, 0} },
207:
208: {"rol", 2, 0xd0, 0, W|Modrm, { Imm1, Reg|Mem, 0} },
209: {"rol", 2, 0xc0, 0, W|Modrm, { Imm8, Reg|Mem, 0} },
210: {"rol", 2, 0xd2, 0, W|Modrm, { ShiftCount, Reg|Mem, 0} },
211: {"rol", 1, 0xd0, 0, W|Modrm, { Reg|Mem, 0, 0} },
212:
213: {"ror", 2, 0xd0, 1, W|Modrm, { Imm1, Reg|Mem, 0} },
214: {"ror", 2, 0xc0, 1, W|Modrm, { Imm8, Reg|Mem, 0} },
215: {"ror", 2, 0xd2, 1, W|Modrm, { ShiftCount, Reg|Mem, 0} },
216: {"ror", 1, 0xd0, 1, W|Modrm, { Reg|Mem, 0, 0} },
217:
218: {"rcl", 2, 0xd0, 2, W|Modrm, { Imm1, Reg|Mem, 0} },
219: {"rcl", 2, 0xc0, 2, W|Modrm, { Imm8, Reg|Mem, 0} },
220: {"rcl", 2, 0xd2, 2, W|Modrm, { ShiftCount, Reg|Mem, 0} },
221: {"rcl", 1, 0xd0, 2, W|Modrm, { Reg|Mem, 0, 0} },
222:
223: {"rcr", 2, 0xd0, 3, W|Modrm, { Imm1, Reg|Mem, 0} },
224: {"rcr", 2, 0xc0, 3, W|Modrm, { Imm8, Reg|Mem, 0} },
225: {"rcr", 2, 0xd2, 3, W|Modrm, { ShiftCount, Reg|Mem, 0} },
226: {"rcr", 1, 0xd0, 3, W|Modrm, { Reg|Mem, 0, 0} },
227:
228: {"sal", 2, 0xd0, 4, W|Modrm, { Imm1, Reg|Mem, 0} },
229: {"sal", 2, 0xc0, 4, W|Modrm, { Imm8, Reg|Mem, 0} },
230: {"sal", 2, 0xd2, 4, W|Modrm, { ShiftCount, Reg|Mem, 0} },
231: {"sal", 1, 0xd0, 4, W|Modrm, { Reg|Mem, 0, 0} },
232: {"shl", 2, 0xd0, 4, W|Modrm, { Imm1, Reg|Mem, 0} },
233: {"shl", 2, 0xc0, 4, W|Modrm, { Imm8, Reg|Mem, 0} },
234: {"shl", 2, 0xd2, 4, W|Modrm, { ShiftCount, Reg|Mem, 0} },
235: {"shl", 1, 0xd0, 4, W|Modrm, { Reg|Mem, 0, 0} },
236:
237: {"shld", 3, 0x0fa4, _, Modrm, { Imm8, WordReg, WordReg|Mem} },
238: {"shld", 3, 0x0fa5, _, Modrm, { ShiftCount, WordReg, WordReg|Mem} },
239: {"shld", 2, 0x0fa5, _, Modrm, { WordReg, WordReg|Mem, 0} },
240:
241: {"shr", 2, 0xd0, 5, W|Modrm, { Imm1, Reg|Mem, 0} },
242: {"shr", 2, 0xc0, 5, W|Modrm, { Imm8, Reg|Mem, 0} },
243: {"shr", 2, 0xd2, 5, W|Modrm, { ShiftCount, Reg|Mem, 0} },
244: {"shr", 1, 0xd0, 5, W|Modrm, { Reg|Mem, 0, 0} },
245:
246: {"shrd", 3, 0x0fac, _, Modrm, { Imm8, WordReg, WordReg|Mem} },
247: {"shrd", 3, 0x0fad, _, Modrm, { ShiftCount, WordReg, WordReg|Mem} },
248: {"shrd", 2, 0x0fad, _, Modrm, { WordReg, WordReg|Mem, 0} },
249:
250: {"sar", 2, 0xd0, 7, W|Modrm, { Imm1, Reg|Mem, 0} },
251: {"sar", 2, 0xc0, 7, W|Modrm, { Imm8, Reg|Mem, 0} },
252: {"sar", 2, 0xd2, 7, W|Modrm, { ShiftCount, Reg|Mem, 0} },
253: {"sar", 1, 0xd0, 7, W|Modrm, { Reg|Mem, 0, 0} },
254:
255: /* control transfer instructions */
256: #define CALL_PC_RELATIVE 0xe8
257: {"call", 1, 0xe8, _, JumpDword, { Disp32, 0, 0} },
258: {"call", 1, 0xff, 2, Modrm, { Reg|Mem|JumpAbsolute, 0, 0} },
259: #define CALL_FAR_IMMEDIATE 0x9a
260: {"lcall", 2, 0x9a, _, JumpInterSegment, { Imm16, Abs32|Imm32, 0} },
261: {"lcall", 1, 0xff, 3, Modrm, { Mem, 0, 0} },
262:
263: #define JUMP_PC_RELATIVE 0xeb
264: {"jmp", 1, 0xeb, _, Jump, { Disp, 0, 0} },
265: {"jmp", 1, 0xff, 4, Modrm, { Reg32|Mem|JumpAbsolute, 0, 0} },
266: #define JUMP_FAR_IMMEDIATE 0xea
267: {"ljmp", 2, 0xea, _, JumpInterSegment, { Imm16, Imm32, 0} },
268: {"ljmp", 1, 0xff, 5, Modrm, { Mem, 0, 0} },
269:
270: {"ret", 0, 0xc3, _, NoModrm, { 0, 0, 0} },
271: {"ret", 1, 0xc2, _, NoModrm, { Imm16, 0, 0} },
272: {"lret", 0, 0xcb, _, NoModrm, { 0, 0, 0} },
273: {"lret", 1, 0xca, _, NoModrm, { Imm16, 0, 0} },
274: {"enter", 2, 0xc8, _, NoModrm, { Imm16, Imm8, 0} },
275: {"leave", 0, 0xc9, _, NoModrm, { 0, 0, 0} },
276:
277: /* conditional jumps */
278: {"jo", 1, 0x70, _, Jump, { Disp, 0, 0} },
279:
280: {"jno", 1, 0x71, _, Jump, { Disp, 0, 0} },
281:
282: {"jb", 1, 0x72, _, Jump, { Disp, 0, 0} },
283: {"jc", 1, 0x72, _, Jump, { Disp, 0, 0} },
284: {"jnae", 1, 0x72, _, Jump, { Disp, 0, 0} },
285:
286: {"jnb", 1, 0x73, _, Jump, { Disp, 0, 0} },
287: {"jnc", 1, 0x73, _, Jump, { Disp, 0, 0} },
288: {"jae", 1, 0x73, _, Jump, { Disp, 0, 0} },
289:
290: {"je", 1, 0x74, _, Jump, { Disp, 0, 0} },
291: {"jz", 1, 0x74, _, Jump, { Disp, 0, 0} },
292:
293: {"jne", 1, 0x75, _, Jump, { Disp, 0, 0} },
294: {"jnz", 1, 0x75, _, Jump, { Disp, 0, 0} },
295:
296: {"jbe", 1, 0x76, _, Jump, { Disp, 0, 0} },
297: {"jna", 1, 0x76, _, Jump, { Disp, 0, 0} },
298:
299: {"jnbe", 1, 0x77, _, Jump, { Disp, 0, 0} },
300: {"ja", 1, 0x77, _, Jump, { Disp, 0, 0} },
301:
302: {"js", 1, 0x78, _, Jump, { Disp, 0, 0} },
303:
304: {"jns", 1, 0x79, _, Jump, { Disp, 0, 0} },
305:
306: {"jp", 1, 0x7a, _, Jump, { Disp, 0, 0} },
307: {"jpe", 1, 0x7a, _, Jump, { Disp, 0, 0} },
308:
309: {"jnp", 1, 0x7b, _, Jump, { Disp, 0, 0} },
310: {"jpo", 1, 0x7b, _, Jump, { Disp, 0, 0} },
311:
312: {"jl", 1, 0x7c, _, Jump, { Disp, 0, 0} },
313: {"jnge", 1, 0x7c, _, Jump, { Disp, 0, 0} },
314:
315: {"jnl", 1, 0x7d, _, Jump, { Disp, 0, 0} },
316: {"jge", 1, 0x7d, _, Jump, { Disp, 0, 0} },
317:
318: {"jle", 1, 0x7e, _, Jump, { Disp, 0, 0} },
319: {"jng", 1, 0x7e, _, Jump, { Disp, 0, 0} },
320:
321: {"jnle", 1, 0x7f, _, Jump, { Disp, 0, 0} },
322: {"jg", 1, 0x7f, _, Jump, { Disp, 0, 0} },
323:
324: /* these turn into pseudo operations when disp is larger than 8 bits */
325: #define IS_JUMP_ON_CX_ZERO(o) \
326: (o == 0x67e3)
327: #define IS_JUMP_ON_ECX_ZERO(o) \
328: (o == 0xe3)
329:
330: {"jcxz", 1, 0x67e3, _, JumpByte, { Disp, 0, 0} },
331: {"jecxz", 1, 0xe3, _, JumpByte, { Disp, 0, 0} },
332:
333: #define IS_LOOP_ECX_TIMES(o) \
334: (o == 0xe2 || o == 0xe1 || o == 0xe0)
335:
336: {"loop", 1, 0xe2, _, JumpByte, { Disp, 0, 0} },
337:
338: {"loopz", 1, 0xe1, _, JumpByte, { Disp, 0, 0} },
339: {"loope", 1, 0xe1, _, JumpByte, { Disp, 0, 0} },
340:
341: {"loopnz", 1, 0xe0, _, JumpByte, { Disp, 0, 0} },
342: {"loopne", 1, 0xe0, _, JumpByte, { Disp, 0, 0} },
343:
344: /* set byte on flag instructions */
345: {"seto", 1, 0x0f90, 0, Modrm, { Reg8|Mem, 0, 0} },
346:
347: {"setno", 1, 0x0f91, 0, Modrm, { Reg8|Mem, 0, 0} },
348:
349: {"setb", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} },
350: {"setc", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} },
351: {"setnae", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} },
352:
353: {"setnb", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} },
354: {"setnc", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} },
355: {"setae", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} },
356:
357: {"sete", 1, 0x0f94, 0, Modrm, { Reg8|Mem, 0, 0} },
358: {"setz", 1, 0x0f94, 0, Modrm, { Reg8|Mem, 0, 0} },
359:
360: {"setne", 1, 0x0f95, 0, Modrm, { Reg8|Mem, 0, 0} },
361: {"setnz", 1, 0x0f95, 0, Modrm, { Reg8|Mem, 0, 0} },
362:
363: {"setbe", 1, 0x0f96, 0, Modrm, { Reg8|Mem, 0, 0} },
364: {"setna", 1, 0x0f96, 0, Modrm, { Reg8|Mem, 0, 0} },
365:
366: {"setnbe", 1, 0x0f97, 0, Modrm, { Reg8|Mem, 0, 0} },
367: {"seta", 1, 0x0f97, 0, Modrm, { Reg8|Mem, 0, 0} },
368:
369: {"sets", 1, 0x0f98, 0, Modrm, { Reg8|Mem, 0, 0} },
370:
371: {"setns", 1, 0x0f99, 0, Modrm, { Reg8|Mem, 0, 0} },
372:
373: {"setp", 1, 0x0f9a, 0, Modrm, { Reg8|Mem, 0, 0} },
374: {"setpe", 1, 0x0f9a, 0, Modrm, { Reg8|Mem, 0, 0} },
375:
376: {"setnp", 1, 0x0f9b, 0, Modrm, { Reg8|Mem, 0, 0} },
377: {"setpo", 1, 0x0f9b, 0, Modrm, { Reg8|Mem, 0, 0} },
378:
379: {"setl", 1, 0x0f9c, 0, Modrm, { Reg8|Mem, 0, 0} },
380: {"setnge", 1, 0x0f9c, 0, Modrm, { Reg8|Mem, 0, 0} },
381:
382: {"setnl", 1, 0x0f9d, 0, Modrm, { Reg8|Mem, 0, 0} },
383: {"setge", 1, 0x0f9d, 0, Modrm, { Reg8|Mem, 0, 0} },
384:
385: {"setle", 1, 0x0f9e, 0, Modrm, { Reg8|Mem, 0, 0} },
386: {"setng", 1, 0x0f9e, 0, Modrm, { Reg8|Mem, 0, 0} },
387:
388: {"setnle", 1, 0x0f9f, 0, Modrm, { Reg8|Mem, 0, 0} },
389: {"setg", 1, 0x0f9f, 0, Modrm, { Reg8|Mem, 0, 0} },
390:
391: #define IS_STRING_INSTRUCTION(o) \
392: ((o) == 0xa6 || (o) == 0x6c || (o) == 0x6e || (o) == 0x6e || \
393: (o) == 0xac || (o) == 0xa4 || (o) == 0xae || (o) == 0xaa || \
394: (o) == 0xd7)
395:
396: /* string manipulation */
397: {"cmps", 0, 0xa6, _, W|NoModrm, { 0, 0, 0} },
398: {"scmp", 0, 0xa6, _, W|NoModrm, { 0, 0, 0} },
399: {"ins", 0, 0x6c, _, W|NoModrm, { 0, 0, 0} },
400: {"outs", 0, 0x6e, _, W|NoModrm, { 0, 0, 0} },
401: {"lods", 0, 0xac, _, W|NoModrm, { 0, 0, 0} },
402: {"slod", 0, 0xac, _, W|NoModrm, { 0, 0, 0} },
403: {"movs", 0, 0xa4, _, W|NoModrm, { 0, 0, 0} },
404: {"smov", 0, 0xa4, _, W|NoModrm, { 0, 0, 0} },
405: {"scas", 0, 0xae, _, W|NoModrm, { 0, 0, 0} },
406: {"ssca", 0, 0xae, _, W|NoModrm, { 0, 0, 0} },
407: {"stos", 0, 0xaa, _, W|NoModrm, { 0, 0, 0} },
408: {"ssto", 0, 0xaa, _, W|NoModrm, { 0, 0, 0} },
409: {"xlat", 0, 0xd7, _, NoModrm, { 0, 0, 0} },
410:
411: /* bit manipulation */
412: {"bsf", 2, 0x0fbc, _, Modrm|ReverseRegRegmem, { Reg|Mem, Reg, 0} },
413: {"bsr", 2, 0x0fbd, _, Modrm|ReverseRegRegmem, { Reg|Mem, Reg, 0} },
414: {"bt", 2, 0x0fa3, _, Modrm, { Reg, Reg|Mem, 0} },
415: {"bt", 2, 0x0fba, 4, Modrm, { Imm8, Reg|Mem, 0} },
416: {"btc", 2, 0x0fbb, _, Modrm, { Reg, Reg|Mem, 0} },
417: {"btc", 2, 0x0fba, 7, Modrm, { Imm8, Reg|Mem, 0} },
418: {"btr", 2, 0x0fb3, _, Modrm, { Reg, Reg|Mem, 0} },
419: {"btr", 2, 0x0fba, 6, Modrm, { Imm8, Reg|Mem, 0} },
420: {"bts", 2, 0x0fab, _, Modrm, { Reg, Reg|Mem, 0} },
421: {"bts", 2, 0x0fba, 5, Modrm, { Imm8, Reg|Mem, 0} },
422:
423: /* interrupts & op. sys insns */
424: /* See gas/config/tc-i386.c for conversion of 'int $3' into the special
425: int 3 insn. */
426: #define INT_OPCODE 0xcd
427: #define INT3_OPCODE 0xcc
428: {"int", 1, 0xcd, _, NoModrm, { Imm8, 0, 0} },
429: {"int3", 0, 0xcc, _, NoModrm, { 0, 0, 0} },
430: {"into", 0, 0xce, _, NoModrm, { 0, 0, 0} },
431: {"iret", 0, 0xcf, _, NoModrm, { 0, 0, 0} },
432: /* i386sl (and i486sl?) only */
433: {"rsm", 0, 0x0faa, _, NoModrm,{ 0, 0, 0} },
434:
435: {"boundl", 2, 0x62, _, Modrm, { Reg32, Mem, 0} },
436: {"boundw", 2, 0x6662, _, Modrm, { Reg16, Mem, 0} },
437:
438: {"hlt", 0, 0xf4, _, NoModrm, { 0, 0, 0} },
439: {"wait", 0, 0x9b, _, NoModrm, { 0, 0, 0} },
440: /* nop is actually 'xchgl %eax, %eax' */
441: {"nop", 0, 0x90, _, NoModrm, { 0, 0, 0} },
442:
443: /* protection control */
444: {"arpl", 2, 0x63, _, Modrm, { Reg16, Reg16|Mem, 0} },
445: {"lar", 2, 0x0f02, _, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} },
446: {"lgdt", 1, 0x0f01, 2, Modrm, { Mem, 0, 0} },
447: {"lidt", 1, 0x0f01, 3, Modrm, { Mem, 0, 0} },
448: {"lldt", 1, 0x0f00, 2, Modrm, { WordReg|Mem, 0, 0} },
449: {"lmsw", 1, 0x0f01, 6, Modrm, { WordReg|Mem, 0, 0} },
450: {"lsl", 2, 0x0f03, _, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} },
451: {"ltr", 1, 0x0f00, 3, Modrm, { WordReg|Mem, 0, 0} },
452:
453: {"sgdt", 1, 0x0f01, 0, Modrm, { Mem, 0, 0} },
454: {"sidt", 1, 0x0f01, 1, Modrm, { Mem, 0, 0} },
455: {"sldt", 1, 0x0f00, 0, Modrm, { WordReg|Mem, 0, 0} },
456: {"smsw", 1, 0x0f01, 4, Modrm, { WordReg|Mem, 0, 0} },
457: {"str", 1, 0x0f00, 1, Modrm, { Reg16|Mem, 0, 0} },
458:
459: {"verr", 1, 0x0f00, 4, Modrm, { WordReg|Mem, 0, 0} },
460: {"verw", 1, 0x0f00, 5, Modrm, { WordReg|Mem, 0, 0} },
461:
462: /* floating point instructions */
463:
464: /* load */
465: {"fld", 1, 0xd9c0, _, ShortForm, { FloatReg, 0, 0} }, /* register */
466: {"flds", 1, 0xd9, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem float */
467: {"fldl", 1, 0xdd, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem double */
468: {"fldl", 1, 0xd9c0, _, ShortForm, { FloatReg, 0, 0} }, /* register */
469: {"fild", 1, 0xdf, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem word (16) */
470: {"fildl", 1, 0xdb, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem dword (32) */
471: {"fildq",1, 0xdf, 5, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem qword (64) */
472: {"fildll",1, 0xdf, 5, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem qword (64) */
473: {"fldt", 1, 0xdb, 5, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem efloat */
474: {"fbld", 1, 0xdf, 4, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem bcd */
475:
476: /* store (no pop) */
477: {"fst", 1, 0xddd0, _, ShortForm, { FloatReg, 0, 0} }, /* register */
478: {"fsts", 1, 0xd9, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem float */
479: {"fstl", 1, 0xdd, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem double */
480: {"fstl", 1, 0xddd0, _, ShortForm, { FloatReg, 0, 0} }, /* register */
481: {"fist", 1, 0xdf, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem word (16) */
482: {"fistl", 1, 0xdb, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem dword (32) */
483:
484: /* store (with pop) */
485: {"fstp", 1, 0xddd8, _, ShortForm, { FloatReg, 0, 0} }, /* register */
486: {"fstps", 1, 0xd9, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem float */
487: {"fstpl", 1, 0xdd, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem double */
488: {"fstpl", 1, 0xddd8, _, ShortForm, { FloatReg, 0, 0} }, /* register */
489: {"fistp", 1, 0xdf, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem word (16) */
490: {"fistpl",1, 0xdb, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem dword (32) */
491: {"fistpq",1, 0xdf, 7, Modrm, { Mem, 0, 0} }, /* %st0 --> mem qword (64) */
492: {"fistpll",1,0xdf, 7, Modrm, { Mem, 0, 0} }, /* %st0 --> mem qword (64) */
493: {"fstpt", 1, 0xdb, 7, Modrm, { Mem, 0, 0} }, /* %st0 --> mem efloat */
494: {"fbstp", 1, 0xdf, 6, Modrm, { Mem, 0, 0} }, /* %st0 --> mem bcd */
495:
496: /* exchange %st<n> with %st0 */
497: {"fxch", 1, 0xd9c8, _, ShortForm, { FloatReg, 0, 0} },
498:
499: /* comparison (without pop) */
500: {"fcom", 1, 0xd8d0, _, ShortForm, { FloatReg, 0, 0} },
501: {"fcoms", 1, 0xd8, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem float */
502: {"ficoml", 1, 0xda, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem word */
503: {"fcoml", 1, 0xdc, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem double */
504: {"fcoml", 1, 0xd8d0, _, ShortForm, { FloatReg, 0, 0} },
505: {"ficoms", 1, 0xde, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem dword */
506:
507: /* comparison (with pop) */
508: {"fcomp", 1, 0xd8d8, _, ShortForm, { FloatReg, 0, 0} },
509: {"fcomps", 1, 0xd8, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem float */
510: {"ficompl", 1, 0xda, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem word */
511: {"fcompl", 1, 0xdc, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem double */
512: {"fcompl", 1, 0xd8d8, _, ShortForm, { FloatReg, 0, 0} },
513: {"ficomps", 1, 0xde, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem dword */
514: {"fcompp", 0, 0xded9, _, NoModrm, { 0, 0, 0} }, /* compare %st0, %st1 & pop 2 */
515:
516: /* unordered comparison (with pop) */
517: {"fucom", 1, 0xdde0, _, ShortForm, { FloatReg, 0, 0} },
518: {"fucomp", 1, 0xdde8, _, ShortForm, { FloatReg, 0, 0} },
519: {"fucompp", 0, 0xdae9, _, NoModrm, { 0, 0, 0} }, /* ucompare %st0, %st1 & pop twice */
520:
521: {"ftst", 0, 0xd9e4, _, NoModrm, { 0, 0, 0} }, /* test %st0 */
522: {"fxam", 0, 0xd9e5, _, NoModrm, { 0, 0, 0} }, /* examine %st0 */
523:
524: /* load constants into %st0 */
525: {"fld1", 0, 0xd9e8, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- 1.0 */
526: {"fldl2t", 0, 0xd9e9, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- log2(10) */
527: {"fldl2e", 0, 0xd9ea, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- log2(e) */
528: {"fldpi", 0, 0xd9eb, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- pi */
529: {"fldlg2", 0, 0xd9ec, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- log10(2) */
530: {"fldln2", 0, 0xd9ed, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- ln(2) */
531: {"fldz", 0, 0xd9ee, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- 0.0 */
532:
533: /* arithmetic */
534:
535: /* add */
536: {"fadd", 1, 0xd8c0, _, ShortForm, { FloatReg, 0, 0} },
537: {"fadd", 2, 0xd8c0, _, ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
538: {"fadd", 0, 0xdcc1, _, NoModrm, { 0, 0, 0} }, /* alias for fadd %st, %st(1) */
539: {"faddp", 1, 0xdac0, _, ShortForm, { FloatReg, 0, 0} },
540: {"faddp", 2, 0xdac0, _, ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
541: {"faddp", 0, 0xdec1, _, NoModrm, { 0, 0, 0} }, /* alias for faddp %st, %st(1) */
542: {"fadds", 1, 0xd8, 0, Modrm, { Mem, 0, 0} },
543: {"fiaddl", 1, 0xda, 0, Modrm, { Mem, 0, 0} },
544: {"faddl", 1, 0xdc, 0, Modrm, { Mem, 0, 0} },
545: {"fiadds", 1, 0xde, 0, Modrm, { Mem, 0, 0} },
546:
547: /* sub */
548: /* Note: intel has decided that certain of these operations are reversed
549: in assembler syntax. */
550: {"fsub", 1, 0xd8e0, _, ShortForm, { FloatReg, 0, 0} },
551: {"fsub", 2, 0xd8e0, _, ShortForm, { FloatReg, FloatAcc, 0} },
552: #ifdef NON_BROKEN_OPCODES
553: {"fsub", 2, 0xdce8, _, ShortForm, { FloatAcc, FloatReg, 0} },
554: #else
555: {"fsub", 2, 0xdce0, _, ShortForm, { FloatAcc, FloatReg, 0} },
556: #endif
557: {"fsub", 0, 0xdce1, _, NoModrm, { 0, 0, 0} },
558: {"fsubp", 1, 0xdae0, _, ShortForm, { FloatReg, 0, 0} },
559: {"fsubp", 2, 0xdae0, _, ShortForm, { FloatReg, FloatAcc, 0} },
560: #ifdef NON_BROKEN_OPCODES
561: {"fsubp", 2, 0xdee8, _, ShortForm, { FloatAcc, FloatReg, 0} },
562: #else
563: {"fsubp", 2, 0xdee0, _, ShortForm, { FloatAcc, FloatReg, 0} },
564: #endif
565: {"fsubp", 0, 0xdee1, _, NoModrm, { 0, 0, 0} },
566: {"fsubs", 1, 0xd8, 4, Modrm, { Mem, 0, 0} },
567: {"fisubl", 1, 0xda, 4, Modrm, { Mem, 0, 0} },
568: {"fsubl", 1, 0xdc, 4, Modrm, { Mem, 0, 0} },
569: {"fisubs", 1, 0xde, 4, Modrm, { Mem, 0, 0} },
570:
571: /* sub reverse */
572: {"fsubr", 1, 0xd8e8, _, ShortForm, { FloatReg, 0, 0} },
573: {"fsubr", 2, 0xd8e8, _, ShortForm, { FloatReg, FloatAcc, 0} },
574: #ifdef NON_BROKEN_OPCODES
575: {"fsubr", 2, 0xdce0, _, ShortForm, { FloatAcc, FloatReg, 0} },
576: #else
577: {"fsubr", 2, 0xdce8, _, ShortForm, { FloatAcc, FloatReg, 0} },
578: #endif
579: {"fsubr", 0, 0xdce9, _, NoModrm, { 0, 0, 0} },
580: {"fsubrp", 1, 0xdae8, _, ShortForm, { FloatReg, 0, 0} },
581: {"fsubrp", 2, 0xdae8, _, ShortForm, { FloatReg, FloatAcc, 0} },
582: #ifdef NON_BROKEN_OPCODES
583: {"fsubrp", 2, 0xdee0, _, ShortForm, { FloatAcc, FloatReg, 0} },
584: #else
585: {"fsubrp", 2, 0xdee8, _, ShortForm, { FloatAcc, FloatReg, 0} },
586: #endif
587: {"fsubrp", 0, 0xdee9, _, NoModrm, { 0, 0, 0} },
588: {"fsubrs", 1, 0xd8, 5, Modrm, { Mem, 0, 0} },
589: {"fisubrl", 1, 0xda, 5, Modrm, { Mem, 0, 0} },
590: {"fsubrl", 1, 0xdc, 5, Modrm, { Mem, 0, 0} },
591: {"fisubrs", 1, 0xde, 5, Modrm, { Mem, 0, 0} },
592:
593: /* mul */
594: {"fmul", 1, 0xd8c8, _, ShortForm, { FloatReg, 0, 0} },
595: {"fmul", 2, 0xd8c8, _, ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
596: {"fmul", 0, 0xdcc9, _, NoModrm, { 0, 0, 0} },
597: {"fmulp", 1, 0xdac8, _, ShortForm, { FloatReg, 0, 0} },
598: {"fmulp", 2, 0xdac8, _, ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
599: {"fmulp", 0, 0xdec9, _, NoModrm, { 0, 0, 0} },
600: {"fmuls", 1, 0xd8, 1, Modrm, { Mem, 0, 0} },
601: {"fimull", 1, 0xda, 1, Modrm, { Mem, 0, 0} },
602: {"fmull", 1, 0xdc, 1, Modrm, { Mem, 0, 0} },
603: {"fimuls", 1, 0xde, 1, Modrm, { Mem, 0, 0} },
604:
605: /* div */
606: /* Note: intel has decided that certain of these operations are reversed
607: in assembler syntax. */
608: {"fdiv", 1, 0xd8f0, _, ShortForm, { FloatReg, 0, 0} },
609: {"fdiv", 2, 0xd8f0, _, ShortForm, { FloatReg, FloatAcc, 0} },
610: #ifdef NON_BROKEN_OPCODES
611: {"fdiv", 2, 0xdcf8, _, ShortForm, { FloatAcc, FloatReg, 0} },
612: #else
613: {"fdiv", 2, 0xdcf0, _, ShortForm, { FloatAcc, FloatReg, 0} },
614: #endif
615: {"fdiv", 0, 0xdcf1, _, NoModrm, { 0, 0, 0} },
616: {"fdivp", 1, 0xdaf0, _, ShortForm, { FloatReg, 0, 0} },
617: {"fdivp", 2, 0xdaf0, _, ShortForm, { FloatReg, FloatAcc, 0} },
618: #ifdef NON_BROKEN_OPCODES
619: {"fdivp", 2, 0xdef8, _, ShortForm, { FloatAcc, FloatReg, 0} },
620: #else
621: {"fdivp", 2, 0xdef0, _, ShortForm, { FloatAcc, FloatReg, 0} },
622: #endif
623: {"fdivp", 0, 0xdef1, _, NoModrm, { 0, 0, 0} },
624: {"fdivs", 1, 0xd8, 6, Modrm, { Mem, 0, 0} },
625: {"fidivl", 1, 0xda, 6, Modrm, { Mem, 0, 0} },
626: {"fdivl", 1, 0xdc, 6, Modrm, { Mem, 0, 0} },
627: {"fidivs", 1, 0xde, 6, Modrm, { Mem, 0, 0} },
628:
629: /* div reverse */
630: {"fdivr", 1, 0xd8f8, _, ShortForm, { FloatReg, 0, 0} },
631: {"fdivr", 2, 0xd8f8, _, ShortForm, { FloatReg, FloatAcc, 0} },
632: #ifdef NON_BROKEN_OPCODES
633: {"fdivr", 2, 0xdcf0, _, ShortForm, { FloatAcc, FloatReg, 0} },
634: #else
635: {"fdivr", 2, 0xdcf8, _, ShortForm, { FloatAcc, FloatReg, 0} },
636: #endif
637: {"fdivr", 0, 0xdcf9, _, NoModrm, { 0, 0, 0} },
638: {"fdivrp", 1, 0xdaf8, _, ShortForm, { FloatReg, 0, 0} },
639: {"fdivrp", 2, 0xdaf8, _, ShortForm, { FloatReg, FloatAcc, 0} },
640: #ifdef NON_BROKEN_OPCODES
641: {"fdivrp", 2, 0xdef0, _, ShortForm, { FloatAcc, FloatReg, 0} },
642: #else
643: {"fdivrp", 2, 0xdef8, _, ShortForm, { FloatAcc, FloatReg, 0} },
644: #endif
645: {"fdivrp", 0, 0xdef9, _, NoModrm, { 0, 0, 0} },
646: {"fdivrs", 1, 0xd8, 7, Modrm, { Mem, 0, 0} },
647: {"fidivrl", 1, 0xda, 7, Modrm, { Mem, 0, 0} },
648: {"fdivrl", 1, 0xdc, 7, Modrm, { Mem, 0, 0} },
649: {"fidivrs", 1, 0xde, 7, Modrm, { Mem, 0, 0} },
650:
651: {"f2xm1", 0, 0xd9f0, _, NoModrm, { 0, 0, 0} },
652: {"fyl2x", 0, 0xd9f1, _, NoModrm, { 0, 0, 0} },
653: {"fptan", 0, 0xd9f2, _, NoModrm, { 0, 0, 0} },
654: {"fpatan", 0, 0xd9f3, _, NoModrm, { 0, 0, 0} },
655: {"fxtract", 0, 0xd9f4, _, NoModrm, { 0, 0, 0} },
656: {"fprem1", 0, 0xd9f5, _, NoModrm, { 0, 0, 0} },
657: {"fdecstp", 0, 0xd9f6, _, NoModrm, { 0, 0, 0} },
658: {"fincstp", 0, 0xd9f7, _, NoModrm, { 0, 0, 0} },
659: {"fprem", 0, 0xd9f8, _, NoModrm, { 0, 0, 0} },
660: {"fyl2xp1", 0, 0xd9f9, _, NoModrm, { 0, 0, 0} },
661: {"fsqrt", 0, 0xd9fa, _, NoModrm, { 0, 0, 0} },
662: {"fsincos", 0, 0xd9fb, _, NoModrm, { 0, 0, 0} },
663: {"frndint", 0, 0xd9fc, _, NoModrm, { 0, 0, 0} },
664: {"fscale", 0, 0xd9fd, _, NoModrm, { 0, 0, 0} },
665: {"fsin", 0, 0xd9fe, _, NoModrm, { 0, 0, 0} },
666: {"fcos", 0, 0xd9ff, _, NoModrm, { 0, 0, 0} },
667:
668: {"fchs", 0, 0xd9e0, _, NoModrm, { 0, 0, 0} },
669: {"fabs", 0, 0xd9e1, _, NoModrm, { 0, 0, 0} },
670:
671: /* processor control */
672: {"fninit", 0, 0xdbe3, _, NoModrm, { 0, 0, 0} },
673: {"finit", 0, 0xdbe3, _, NoModrm, { 0, 0, 0} },
674: {"fldcw", 1, 0xd9, 5, Modrm, { Mem, 0, 0} },
675: {"fnstcw", 1, 0xd9, 7, Modrm, { Mem, 0, 0} },
676: {"fstcw", 1, 0xd9, 7, Modrm, { Mem, 0, 0} },
677: {"fnstsw", 1, 0xdfe0, _, NoModrm, { Acc, 0, 0} },
678: {"fnstsw", 1, 0xdd, 7, Modrm, { Mem, 0, 0} },
679: {"fnstsw", 0, 0xdfe0, _, NoModrm, { 0, 0, 0} },
680: {"fstsw", 1, 0xdfe0, _, NoModrm, { Acc, 0, 0} },
681: {"fstsw", 1, 0xdd, 7, Modrm, { Mem, 0, 0} },
682: {"fstsw", 0, 0xdfe0, _, NoModrm, { 0, 0, 0} },
683: {"fnclex", 0, 0xdbe2, _, NoModrm, { 0, 0, 0} },
684: {"fclex", 0, 0xdbe2, _, NoModrm, { 0, 0, 0} },
685: /*
686: We ignore the short format (287) versions of fstenv/fldenv & fsave/frstor
687: instructions; i'm not sure how to add them or how they are different.
688: My 386/387 book offers no details about this.
689: */
690: {"fnstenv", 1, 0xd9, 6, Modrm, { Mem, 0, 0} },
691: {"fstenv", 1, 0xd9, 6, Modrm, { Mem, 0, 0} },
692: {"fldenv", 1, 0xd9, 4, Modrm, { Mem, 0, 0} },
693: {"fnsave", 1, 0xdd, 6, Modrm, { Mem, 0, 0} },
694: {"fsave", 1, 0xdd, 6, Modrm, { Mem, 0, 0} },
695: {"frstor", 1, 0xdd, 4, Modrm, { Mem, 0, 0} },
696:
697: {"ffree", 1, 0xddc0, _, ShortForm, { FloatReg, 0, 0} },
698: {"fnop", 0, 0xd9d0, _, NoModrm, { 0, 0, 0} },
699: {"fwait", 0, 0x9b, _, NoModrm, { 0, 0, 0} },
700:
701: /*
702: opcode prefixes; we allow them as seperate insns too
703: (see prefix table below)
704: */
705: {"aword", 0, 0x67, _, NoModrm, { 0, 0, 0} },
706: {"addr16", 0, 0x67, _, NoModrm, { 0, 0, 0} },
707: {"word", 0, 0x66, _, NoModrm, { 0, 0, 0} },
708: {"data16", 0, 0x66, _, NoModrm, { 0, 0, 0} },
709: {"lock", 0, 0xf0, _, NoModrm, { 0, 0, 0} },
710: {"cs", 0, 0x2e, _, NoModrm, { 0, 0, 0} },
711: {"ds", 0, 0x3e, _, NoModrm, { 0, 0, 0} },
712: {"es", 0, 0x26, _, NoModrm, { 0, 0, 0} },
713: {"fs", 0, 0x64, _, NoModrm, { 0, 0, 0} },
714: {"gs", 0, 0x65, _, NoModrm, { 0, 0, 0} },
715: {"ss", 0, 0x36, _, NoModrm, { 0, 0, 0} },
716: {"rep", 0, 0xf3, _, NoModrm, { 0, 0, 0} },
717: {"repe", 0, 0xf3, _, NoModrm, { 0, 0, 0} },
718: {"repz", 0, 0xf3, _, NoModrm, { 0, 0, 0} },
719: {"repne", 0, 0xf2, _, NoModrm, { 0, 0, 0} },
720: {"repnz", 0, 0xf2, _, NoModrm, { 0, 0, 0} },
721:
722: /* 486 extensions */
723:
724: {"bswap", 1, 0x0fc8, _, ShortForm, { Reg32,0,0 } },
725: {"xadd", 2, 0x0fc0, _, DW|Modrm, { Reg, Reg|Mem, 0 } },
726: {"cmpxchg", 2, 0x0fb0, _, DW|Modrm, { Reg, Reg|Mem, 0 } },
727: {"invd", 0, 0x0f08, _, NoModrm, { 0, 0, 0} },
728: {"wbinvd", 0, 0x0f09, _, NoModrm, { 0, 0, 0} },
729: {"invlpg", 1, 0x0f01, 7, Modrm, { Mem, 0, 0} },
730:
731: {"", 0, 0, 0, 0, { 0, 0, 0} } /* sentinal */
732: };
733: #undef _
734:
735: static const template *const i386_optab_end
736: = i386_optab + sizeof (i386_optab)/sizeof(i386_optab[0]);
737:
738: /* 386 register table */
739:
740: static const reg_entry i386_regtab[] = {
741: /* 8 bit regs */
742: {"al", Reg8|Acc, 0}, {"cl", Reg8|ShiftCount, 1}, {"dl", Reg8, 2},
743: {"bl", Reg8, 3},
744: {"ah", Reg8, 4}, {"ch", Reg8, 5}, {"dh", Reg8, 6}, {"bh", Reg8, 7},
745: /* 16 bit regs */
746: {"ax", Reg16|Acc, 0}, {"cx", Reg16, 1}, {"dx", Reg16|InOutPortReg, 2}, {"bx", Reg16, 3},
747: {"sp", Reg16, 4}, {"bp", Reg16, 5}, {"si", Reg16, 6}, {"di", Reg16, 7},
748: /* 32 bit regs */
749: {"eax", Reg32|Acc, 0}, {"ecx", Reg32, 1}, {"edx", Reg32, 2}, {"ebx", Reg32, 3},
750: {"esp", Reg32, 4}, {"ebp", Reg32, 5}, {"esi", Reg32, 6}, {"edi", Reg32, 7},
751: /* segment registers */
752: {"es", SReg2, 0}, {"cs", SReg2, 1}, {"ss", SReg2, 2},
753: {"ds", SReg2, 3}, {"fs", SReg3, 4}, {"gs", SReg3, 5},
754: /* control registers */
755: {"cr0", Control, 0}, {"cr2", Control, 2}, {"cr3", Control, 3},
756: /* debug registers */
757: {"db0", Debug, 0}, {"db1", Debug, 1}, {"db2", Debug, 2},
758: {"db3", Debug, 3}, {"db6", Debug, 6}, {"db7", Debug, 7},
759: /* test registers */
760: {"tr6", Test, 6}, {"tr7", Test, 7},
761: /* float registers */
762: {"st(0)", FloatReg|FloatAcc, 0},
763: {"st", FloatReg|FloatAcc, 0},
764: {"st(1)", FloatReg, 1}, {"st(2)", FloatReg, 2},
765: {"st(3)", FloatReg, 3}, {"st(4)", FloatReg, 4}, {"st(5)", FloatReg, 5},
766: {"st(6)", FloatReg, 6}, {"st(7)", FloatReg, 7}
767: };
768:
769: #define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */
770:
771: static const reg_entry *const i386_regtab_end
772: = i386_regtab + sizeof(i386_regtab)/sizeof(i386_regtab[0]);
773:
774: /* segment stuff */
775: static const seg_entry cs = { "cs", 0x2e };
776: static const seg_entry ds = { "ds", 0x3e };
777: static const seg_entry ss = { "ss", 0x36 };
778: static const seg_entry es = { "es", 0x26 };
779: static const seg_entry fs = { "fs", 0x64 };
780: static const seg_entry gs = { "gs", 0x65 };
781: static const seg_entry null = { "", 0x0 };
782:
783: /*
784: This table is used to store the default segment register implied by all
785: possible memory addressing modes.
786: It is indexed by the mode & modrm entries of the modrm byte as follows:
787: index = (mode<<3) | modrm;
788: */
789: static const seg_entry *const one_byte_segment_defaults[] = {
790: /* mode 0 */
791: &ds, &ds, &ds, &ds, &null, &ds, &ds, &ds,
792: /* mode 1 */
793: &ds, &ds, &ds, &ds, &null, &ss, &ds, &ds,
794: /* mode 2 */
795: &ds, &ds, &ds, &ds, &null, &ss, &ds, &ds,
796: /* mode 3 --- not a memory reference; never referenced */
797: };
798:
799: static const seg_entry *const two_byte_segment_defaults[] = {
800: /* mode 0 */
801: &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds,
802: /* mode 1 */
803: &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds,
804: /* mode 2 */
805: &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds,
806: /* mode 3 --- not a memory reference; never referenced */
807: };
808:
809: static const prefix_entry i386_prefixtab[] = {
810: { "addr16", 0x67 }, /* address size prefix ==> 16bit addressing
811: * (How is this useful?) */
812: #define WORD_PREFIX_OPCODE 0x66
813: { "data16", 0x66 }, /* operand size prefix */
814: { "lock", 0xf0 }, /* bus lock prefix */
815: { "wait", 0x9b }, /* wait for coprocessor */
816: { "cs", 0x2e }, { "ds", 0x3e }, /* segment overrides ... */
817: { "es", 0x26 }, { "fs", 0x64 },
818: { "gs", 0x65 }, { "ss", 0x36 },
819: /* REPE & REPNE used to detect rep/repne with a non-string instruction */
820: #define REPNE 0xf2
821: #define REPE 0xf3
822: { "rep", 0xf3 }, /* repeat string instructions */
823: { "repe", 0xf3 }, { "repz", 0xf3 },
824: { "repne", 0xf2 }, { "repnz", 0xf2 }
825: };
826:
827: static const prefix_entry *const i386_prefixtab_end
828: = i386_prefixtab + sizeof(i386_prefixtab)/sizeof(i386_prefixtab[0]);
829:
830: /* end of i386-opcode.h */
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