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1.1 root 1:
2: /* Definitions for opcode table for the sparc.
3: Copyright 1989, 1991, 1992 Free Software Foundation, Inc.
4:
5: This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
6: the GNU Binutils.
7:
8:
9: GAS/GDB is free software; you can redistribute it and/or modify
10: it under the terms of the GNU General Public License as published by
11: the Free Software Foundation; either version 2, or (at your option)
12: any later version.
13:
14: GAS/GDB is distributed in the hope that it will be useful,
15: but WITHOUT ANY WARRANTY; without even the implied warranty of
16: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17: GNU General Public License for more details.
18:
19: You should have received a copy of the GNU General Public License
20: along with GAS or GDB; see the file COPYING. If not, write to
21: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
22:
23: /* The SPARC opcode table (and other related data) is defined in
24: the opcodes library in sparc-opc.c. If you change anything here, make
25: sure you fix up that file, and vice versa. */
26:
27: /* FIXME-someday: perhaps the ,a's and such should be embedded in the
28: instruction's name rather than the args. This would make gas faster, pinsn
29: slower, but would mess up some macros a bit. xoxorich. */
30:
31: #define sparc_architecture bfd_sparc_architecture
32: #define architecture_pname bfd_sparc_architecture_pname
33: #define sparc_opcode bfd_sparc_opcode
34: #define sparc_opcodes bfd_sparc_opcodes
35:
36: /*
37: * Structure of an opcode table entry.
38: * This enumerator must parallel the architecture_pname array
39: * in bfd/opc-sparc.c.
40: */
41: enum sparc_architecture {
42: v6 = 0,
43: v7,
44: v8,
45: sparclite
46: };
47:
48: extern const char *architecture_pname[];
49:
50:
51:
52: struct sparc_opcode {
53: const char *name;
54: unsigned long match; /* Bits that must be set. */
55: unsigned long lose; /* Bits that must not be set. */
56: const char *args;
57: /* This was called "delayed" in versions before the flags. */
58: char flags;
59: enum sparc_architecture architecture;
60: };
61:
62: #define F_DELAYED 1 /* Delayed branch */
63: #define F_ALIAS 2 /* Alias for a "real" instruction */
64: #define F_UNBR 4 /* Unconditional branch */
65: #define F_CONDBR 8 /* Conditional branch */
66: #define F_JSR 16 /* Subroutine call */
67:
68: /*
69:
70: All sparc opcodes are 32 bits, except for the `set' instruction (really a
71: macro), which is 64 bits. It is handled as a special case.
72:
73: The match component is a mask saying which bits must match a particular
74: opcode in order for an instruction to be an instance of that opcode.
75:
76: The args component is a string containing one character for each operand of the
77: instruction.
78:
79: Kinds of operands:
80: # Number used by optimizer. It is ignored.
81: 1 rs1 register.
82: 2 rs2 register.
83: d rd register.
84: e frs1 floating point register.
85: v frs1 floating point register (double/even).
86: V frs1 floating point register (quad/multiple of 4).
87: f frs2 floating point register.
88: B frs2 floating point register (double/even).
89: R frs2 floating point register (quad/multiple of 4).
90: g frsd floating point register.
91: H frsd floating point register (double/even).
92: J frsd floating point register (quad/multiple of 4).
93: b crs1 coprocessor register
94: c crs2 coprocessor register
95: D crsd coprocessor register
96: m alternate space register (asr) in rd
97: M alternate space register (asr) in rs1
98: h 22 high bits.
99: i 13 bit Immediate.
100: n 22 bit immediate.
101: l 22 bit PC relative immediate.
102: L 30 bit PC relative immediate.
103: a Annul. The annul bit is set.
104: A Alternate address space. Stored as 8 bits.
105: C Coprocessor state register.
106: F floating point state register.
107: p Processor state register.
108: q Floating point queue.
109: r Single register that is both rs1 and rsd.
110: Q Coprocessor queue.
111: S Special case.
112: t Trap base register.
113: w Window invalid mask register.
114: y Y register.
115:
116: The following chars are unused: (note: ,[] are used as punctuation)
117: [uxOUXY3450]
118:
119: */
120:
121: #define OP2(x) (((x)&0x7) << 22) /* op2 field of format2 insns */
122: #define OP3(x) (((x)&0x3f) << 19) /* op3 field of format3 insns */
123: #define OP(x) ((unsigned)((x)&0x3) << 30) /* op field of all insns */
124: #define OPF(x) (((x)&0x1ff) << 5) /* opf field of float insns */
125: #define F3F(x, y, z) (OP(x) | OP3(y) | OPF(z)) /* format3 float insns */
126: #define F3I(x) (((x)&0x1) << 13) /* immediate field of format 3 insns */
127: #define F2(x, y) (OP(x) | OP2(y)) /* format 2 insns */
128: #define F3(x, y, z) (OP(x) | OP3(y) | F3I(z)) /* format3 insns */
129: #define F1(x) (OP(x))
130: #define DISP30(x) ((x)&0x3fffffff)
131: #define ASI(x) (((x)&0xff) << 5) /* asi field of format3 insns */
132: #define RS2(x) ((x)&0x1f) /* rs2 field */
133: #define SIMM13(x) ((x)&0x1fff) /* simm13 field */
134: #define RD(x) (((x)&0x1f) << 25) /* destination register field */
135: #define RS1(x) (((x)&0x1f) << 14) /* rs1 field */
136: #define ASI_RS2(x) (SIMM13(x))
137:
138: #define ANNUL (1<<29)
139: #define IMMED F3I(1)
140: #define RD_G0 RD(~0)
141: #define RS1_G0 RS1(~0)
142: #define RS2_G0 RS2(~0)
143:
144: extern struct sparc_opcode sparc_opcodes[];
145: extern const int bfd_sparc_num_opcodes;
146:
147: #define NUMOPCODES bfd_sparc_num_opcodes
148:
149: /*
150: * Local Variables:
151: * fill-column: 131
152: * comment-column: 0
153: * End:
154: */
155:
156: /* end of sparc.h */
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