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1.1 root 1: /*
2: * Mach Operating System
3: * Copyright (c) 1991,1990,1989 Carnegie Mellon University
4: * All Rights Reserved.
5: *
6: * Permission to use, copy, modify and distribute this software and its
7: * documentation is hereby granted, provided that both the copyright
8: * notice and this permission notice appear in all copies of the
9: * software, derivative works or modified versions, and any portions
10: * thereof, and that both notices appear in supporting documentation.
11: *
12: * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
13: * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
14: * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
15: *
16: * Carnegie Mellon requests users of this software to return to
17: *
18: * Software Distribution Coordinator or [email protected]
19: * School of Computer Science
20: * Carnegie Mellon University
21: * Pittsburgh PA 15213-3890
22: *
23: * any improvements or extensions that they make and grant Carnegie Mellon
24: * the rights to redistribute these changes.
25: */
26: /*
27: * File: dz_7085.h
28: * Author: Alessandro Forin, Carnegie Mellon University
29: * Date: 9/90
30: *
31: * Defines for the DEC 7085 Serial Line Controller Chip
32: */
33:
34: #define NDZ_LINE 4
35:
36: /*
37: * What's hanging off those 4 lines
38: */
39:
40: #define DZ_LINE_KEYBOARD 0
41: #define DZ_LINE_MOUSE 1
42: #define DZ_LINE_MODEM 2
43: #define DZ_LINE_PRINTER 3
44:
45: /*
46: * Register layout, ignoring padding
47: */
48: typedef struct {
49: volatile unsigned short dz_csr; /* Control and Status */
50: volatile unsigned short dz_rbuf; /* Rcv buffer (RONLY) */
51: volatile unsigned short dz_tcr; /* Xmt control (R/W)*/
52: volatile unsigned short dz_tbuf; /* Xmt buffer (WONLY)*/
53: # define dz_lpr dz_rbuf /* Line parameters (WONLY)*/
54: # define dz_msr dz_tbuf /* Modem status (RONLY)*/
55: } dz_regmap_t;
56:
57: /*
58: * CSR bits
59: */
60:
61: #define DZ_CSR_MBZ 0x3c07 /* Must be zero */
62: #define DZ_CSR_MAINT 0x0008 /* rw: Maintenance mode */
63: #define DZ_CSR_CLR 0x0010 /* rw: Master clear (init) */
64: #define DZ_CSR_MSE 0x0020 /* rw: Master scan enable */
65: #define DZ_CSR_RIE 0x0040 /* rw: Rcv Interrupt Enable */
66: #define DZ_CSR_RDONE 0x0080 /* ro: Rcv done (silo avail) */
67: #define DZ_CSR_TLINE 0x0300 /* ro: Lineno ready for xmt */
68: #define DZ_CSR_TIE 0x4000 /* rw: Xmt Interrupt Enable */
69: #define DZ_CSR_TRDY 0x8000 /* ro: Xmt ready */
70:
71: /*
72: * Receiver buffer (top of silo). Read-only.
73: */
74:
75: #define DZ_SILO_DEEP 64
76:
77: #define DZ_RBUF_CHAR 0x00ff /* Received character */
78: #define DZ_RBUF_RLINE 0x0300 /* Line it came from */
79: #define DZ_RBUF_XXXX 0x0c00 /* Reads as zero */
80: #define DZ_RBUF_PERR 0x1000 /* Parity error */
81: #define DZ_RBUF_FERR 0x2000 /* Framing error (break) */
82: #define DZ_RBUF_OERR 0x4000 /* Silo overrun */
83: #define DZ_RBUF_VALID 0x8000 /* Info is valid */
84:
85: /*
86: * Line parameters register. Write-only.
87: */
88:
89: #define DZ_LPAR_LINE 0x0003 /* Bin encoded line no */
90: #define DZ_LPAR_MBZ 0xe004 /* Must be zero */
91: #define DZ_LPAR_CLEN 0x0018 /* Character length: */
92: # define DZ_LPAR_5BITS 0x0000 /* 5 bits per char */
93: # define DZ_LPAR_6BITS 0x0008 /* 6 bits per char */
94: # define DZ_LPAR_7BITS 0x0010 /* 7 bits per char */
95: # define DZ_LPAR_8BITS 0x0018 /* 8 bits per char */
96: #define DZ_LPAR_STOP 0x0020 /* stop bits: off->1, on->2 */
97: #define DZ_LPAR_PAR_ENB 0x0040 /* generate/detect parity */
98: #define DZ_LPAR_ODD_PAR 0x0080 /* generate/detect ODD parity */
99: #define DZ_LPAR_SPEED 0x0f00 /* Speed code: */
100: # define DZ_LPAR_50 0x0000 /* 50 baud */
101: # define DZ_LPAR_75 0x0100 /* 75 baud */
102: # define DZ_LPAR_110 0x0200 /* 110 baud */
103: # define DZ_LPAR_134_5 0x0300 /* 134.5 baud */
104: # define DZ_LPAR_150 0x0400 /* 150 baud */
105: # define DZ_LPAR_300 0x0500 /* 300 baud */
106: # define DZ_LPAR_600 0x0600 /* 600 baud */
107: # define DZ_LPAR_1200 0x0700 /* 1200 baud */
108: # define DZ_LPAR_1800 0x0800 /* 1800 baud */
109: # define DZ_LPAR_2000 0x0900 /* 2000 baud */
110: # define DZ_LPAR_2400 0x0a00 /* 2400 baud */
111: # define DZ_LPAR_3600 0x0b00 /* 3600 baud */
112: # define DZ_LPAR_4800 0x0c00 /* 4800 baud */
113: # define DZ_LPAR_7200 0x0d00 /* 7200 baud */
114: # define DZ_LPAR_9600 0x0e00 /* 9600 baud */
115: # define DZ_LPAR_MAX_SPEED 0x0f00 /* 19200/38400 baud */
116: #define DZ_LPAR_ENABLE 0x1000 /* Enable receiver */
117:
118: /*
119: * Xmt control register
120: */
121:
122: #define DZ_TCR_LNENB 0x000f /* rw: Xmt line enable */
123: #define DZ_TCR_MBZ 0xf0f0 /* Must be zero */
124: #define DZ_TCR_DTR3 0x0100 /* rw: DTR on printer line */
125: #define DZ_TCR_RTS3 0x0200 /* rw: RTS on printer line */
126: #define DZ_TCR_DTR2 0x0400 /* rw: DTR on modem line */
127: #define DZ_TCR_RTS2 0x0800 /* rw: RTS on modem line */
128:
129: /*
130: * Modem status register. Read-only.
131: */
132:
133: #define DZ_MSR_CTS3 0x0001 /* Clear To Send, printer line */
134: #define DZ_MSR_DSR3 0x0002 /* Data Set Ready, printer line */
135: #define DZ_MSR_CD3 0x0004 /* Carrier Detect, printer line */
136: #define DZ_MSR_RI3 0x0008 /* Ring Indicator, printer line */
137: #define DZ_MSR_XXXX 0xf0f0 /* Reads as zero */
138: #define DZ_MSR_CTS2 0x0100 /* Clear To Send, modem line */
139: #define DZ_MSR_DSR2 0x0200 /* Data Set Ready, modem line */
140: #define DZ_MSR_CD2 0x0400 /* Carrier Detect, modem line */
141: #define DZ_MSR_RI2 0x0800 /* Ring Indicator, modem line */
142:
143:
144: /*
145: * Xmt buffer
146: */
147:
148: #define DZ_TBUF_CHAR 0x00ff /* Xmt character */
149: #define DZ_TBUF_BREAK_0 0x0100 /* set line 0 to space */
150: #define DZ_TBUF_BREAK_1 0x0200 /* set line 1 to space */
151: #define DZ_TBUF_BREAK_2 0x0400 /* set line 2 to space */
152: #define DZ_TBUF_BREAK_3 0x0800 /* set line 3 to space */
153: #define DZ_TBUF_MBZ 0xf000 /* Must be zero */
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