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1.1 root 1: /*
2: * Mach Operating System
3: * Copyright (c) 1992 Carnegie Mellon University
4: * All Rights Reserved.
5: *
6: * Permission to use, copy, modify and distribute this software and its
7: * documentation is hereby granted, provided that both the copyright
8: * notice and this permission notice appear in all copies of the
9: * software, derivative works or modified versions, and any portions
10: * thereof, and that both notices appear in supporting documentation.
11: *
12: * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
13: * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
14: * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
15: *
16: * Carnegie Mellon requests users of this software to return to
17: *
18: * Software Distribution Coordinator or [email protected]
19: * School of Computer Science
20: * Carnegie Mellon University
21: * Pittsburgh PA 15213-3890
22: *
23: * any improvements or extensions that they make and grant Carnegie Mellon
24: * the rights to redistribute these changes.
25: */
26: /*
27: * File: fdi_82077_hdw.h
28: * Author: Alessandro Forin, Carnegie Mellon University
29: * Date: 1/92
30: *
31: * Defines for the Intel 82077 Floppy Disk Controller chip.
32: * Includes defines for 8272A and 82072.
33: */
34:
35: #ifndef _FDC_82077_H_
36: #define _FDC_82077_H_
37:
38: /*
39: * Chips we claim to understand, and their modes
40: */
41: #define fdc_8272a 0
42: #define fdc_82072 1
43: #define fdc_82077aa 2
44:
45: #define at_mode 0
46: #define ps2_mode 1
47: #define mod30_mode 2
48:
49: #define DRIVES_PER_FDC 4
50:
51: /*
52: * Register maps
53: */
54: typedef struct {
55: volatile unsigned char fd_sra; /* r: status register A */
56: volatile unsigned char fd_srb; /* r: status register B */
57: volatile unsigned char fd_dor; /* rw: digital output reg */
58: volatile unsigned char fd_tdr; /* rw: tape drive register */
59: volatile unsigned char fd_msr; /* r: main status register */
60: #define fd_dsr fd_msr /* w: data rate select reg */
61: volatile unsigned char fd_data; /* rw: fifo */
62: volatile unsigned char fd_xxx; /* --reserved-- */
63: volatile unsigned char fd_dir; /* r: digital input reg */
64: #define fd_ccr fd_dir /* w: config control reg */
65: } fd_regmap_t;
66:
67: typedef struct {
68: volatile unsigned char fd_msr; /* r: main status register */
69: volatile unsigned char fd_data; /* rw: data register */
70: } fd_8272a_regmap_t;
71:
72: typedef fd_8272a_regmap_t fd_82072_regmap_t;
73: /*#define fd_dsr fd_msr /* w: data rate select reg */
74:
75: /*
76: * Status register A (82077AA only)
77: *
78: * Only available in PS/2 (ps2) and Model 30 (m30) modes,
79: * not available in PC/AT (at) mode.
80: * Some signals have inverted polarity (~) on mod30
81: */
82:
83: #define FD_SRA_INT 0x80 /* interrupt */
84: #define FD_SRA_DRV2 0x40 /* 2nd drive installed (ps2) */
85: #define FD_SRA_DRQ 0x40 /* dma request (mod30) */
86: #define FD_SRA_STEP 0x20 /* step pulse (~mod30) */
87: #define FD_SRA_TRK0 0x10 /* Track 0 (~mod30) */
88: #define FD_SRA_HDSEL 0x08 /* select head 1 (~mod30) */
89: #define FD_SRA_INDX 0x04 /* Index hole (~mod30) */
90: #define FD_SRA_WP 0x02 /* write protect (~mod30) */
91: #define FD_SRA_DIR 0x01 /* step dir, 1->center (~mod30) */
92:
93: /*
94: * Status register B (82077AA only)
95: * Not available in at mode.
96: */
97:
98: #define FD_SRB_DRV2 0x80 /* 2nd drive installed (mod30) */
99: /* wired 1 on ps2 */
100:
101: #define FD_SRB_DS1 0x40 /* drive select 1 (mod30) */
102: /* wired 1 on ps2 */
103:
104: #define FD_SRB_DS0 0x20 /* drive select 0 */
105: #define FD_SRB_WRDATA 0x10 /* out data (toggle or ~trigger) */
106: #define FD_SRB_RDDATA 0x08 /* in data (toggle or ~trigger) */
107: #define FD_SRB_WE 0x04 /* write enable (~mod30) */
108: #define FD_SRB_MOT_1 0x02 /* motor enable drive 1 (ps2) */
109: #define FD_SRB_DS3 0x02 /* drive select 3 (mod30) */
110: #define FD_SRB_MOT_0 0x01 /* motor enable drive 0 (ps2) */
111: #define FD_SRB_DS2 0x01 /* drive select 2 (mod30) */
112:
113: /*
114: * Digital output register (82077AA only)
115: */
116:
117: #define FD_DOR_MOT_3 0x80 /* motor enable drive 3 */
118: #define FD_DOR_MOT_2 0x40
119: #define FD_DOR_MOT_1 0x20
120: #define FD_DOR_MOT_0 0x10
121: #define FD_DOR_DMA_GATE 0x08 /* enable dma (mod30,at) */
122: #define FD_DOR_ENABLE 0x04 /* chip reset (inverted) */
123: #define FD_DOR_DRIVE_0 0x00 /* select drive no 0 */
124: #define FD_DOR_DRIVE_1 0x01
125: #define FD_DOR_DRIVE_2 0x02
126: #define FD_DOR_DRIVE_3 0x03
127:
128: /*
129: * Tape drive register (82077AA only)
130: */
131:
132: #define FD_TDR_TAPE_1 0x01 /* unit 1 is a tape */
133: #define FD_TDR_TAPE_2 0x02
134: #define FD_TDR_TAPE_3 0x03
135: #define FD_TDR_xxx 0xfc
136:
137: /*
138: * Data-rate select register (82077AA and 82072)
139: */
140:
141: #define FD_DSR_RESET 0x80 /* self-clearing reset */
142: #define FD_DSR_POWER_DOWN 0x40 /* stop clocks and oscill */
143: #define FD_DSR_zero 0x20 /* wired zero on 82077AA */
144: #define FD_DSR_EPLL 0x20 /* enable PLL on 82072 */
145:
146: #define FD_DSR_PRECOMP_MASK 0x1c /* precompensation value */
147: # define FD_DSR_PRECOMP_SHIFT 2
148:
149: # define FD_DSR_PRECOMP_DEFAULT 0 /* 41.67@1Mbps else 125ns */
150: # define FD_DSR_PRECOMP_41_67 1
151: # define FD_DSR_PRECOMP_83_34 2
152: # define FD_DSR_PRECOMP_125_00 3
153: # define FD_DSR_PRECOMP_166_67 4
154: # define FD_DSR_PRECOMP_208_33 5
155: # define FD_DSR_PRECOMP_250_00 6
156: # define FD_DSR_PRECOMP_DISABLE 7 /* 0.00ns */
157:
158: #define FD_DSR_DATA_RATE_MASK 0x03
159: #define FD_DSR_SD_250 0x00 /* fm modulation, 250Kbps bit clock */
160: #define FD_DSR_SD_150 0x01
161: #define FD_DSR_SD_125 0x02
162:
163: #define FD_DSR_DD_500 0x00 /* mfm modulation, 500Kbps */
164: #define FD_DSR_DD_300 0x01
165: #define FD_DSR_DD_250 0x02
166: #define FD_DSR_DD_1000 0x03 /* illegal for 82077 */
167:
168: /*
169: * Main status register (all chips)
170: */
171:
172: #define FD_MSR_RQM 0x80 /* request from master (allowed) */
173: #define FD_MSR_DIO 0x40 /* data in/out, 1->master read */
174: #define FD_MSR_NON_DMA 0x20 /* dma disabled */
175: #define FD_MSR_CMD_BSY 0x10 /* command in progress */
176: #define FD_MSR_DRV_3_BSY 0x08 /* drive busy seeking */
177: #define FD_MSR_DRV_2_BSY 0x04
178: #define FD_MSR_DRV_1_BSY 0x02
179: #define FD_MSR_DRV_0_BSY 0x01
180:
181: /*
182: * FIFO (82077AA and 82072)
183: *
184: * Service delay is
185: * Threshold * 8
186: * delay = ------------- - 1.5 usecs
187: * Data-rate
188: */
189:
190: #define FD_FIFO_DEEP 16
191:
192: /*
193: * Digital input register (82077AA only)
194: */
195:
196: #define FD_DIR_DSK_CHG 0x80 /* disk was changed (~mod30) */
197:
198: #define FD_DIR_ones 0x78 /* wired ones for ps2 */
199: #define FD_DIR_zeroes 0x70 /* wired zeroes for mod30 */
200: #define FD_DIR_undef 0x7f /* undefined for at */
201:
202: #define FD_DIR_DR_MASK_PS2 0x06 /* current data rate (ps2) */
203: # define FD_DIR_DR_SHIFT_PS2 1
204: #define FD_DIR_LOW_DENS 0x01 /* zero for 500/1M dr (ps2) */
205:
206: #define FD_DIR_DMA_GATE 0x08 /* same as DOR (mod30) */
207: #define FD_DIR_NOPREC 0x04 /* same as CCR (mod30) */
208: #define FD_DIR_DR_MASK_M30 0x03 /* current data rate (mod30) */
209: # define FD_DIR_DR_SHIFT_M30 0
210:
211: /*
212: * Configuration control register (82077AA only)
213: */
214:
215: #define FD_CCR_DATA_RATE_MASK 0x03 /* see DSR for values */
216: #define FD_CCR_NOPREC 0x04 /* "has no function" (mod30) */
217:
218:
219: /*
220: * Programming
221: *
222: * Legend for command bytes, when applicable
223: *
224: * hds bit 2 of byte 1, head select (1 -> head 1)
225: * ds bits 0-1 of byte 1, drive select
226: * c cylinder number (max 76 for 8272A, else 255)
227: * h head number
228: * r sector number
229: * n number of bytes in sector
230: * eot end-of-track, e.g. final sector number
231: * gpl gap length
232: * dtl data length (for partial sectors)
233: * st0-3 status byte
234: * srt step rate time
235: * hut head unload time
236: * hlt head load time
237: * nd disable DMA
238: * mot do not turn motor on before checking drive status
239: * pcn present cylinder number
240: * ncn new cylinder number
241: * rcn relative cylinder number (new=present+rcn)
242: * sc sectors/cylinder
243: * d filler byte
244: * ? undefined
245: * hsda high-speed disk adjust (doubles motor on/off delays)
246: * moff motor off timer, one disk revolution increments
247: * mon motor on timer, ditto
248: * eis enable implied seeks
249: * dfifo disable fifo
250: * poll disable poll
251: * fifthr fifo threshold (1 to 16 bytes)
252: * pretrk precomp starts on this trackno (0-255)
253: * wgate change timings of WE signal, in perpendicular mode
254: * gap change gap2 length, in perpendicular mode
255: * ec in verify, qualify terminating conditions (sc viz eot)
256: */
257:
258: /* First byte of command, qualifiers */
259: #define FD_CMD_MT 0x80 /* Multi-track */
260: #define FD_CMD_MFM 0x40 /* Double density */
261: #define FD_CMD_SK 0x20 /* skip deleted data address mark */
262: #define FD_CMD_DIR 0x40 /* relative seek direction (up) */
263:
264: /* command codes and description */
265:
266: /*
267: * Read an entire track.
268: * Qualifiers: MFM, SK (8272A only)
269: * Bytes total: 9 code,hds+ds,c,h,r,n,eot,gpl,dtl
270: * Result total: 7 st0,st1,st2,c,h,r,n
271: */
272: #define FD_CMD_READ_TRACK 0x02
273:
274: /*
275: * Specify timers
276: * Qualifiers:
277: * Bytes total: 3 code,srt+hut,hlt+nd
278: * Result total:
279: */
280: #define FD_CMD_SPECIFY 0x03
281:
282: /*
283: * Sense status of drive
284: * Qualifiers:
285: * Bytes total: 2 code,hds+ds +mot(82072 only)
286: * Result total: 1 st3
287: */
288: #define FD_CMD_SENSE_DRIVE_STATUS 0x04
289: # define FD_CMD_SDS_NO_MOT 0x80
290:
291: /*
292: * Write
293: * Qualifiers: MT, MFM
294: * Bytes total: 9 code,hds+ds,c,h,r,n,eot,gpl,dtl
295: * Result total: 7 st0,st1,st2,c,h,r,n
296: */
297: #define FD_CMD_WRITE_DATA 0x05
298:
299: /*
300: * Read
301: * Qualifiers: MT, MFM, SK
302: * Bytes total: 9 code,hds+ds,c,h,r,n,eot,gpl,dtl
303: * Result total: 7 st0,st1,st2,c,h,r,n
304: */
305: #define FD_CMD_READ_DATA 0x06
306:
307: /*
308: * Seek to track 0
309: * Qualifiers:
310: * Bytes total: 2 code,ds
311: * Result total:
312: */
313: #define FD_CMD_RECALIBRATE 0x07
314:
315: /*
316: * Sense interrupt status
317: * Qualifiers:
318: * Bytes total: 1 code
319: * Result total: 2 st0,pcn
320: */
321: #define FD_CMD_SENSE_INT_STATUS 0x08
322:
323: /*
324: * Write data and mark deleted
325: * Qualifiers: MT, MFM
326: * Bytes total: 9 code,hds+ds,c,h,r,n,eot,gpl,dtl
327: * Result total: 7 st0,st1,st2,c,h,r,n
328: */
329: #define FD_CMD_WRITE_DELETED_DATA 0x09
330:
331: /*
332: * Read current head position
333: * Qualifiers: MFM
334: * Bytes total: 2 code,hds+ds
335: * Result total: 7 st0,st1,st2,c,h,r,n
336: */
337: #define FD_CMD_READ_ID 0x0a
338:
339: /*
340: * Set value of MOT pin, unconditionally
341: * Qualifiers: see
342: * Bytes total: 1 code+..
343: * Result total: none returns to command phase
344: */
345: #define FD_CMD_MOTOR_ON_OFF 0x0b /* 82072 only */
346:
347: # define FD_CMD_MOT_ON 0x80
348: # define FD_CMD_MOT_DS 0x60
349: # define FD_CMD_MOT_DS_SHIFT 5
350:
351: /*
352: * Read data despite deleted address mark
353: * Qualifiers: MT, MFM, SK
354: * Bytes total: 9 code,hds+ds,c,h,r,n,eot,gpl,dtl
355: * Result total: 7 st0,st1,st2,c,h,r,n
356: */
357: #define FD_CMD_READ_DELETED_DATA 0x0c
358:
359: /*
360: * Media initialization
361: * Qualifiers: MFM
362: * Bytes total: 6 code,hds+ds,n,sc,gpl,d
363: * Data: 4*sc/2 c,h,r,n
364: * Result total: 7 st0,st1,st2,?,?,?,?
365: */
366: #define FD_CMD_FORMAT_TRACK 0x0d
367:
368: /*
369: * Dump internal register status
370: * Qualifiers:
371: * Bytes total: 1 code
372: * Result total: 10 pcn0,pcn1,pcn2,pcn3,srt+hut,hlt+nd,
373: * sc/eot,hsda+moff+mon,
374: * eis+dfifo+poll+fifothr, pretrk
375: * Notes: 82077AA does not provide for hsda+moff+mon
376: */
377: #define FD_CMD_DUMPREG 0x0e /* not 8272a */
378:
379: /*
380: * Move head
381: * Qualifiers:
382: * Bytes total: 3 code,hds+ds,ncn
383: * Result total:
384: */
385: #define FD_CMD_SEEK 0x0f
386:
387: /*
388: *
389: * Qualifiers:
390: * Bytes total: 1 code
391: * Result total: 1 version
392: */
393: #define FD_CMD_VERSION 0x10 /* 82077AA only */
394: # define FD_VERSION_82077AA 0x90
395:
396: /*
397: * Scan disk data
398: * Qualifiers: MT, MFM, SK
399: * Bytes total: 9 code,hds+ds,c,h,r,n,eot,gpl,dtl
400: * Result total: 7 st0,st1,st2,c,h,r,n
401: */
402: #define FD_CMD_SCAN_EQUAL 0x11 /* 8272A only */
403:
404: /*
405: * Specify timers
406: * Qualifiers:
407: * Bytes total: 2 code,wgate+gap
408: * Result total:
409: */
410: #define FD_CMD_PERPENDICULAR_MODE 0x12 /* 82077AA only */
411:
412: /*
413: * Set configuration parameters
414: * Qualifiers:
415: * Bytes total: 4 code,hsda+moff+mon,eis+dfifo+poll+fifothr,
416: * pretrk
417: * Result total:
418: * Notes: 82077AA does not provide for hsda+moff+mon
419: */
420: #define FD_CMD_CONFIGURE 0x13 /* not 8272a */
421:
422: /*
423: * Verify CRC of disk data
424: * Qualifiers: MT, MFM, SK
425: * Bytes total: 9 code,ec+hds+ds,c,h,r,n,eot,gpl,dtl/sc
426: * Result total: 7 st0,st1,st2,c,h,r,n
427: */
428: #define FD_CMD_VERIFY 0x16 /* 82077AA only */
429:
430: /*
431: * Scan disk data (disk less-or-equal memory)
432: * Qualifiers: MT, MFM, SK
433: * Bytes total: 9 code,hds+ds,c,h,r,n,eot,gpl,dtl
434: * Result total: 7 st0,st1,st2,c,h,r,n
435: */
436: #define FD_CMD_SCAN_LOW_OR_EQUAL 0x19 /* 8272A only */
437:
438: /*
439: * Scan disk data (disk greater-or-equal memory)
440: * Qualifiers: MT, MFM, SK
441: * Bytes total: 9 code,hds+ds,c,h,r,n,eot,gpl,dtl
442: * Result total: 7 st0,st1,st2,c,h,r,n
443: */
444: #define FD_CMD_SCAN_HIGH_OR_EQUAL 0x1d /* 8272A only */
445:
446: /*
447: * Specify timers
448: * Qualifiers: DIR
449: * Bytes total: 3 code,hds+ds,rcn
450: * Result total:
451: */
452: #define FD_CMD_RELATIVE_SEEK 0x8f /* not 8272a */
453:
454: /*
455: * Any invalid command code
456: * Qualifiers:
457: * Bytes total: 1 code
458: * Result total: 1 st0 (st0 == 0x80)
459: */
460: #define FD_CMD_INVALID 0xff
461:
462:
463: /*
464: * Results and statii
465: *
466: * The typical command returns three status bytes,
467: * followed by four drive status bytes.
468: */
469:
470: /*
471: * Status register 0
472: */
473: #define FD_ST0_IC_MASK 0xc0 /* interrupt completion code */
474:
475: # define FD_ST0_IC_OK 0x00 /* terminated ok */
476: # define FD_ST0_IC_AT 0x40 /* exec phase ended sour */
477: # define FD_ST0_IC_BAD_CMD 0x80 /* didnt grok */
478: # define FD_ST0_IC_AT_POLL 0xc0 /* polling got in the way */
479:
480: #define FD_ST0_SE 0x20 /* (implied) seek ended */
481: #define FD_ST0_EC 0x10 /* equipment check */
482: #define FD_ST0_NR 0x08 /* not ready (raz for 82077aa) */
483: #define FD_ST0_H 0x04 /* currently selected head */
484: #define FD_ST0_DS 0x03 /* currently selected drive */
485:
486: /*
487: * Status register 1
488: */
489:
490: #define FD_ST1_EN 0x80 /* end of cylinder (TC not set?) */
491: #define FD_ST1_zero 0x48
492: #define FD_ST1_DE 0x20 /* data error, bad CRC */
493: #define FD_ST1_OR 0x10 /* overrun/underrun
494: #define FD_ST1_ND 0x04 /* no data, sector not found */
495: #define FD_ST1_NW 0x02 /* write protect signal */
496: #define FD_ST1_MA 0x01 /* missing address mark */
497:
498: /*
499: * Status register 2
500: */
501:
502: #define FD_ST2_zero 0x80
503: #define FD_ST2_CM 0x40 /* control mark, improper read */
504: #define FD_ST2_DD 0x20 /* the CRC error was for data */
505: #define FD_ST2_WC 0x10 /* wrong cylinder */
506: #define FD_ST2_SH 0x08 /* scan hit (8272a only) */
507: #define FD_ST2_SN 0x04 /* scan not met (8272a only) */
508: #define FD_ST2_BC 0x02 /* bad cylinder, has 0xff mark */
509: #define FD_ST2_MD 0x01 /* missing data mark */
510:
511: /*
512: * Status register 3
513: * (sense drive status)
514: */
515:
516: #define FD_ST3_FT 0x80 /* fault pin (0 if not 8272a) */
517: #define FD_ST3_WP 0x40 /* write protect pin */
518: #define FD_ST3_RDY 0x20 /* ready pin (1 on 82077aa) */
519: #define FD_ST3_T0 0x10 /* track0 pin */
520: #define FD_ST3_TS 0x08 /* two-sided pin (1 if not 8272a) */
521: #define FD_ST3_HD 0x04 /* hdsel pin */
522: #define FD_ST3_DS 0x03 /* drive select pins (1&0) */
523:
524:
525: #endif /* _FDC_82077_H_ */
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