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Annotation of Gnu-Mach/chips/ims332.h, revision 1.1

1.1     ! root        1: /* 
        !             2:  * Mach Operating System
        !             3:  * Copyright (c) 1991,1990,1989 Carnegie Mellon University
        !             4:  * All Rights Reserved.
        !             5:  * 
        !             6:  * Permission to use, copy, modify and distribute this software and its
        !             7:  * documentation is hereby granted, provided that both the copyright
        !             8:  * notice and this permission notice appear in all copies of the
        !             9:  * software, derivative works or modified versions, and any portions
        !            10:  * thereof, and that both notices appear in supporting documentation.
        !            11:  * 
        !            12:  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
        !            13:  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
        !            14:  * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
        !            15:  * 
        !            16:  * Carnegie Mellon requests users of this software to return to
        !            17:  * 
        !            18:  *  Software Distribution Coordinator  or  [email protected]
        !            19:  *  School of Computer Science
        !            20:  *  Carnegie Mellon University
        !            21:  *  Pittsburgh PA 15213-3890
        !            22:  * 
        !            23:  * any improvements or extensions that they make and grant Carnegie Mellon
        !            24:  * the rights to redistribute these changes.
        !            25:  */
        !            26: /*
        !            27:  *     File: ims332.h
        !            28:  *     Author: Alessandro Forin, Carnegie Mellon University
        !            29:  *     Date:   1/92
        !            30:  *
        !            31:  *     Defines for the Inmos IMS-G332 Colour video controller
        !            32:  */
        !            33: 
        !            34: 
        !            35: #ifndef        _CHIPS_IMS332_H_
        !            36: #define        _CHIPS_IMS332_H_        1
        !            37: 
        !            38: /*
        !            39:  * Although the chip is built to be memory-mapped
        !            40:  * it can be programmed for 32 or 64 bit addressing.
        !            41:  * Moreover, the hardware bits have been twisted
        !            42:  * even more on the machine I am writing this for.
        !            43:  * So I'll just define the chip's offsets and leave
        !            44:  * it to the implementation to define the rest.
        !            45:  */
        !            46: 
        !            47: #define        IMS332_REG_BOOT                 0x000   /* boot time config */
        !            48: 
        !            49: #define        IMS332_REG_HALF_SYNCH           0x021   /* datapath registers */
        !            50: #define        IMS332_REG_BACK_PORCH           0x022
        !            51: #define        IMS332_REG_DISPLAY              0x023
        !            52: #define        IMS332_REG_SHORT_DIS            0x024
        !            53: #define        IMS332_REG_BROAD_PULSE          0x025
        !            54: #define        IMS332_REG_V_SYNC               0x026
        !            55: #define        IMS332_REG_V_PRE_EQUALIZE       0x027
        !            56: #define        IMS332_REG_V_POST_EQUALIZE      0x028
        !            57: #define        IMS332_REG_V_BLANK              0x029
        !            58: #define        IMS332_REG_V_DISPLAY            0x02a
        !            59: #define        IMS332_REG_LINE_TIME            0x02b
        !            60: #define        IMS332_REG_LINE_START           0x02c
        !            61: #define        IMS332_REG_MEM_INIT             0x02d
        !            62: #define        IMS332_REG_XFER_DELAY           0x02e
        !            63: 
        !            64: #define        IMS332_REG_COLOR_MASK           0x040   /* color mask register */
        !            65: 
        !            66: #define        IMS332_REG_CSR_A                0x060
        !            67: 
        !            68: #define        IMS332_REG_CSR_B                0x070
        !            69: 
        !            70: #define        IMS332_REG_TOP_SCREEN           0x080   /* top-of-screen offset */
        !            71: 
        !            72: #define        IMS332_REG_CURSOR_LUT_0         0x0a1   /* cursor palette */
        !            73: #define        IMS332_REG_CURSOR_LUT_1         0x0a2
        !            74: #define        IMS332_REG_CURSOR_LUT_2         0x0a3
        !            75: 
        !            76: #define        IMS332_REG_RGB_CKSUM_0          0x0c0   /* test registers */
        !            77: #define        IMS332_REG_RGB_CKSUM_1          0x0c1
        !            78: #define        IMS332_REG_RGB_CKSUM_2          0x0c2
        !            79: 
        !            80: #define        IMS332_REG_CURSOR_LOC           0x0c7   /* cursor location */
        !            81: 
        !            82: #define        IMS332_REG_LUT_BASE             0x100   /* color palette */
        !            83: #define        IMS332_REG_LUT_END              0x1ff
        !            84: 
        !            85: #define        IMS332_REG_CURSOR_RAM           0x200   /* cursor bitmap */
        !            86: #define        IMS332_REG_CURSOR_RAM_END       0x3ff
        !            87: 
        !            88: /*
        !            89:  * Control register A
        !            90:  */
        !            91: 
        !            92: #define IMS332_CSR_A_VTG_ENABLE                0x000001        /* vertical timing generator */
        !            93: #define IMS332_CSR_A_INTERLACED                0x000002        /* screen format */
        !            94: #define IMS332_CSR_A_CCIR              0x000004        /* default is EIA */
        !            95: #define IMS332_CSR_A_SLAVE_SYNC                0x000008        /* else from our pll */
        !            96: #define IMS332_CSR_A_PLAIN_SYNC                0x000010        /* else tesselated */
        !            97: #define IMS332_CSR_A_SEPARATE_SYNC     0x000020        /* else composite */
        !            98: #define IMS332_CSR_A_VIDEO_ONLY                0x000040        /* else video+sync */
        !            99: #define IMS332_CSR_A_BLANK_PEDESTAL    0x000080        /* blank level */
        !           100: #define IMS332_CSR_A_CBLANK_IS_OUT     0x000100
        !           101: #define IMS332_CSR_A_CBLANK_NO_DELAY   0x000200
        !           102: #define IMS332_CSR_A_FORCE_BLANK       0x000400
        !           103: #define IMS332_CSR_A_BLANK_DISABLE     0x000800
        !           104: #define IMS332_CSR_A_VRAM_INCREMENT    0x003000
        !           105: #      define IMS332_VRAM_INC_1        0x000000
        !           106: #      define IMS332_VRAM_INC_256      0x001000        /* except interlaced->2 */
        !           107: #      define IMS332_VRAM_INC_512      0x002000
        !           108: #      define IMS332_VRAM_INC_1024     0x003000
        !           109: #define IMS332_CSR_A_DMA_DISABLE       0x004000
        !           110: #define IMS332_CSR_A_SYNC_DELAY_MASK   0x038000        /* 0-7 VTG clk delays */
        !           111: #define IMS332_CSR_A_PIXEL_INTERLEAVE  0x040000
        !           112: #define IMS332_CSR_A_DELAYED_SAMPLING  0x080000
        !           113: #define IMS332_CSR_A_BITS_PER_PIXEL    0x700000
        !           114: #      define IMS332_BPP_1             0x000000
        !           115: #      define IMS332_BPP_2             0x100000
        !           116: #      define IMS332_BPP_4             0x200000
        !           117: #      define IMS332_BPP_8             0x300000
        !           118: #      define IMS332_BPP_15            0x400000
        !           119: #      define IMS332_BPP_16            0x500000
        !           120: #define IMS332_CSR_A_DISABLE_CURSOR    0x800000
        !           121: 
        !           122: 
        !           123: /*
        !           124:  * Control register B is mbz
        !           125:  */
        !           126: 
        !           127: /*
        !           128:  * Boot register
        !           129:  */
        !           130: 
        !           131: #define        IMS332_BOOT_PLL                 0x00001f        /* xPLL, binary */
        !           132: #define        IMS332_BOOT_CLOCK_PLL           0x000020        /* else xternal */
        !           133: #define        IMS332_BOOT_64_BIT_MODE         0x000040        /* else 32 */
        !           134: #define        IMS332_BOOT_xxx                 0xffff80        /* reserved, mbz */
        !           135: 
        !           136: 
        !           137: #endif _CHIPS_IMS332_H_
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