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1.1 root 1: /*
2: * Mach Operating System
3: * Copyright (c) 1993 Carnegie Mellon University
4: * All Rights Reserved.
5: *
6: * Permission to use, copy, modify and distribute this software and its
7: * documentation is hereby granted, provided that both the copyright
8: * notice and this permission notice appear in all copies of the
9: * software, derivative works or modified versions, and any portions
10: * thereof, and that both notices appear in supporting documentation.
11: *
12: * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
13: * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
14: * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
15: *
16: * Carnegie Mellon requests users of this software to return to
17: *
18: * Software Distribution Coordinator or [email protected]
19: * School of Computer Science
20: * Carnegie Mellon University
21: * Pittsburgh PA 15213-3890
22: *
23: * any improvements or extensions that they make and grant Carnegie Mellon
24: * the rights to redistribute these changes.
25: */
26: /*-
27: * Copyright (c) 1991, 1992 The Regents of the University of California.
28: * All rights reserved.
29: *
30: * Redistribution and use in source and binary forms, with or without
31: * modification, are permitted provided that the following conditions
32: * are met:
33: * 1. Redistributions of source code must retain the above copyright
34: * notice, this list of conditions and the following disclaimer.
35: * 2. Redistributions in binary form must reproduce the above copyright
36: * notice, this list of conditions and the following disclaimer in the
37: * documentation and/or other materials provided with the distribution.
38: * 3. All advertising materials mentioning features or use of this software
39: * must display the following acknowledgement:
40: * This product includes software developed by the Computer Systems
41: * Engineering Group at Lawrence Berkeley Laboratory.
42: * 4. The name of the Laboratory may not be used to endorse or promote
43: * products derived from this software without specific prior written
44: * permission.
45: *
46: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
47: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
48: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
49: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
50: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
51: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
52: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
53: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
54: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
55: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
56: * SUCH DAMAGE.
57: */
58:
59: /*
60: * Bit encodings for chip commands from "Microprocessor Access Guide for
61: * Indirect Registers", p.19 Am79C30A/32A Advanced Micro Devices spec
62: * sheet (preliminary).
63: *
64: * Indirect register numbers (the value written into cr to select a given
65: * chip registers) have the form AMDR_*. Register fields look like AMD_*.
66: */
67:
68: typedef struct {
69: volatile unsigned char cr; /* command register (wo) */
70: #define ir cr /* interrupt register (ro) */
71: volatile unsigned char dr; /* data register (rw) */
72: volatile unsigned char dsr1; /* D-channel status register 1 (ro) */
73: volatile unsigned char der; /* D-channel error register (ro) */
74: volatile unsigned char dctb; /* D-channel transmit register (wo) */
75: #define dcrb dctb /* D-channel receive register (ro) */
76: volatile unsigned char bbtb; /* Bb-channel transmit register (wo) */
77: #define bbrb bbtb /* Bb-channel receive register (ro) */
78: volatile unsigned char bctb; /* Bc-channel transmit register (wo)*/
79: #define bcrb bctb /* Bc-channel receive register (ro) */
80: volatile unsigned char dsr2; /* D-channel status register 2 (ro) */
81: } amd79c30_regmap_t;
82:
83: #define AMDR_INIT 0x21
84: #define AMD_INIT_PMS_IDLE 0x00
85: #define AMD_INIT_PMS_ACTIVE 0x01
86: #define AMD_INIT_PMS_ACTIVE_DATA 0x02
87: #define AMD_INIT_INT_DISABLE (0x01 << 2)
88: #define AMD_INIT_CDS_DIV2 (0x00 << 3)
89: #define AMD_INIT_CDS_DIV1 (0x01 << 3)
90: #define AMD_INIT_CDS_DIV4 (0x02 << 3)
91: #define AMD_INIT_AS_RX (0x01 << 6)
92: #define AMD_INIT_AS_TX (0x01 << 7)
93:
94: #define AMDR_LIU_LSR 0xa1
95: #define AMDR_LIU_LPR 0xa2
96: #define AMDR_LIU_LMR1 0xa3
97: #define AMDR_LIU_LMR2 0xa4
98: #define AMDR_LIU_2_4 0xa5
99: #define AMDR_LIU_MF 0xa6
100: #define AMDR_LIU_MFSB 0xa7
101: #define AMDR_LIU_MFQB 0xa8
102:
103: #define AMDR_MUX_MCR1 0x41
104: #define AMDR_MUX_MCR2 0x42
105: #define AMDR_MUX_MCR3 0x43
106: #define AMD_MCRCHAN_NC 0x00
107: #define AMD_MCRCHAN_B1 0x01
108: #define AMD_MCRCHAN_B2 0x02
109: #define AMD_MCRCHAN_BA 0x03
110: #define AMD_MCRCHAN_BB 0x04
111: #define AMD_MCRCHAN_BC 0x05
112: #define AMD_MCRCHAN_BD 0x06
113: #define AMD_MCRCHAN_BE 0x07
114: #define AMD_MCRCHAN_BF 0x08
115: #define AMDR_MUX_MCR4 0x44
116: #define AMD_MCR4_INT_ENABLE (1 << 3)
117: #define AMD_MCR4_SWAPBB (1 << 4)
118: #define AMD_MCR4_SWAPBC (1 << 5)
119:
120: #define AMDR_MUX_1_4 0x45
121:
122: #define AMDR_MAP_X 0x61
123: #define AMDR_MAP_R 0x62
124: #define AMDR_MAP_GX 0x63
125: #define AMDR_MAP_GR 0x64
126: #define AMDR_MAP_GER 0x65
127: #define AMDR_MAP_STG 0x66
128: #define AMDR_MAP_FTGR 0x67
129: #define AMDR_MAP_ATGR 0x68
130: #define AMDR_MAP_MMR1 0x69
131: #define AMD_MMR1_ALAW 0x01
132: #define AMD_MMR1_GX 0x02
133: #define AMD_MMR1_GR 0x04
134: #define AMD_MMR1_GER 0x08
135: #define AMD_MMR1_X 0x10
136: #define AMD_MMR1_R 0x20
137: #define AMD_MMR1_STG 0x40
138: #define AMD_MMR1_LOOP 0x80
139: #define AMDR_MAP_MMR2 0x6a
140: #define AMD_MMR2_AINB 0x01
141: #define AMD_MMR2_LS 0x02
142: #define AMD_MMR2_DTMF 0x04
143: #define AMD_MMR2_GEN 0x08
144: #define AMD_MMR2_RNG 0x10
145: #define AMD_MMR2_DIS_HPF 0x20
146: #define AMD_MMR2_DIS_AZ 0x40
147: #define AMDR_MAP_1_10 0x6b
148:
149: #define AMDR_DLC_FRAR123 0x81
150: #define AMDR_DLC_SRAR123 0x82
151: #define AMDR_DLC_TAR 0x83
152: #define AMDR_DLC_DRLR 0x84
153: #define AMDR_DLC_DTCR 0x85
154: #define AMDR_DLC_DMR1 0x86
155: #define AMDR_DLC_DMR2 0x87
156: #define AMDR_DLC_1_7 0x88
157: #define AMDR_DLC_DRCR 0x89
158: #define AMDR_DLC_RNGR1 0x8a
159: #define AMDR_DLC_RNGR2 0x8b
160: #define AMDR_DLC_FRAR4 0x8c
161: #define AMDR_DLC_SRAR4 0x8d
162: #define AMDR_DLC_DMR3 0x8e
163: #define AMDR_DLC_DMR4 0x8f
164: #define AMDR_DLC_12_15 0x90
165: #define AMDR_DLC_ASR 0x91
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