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1.1 root 1: /*
2: * Mach Operating System
3: * Copyright (c) 1992,1991,1990,1989 Carnegie Mellon University
4: * All Rights Reserved.
5: *
6: * Permission to use, copy, modify and distribute this software and its
7: * documentation is hereby granted, provided that both the copyright
8: * notice and this permission notice appear in all copies of the
9: * software, derivative works or modified versions, and any portions
10: * thereof, and that both notices appear in supporting documentation.
11: *
12: * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
13: * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
14: * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
15: *
16: * Carnegie Mellon requests users of this software to return to
17: *
18: * Software Distribution Coordinator or [email protected]
19: * School of Computer Science
20: * Carnegie Mellon University
21: * Pittsburgh PA 15213-3890
22: *
23: * any improvements or extensions that they make and grant Carnegie Mellon
24: * the rights to redistribute these changes.
25: */
26: /*
27: * File: if_se.h
28: * Authors: Robert V. Baron and Alessandro Forin
29: * Date: 1989
30: *
31: */
32: /*
33: * AMD 7990 "Lance" Ethernet interface definitions.
34: * All structures are as seen from the Lance,
35: * both in the memory-alignment sense and in the
36: * byte-order sense. Mapping to host memory is
37: * model specific: on pmaxen there is a 16 bit gap
38: * every other 16 bits.
39: */
40:
41: #include <scsi/scsi_endian.h>
42:
43: /*
44: * Selection of one of the four Lance CSR is done in a
45: * two-step process: select which CSR first by writing
46: * into the RAP, then access the register via the RDP.
47: * Note that (a) the selection remains, and (b) all
48: * but CSR0 can only be accessed when the chip is stopped.
49: * These registers are mapped in the 'registers' I/O segment.
50: */
51: #ifndef se_reg_type
52: #define se_reg_type unsigned short
53: #endif
54: typedef volatile se_reg_type *se_reg_t;
55:
56: #define CSR0_SELECT 0x0 /* Valid RAP selections */
57: #define CSR1_SELECT 0x1
58: #define CSR2_SELECT 0x2
59: #define CSR3_SELECT 0x3
60:
61: /*
62: * Bit definitions for the CSR0.
63: * Legend:
64: * R=Readable W=Writeable
65: * S=Set-on-write-1 C=Clear-on-write-1
66: */
67:
68: #define LN_CSR0_INIT 0x0001 /* (RS) Initialize */
69: #define LN_CSR0_STRT 0x0002 /* (RS) Start */
70: #define LN_CSR0_STOP 0x0004 /* (RS) Stop */
71: #define LN_CSR0_TDMD 0x0008 /* (RS) Transmit demand */
72: #define LN_CSR0_TXON 0x0010 /* (R) Transmitter enabled */
73: #define LN_CSR0_RXON 0x0020 /* (R) Receiver enabled */
74: #define LN_CSR0_INEA 0x0040 /* (RW) Interrupt enable */
75: #define LN_CSR0_INTR 0x0080 /* (R) Interrupt pending */
76: #define LN_CSR0_IDON 0x0100 /* (RC) Initialization done */
77: #define LN_CSR0_TINT 0x0200 /* (RC) Transmitter interrupt */
78: #define LN_CSR0_RINT 0x0400 /* (RC) Receiver interrupt */
79: #define LN_CSR0_MERR 0x0800 /* (RC) Memory error during DMA */
80: #define LN_CSR0_MISS 0x1000 /* (RC) No available receive buffers */
81: #define LN_CSR0_CERR 0x2000 /* (RC) Signal quality (SQE) test */
82: #define LN_CSR0_BABL 0x4000 /* (RC) Babble error: xmit too long */
83: #define LN_CSR0_ERR 0x8000 /* (R) Error summary: any of the 4 above */
84:
85: #define LN_CSR0_WTC 0x7f00 /* Write-to-clear bits */
86:
87: /*
88: * Bit definitions for the CSR1.
89: */
90:
91: #define LN_CSR1_MBZ 0x0001 /* Must be zero */
92: #define LN_CSR1_IADR 0xfffe /* (RW) Initialization block address (low) */
93:
94: /*
95: * Bit definitions for the CSR2.
96: */
97:
98: #define LN_CSR2_IADR 0x00ff /* (RW) Initialization block address (high) */
99: #define LN_CSR2_XXXX 0xff00 /* (RW) Reserved */
100:
101: /*
102: * Bit definitions for the CSR3.
103: */
104:
105: #define LN_CSR3_BCON 0x0001 /* (RW) BM/HOLD Control */
106: #define LN_CSR3_ACON 0x0002 /* (RW) ALE Control */
107: #define LN_CSR3_BSWP 0x0004 /* (RW) Byte Swap */
108: #define LN_CSR3_XXXX 0xfff8 /* (RW) Reserved */
109:
110:
111: /*
112: * Initialization Block
113: *
114: * Read when the INIT command is sent to the lance.
115: */
116:
117: struct se_init_block {
118: unsigned short mode; /* Mode Register, see below */
119: unsigned short phys_addr_low; /* Ethernet address */
120: unsigned short phys_addr_med; /* Ethernet address */
121: unsigned short phys_addr_high; /* Ethernet address */
122: unsigned short logical_addr_filter0; /* Multicast filter */
123: unsigned short logical_addr_filter1; /* Multicast filter */
124: unsigned short logical_addr_filter2; /* Multicast filter */
125: unsigned short logical_addr_filter3; /* Multicast filter */
126: unsigned short recv_ring_pointer_lo; /* Receive Ring ptr, low */
127: BITFIELD_3(unsigned char,
128: recv_ring_pointer_hi, /* Receive Ring ptr, high */
129: reserved0 : 5,
130: recv_ring_len : 3); /* Length: log2(nbuffers) */
131: unsigned short xmit_ring_pointer_lo; /* Transmit Ring ptr, low */
132: BITFIELD_3(unsigned char,
133: xmit_ring_pointer_hi, /* Transmit Ring ptr, high */
134: reserved1 : 5,
135: xmit_ring_len : 3); /* Length: log2(nbuffers) */
136: };
137:
138: typedef volatile struct se_init_block *se_init_block_t;
139:
140: /*
141: * Bit definitions for the MODE word
142: * (Normally set to 0)
143: */
144:
145: #define LN_MODE_DRX 0x0001 /* Disable Receiver */
146: #define LN_MODE_DTX 0x0002 /* Disable Transmitter */
147: #define LN_MODE_LOOP 0x0004 /* Loopback mode */
148: #define LN_MODE_DTRC 0x0008 /* Disable CRC generation */
149: #define LN_MODE_COLL 0x0010 /* Force collision */
150: #define LN_MODE_DRTY 0x0020 /* Disable retry */
151: #define LN_MODE_INTL 0x0040 /* Internal Loopback mode */
152: #define LN_MODE_XXXX 0x7f80 /* Reserved */
153: #define LN_MODE_PROM 0x8000 /* Promiscuous mode */
154:
155: /*
156: * Bit definitions for the ring pointers
157: */
158:
159: #define LN_RNGP_LOW 0xfffc /* longword aligned */
160:
161:
162: /*
163: * Buffer Descriptors
164: * Legend:
165: * H-set-by-Host C-set-by-chip
166: */
167:
168: struct se_desc {
169: unsigned short addr_low; /* (H) Buffer pointer low */
170: BITFIELD_2(unsigned char,
171: addr_hi, /* (H) Buffer pointer high */
172: status); /* (HC) Buffer status */
173: unsigned short buffer_size; /* (H) Buffer length (bytes),*/
174: /* bits 15..12 must be ones */
175: union {
176: struct {
177: BITFIELD_2(unsigned short,
178: bcnt : 12, /* (C) Rcvd data size */
179: res : 4); /* Reads as zeroes */
180: } rcv;
181: struct {
182: BITFIELD_2(unsigned short,
183: TDR : 10, /* (C) Time Domain Reflectometry */
184: flg2 : 6); /* (C) Xmit status */
185: } xmt;
186: unsigned short bits;
187: } desc4;
188: #define message_size desc4.rcv.bcnt
189: #define tdr desc4.xmt.TDR
190: #define status2 desc4.xmt.flg2
191: };
192:
193: typedef volatile struct se_desc *se_desc_t;
194:
195: /*
196: * Bit definition for STATUS byte (receive case)
197: */
198:
199: #define LN_RSTATE_ENP 0x01 /* (C) End of Packet */
200: #define LN_RSTATE_STP 0x02 /* (C) Start of packet */
201: #define LN_RSTATE_BUFF 0x04 /* (C) Buffer error */
202: #define LN_RSTATE_CRC 0x08 /* (C) CRC error */
203: #define LN_RSTATE_OFLO 0x10 /* (C) SILO Overflow */
204: #define LN_RSTATE_FRAM 0x20 /* (C) Framing error */
205: #define LN_RSTATE_ERR 0x40 /* (C) Error summary */
206: #define LN_RSTATE_OWN 0x80 /* (C) Owned by Lance Chip (if set) */
207:
208:
209: /*
210: * Bit definition for STATUS byte (transmit case)
211: */
212:
213: #define LN_TSTATE_ENP 0x01 /* (H) End of Packet */
214: #define LN_TSTATE_STP 0x02 /* (H) Start of packet */
215: #define LN_TSTATE_DEF 0x04 /* (C) Deferred */
216: #define LN_TSTATE_ONE 0x08 /* (C) Retried exactly once */
217: #define LN_TSTATE_MORE 0x10 /* (C) Retried more than once */
218: #define LN_TSTATE_XXXX 0x20 /* Reserved */
219: #define LN_TSTATE_ERR 0x40 /* (C) Error summary (see status2) */
220: #define LN_TSTATE_OWN 0x80 /* (H) Owned by Lance Chip (if set) */
221:
222: /*
223: * Bit definitions for STATUS2 byte (transmit case)
224: */
225:
226: #define LN_TSTATE2_RTRY 0x01 /* (C) Failed after 16 retransmissions */
227: #define LN_TSTATE2_LCAR 0x02 /* (C) Loss of Carrier */
228: #define LN_TSTATE2_LCOL 0x04 /* (C) Late collision */
229: #define LN_TSTATE2_XXXX 0x08 /* Reserved */
230: #define LN_TSTATE2_UFLO 0x10 /* (C) Underflow (late memory) */
231: #define LN_TSTATE2_BUFF 0x20 /* (C) Buffering error (no ENP) */
232:
233: /* Errors that disable the transmitter */
234: #define LN_TSTATE2_DISABLE (LN_TSTATE2_UFLO|LN_TSTATE2_BUFF|LN_TSTATE2_RTRY)
235:
236: /*
237: * Other chip characteristics
238: */
239:
240: #define LN_MINBUF_CH 100 /* Minimum size of first lance buffer, if
241: chaining */
242:
243: #define LN_MINBUF_NOCH 60 /* Minimum size of a lance buffer, if
244: no chaining and DTCR==1 */
245:
246: #define LN_MINBUF_NOCH_RAW 64 /* Minimum size of a lance buffer, if
247: no chaining and DTCR==0 */
248:
249: /*
250: * Information for mapped ether
251: */
252: typedef struct mapped_ether_info {
253: volatile unsigned int interrupt_count;
254: /* tot interrupts received */
255: volatile unsigned short saved_csr0;
256: /* copy of csr0 at last intr */
257: unsigned char rom_stride;
258: unsigned char ram_stride;
259: /* rom&ram strides */
260: unsigned buffer_size;
261: /* how much ram for lance */
262: natural_t buffer_physaddr;
263: /* where it is in phys memory */
264: unsigned wait_event;
265: } *mapped_ether_info_t;
266:
267: #ifdef KERNEL
268: extern struct se_switch {
269: vm_offset_t regspace;
270: vm_offset_t bufspace;
271: vm_offset_t ln_bufspace;
272: vm_offset_t romspace;
273: short romstride;
274: short ramstride;
275: int ramsize;
276: void (*desc_copyin)( vm_offset_t, vm_offset_t, int);
277: void (*desc_copyout)( vm_offset_t, vm_offset_t, int);
278: void (*data_copyin)( vm_offset_t, vm_offset_t, int);
279: void (*data_copyout)( vm_offset_t, vm_offset_t, int);
280: void (*bzero)( vm_offset_t, int );
281: vm_offset_t (*mapaddr)( vm_offset_t );
282: vm_size_t (*mapoffs)( vm_size_t );
283: } *se_sw;
284: #endif KERNEL
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