![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to scc_8530.h CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [GnuMach] / Gnu-Mach / chips|
Return to scc_8530.h CVS log | Up to [GnuMach] / Gnu-Mach / chips |
1.1 root 1: /*
2: * Mach Operating System
3: * Copyright (c) 1991,1990,1989 Carnegie Mellon University
4: * All Rights Reserved.
5: *
6: * Permission to use, copy, modify and distribute this software and its
7: * documentation is hereby granted, provided that both the copyright
8: * notice and this permission notice appear in all copies of the
9: * software, derivative works or modified versions, and any portions
10: * thereof, and that both notices appear in supporting documentation.
11: *
12: * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
13: * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
14: * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
15: *
16: * Carnegie Mellon requests users of this software to return to
17: *
18: * Software Distribution Coordinator or [email protected]
19: * School of Computer Science
20: * Carnegie Mellon University
21: * Pittsburgh PA 15213-3890
22: *
23: * any improvements or extensions that they make and grant Carnegie Mellon
24: * the rights to redistribute these changes.
25: */
26: /*
27: * File: scc_8530.h
28: * Author: Alessandro Forin, Carnegie Mellon University
29: * Date: 6/91
30: *
31: * Definitions for the Zilog Z8530 SCC serial line chip
32: */
33:
34: #ifndef _SCC_8530_H_
35: #define _SCC_8530_H_
36:
37: /*
38: * Register map, needs definition of the alignment
39: * used on the specific machine.
40: * #define the 'scc_register_t' data type before
41: * including this header file. For restrictions on
42: * access modes define the set/get_datum macros.
43: * We provide defaults ifnot.
44: */
45:
46: #ifndef scc_register_t
47:
48: typedef struct scc_register {
49: volatile unsigned char datum;
50: } scc_register_t;
51:
52: #endif
53:
54:
55: #define SCC_CHANNEL_A 1
56: #define SCC_CHANNEL_B 0
57:
58: typedef struct {
59: /* Channel B is first, then A */
60: struct {
61: scc_register_t scc_command; /* reg select */
62: scc_register_t scc_data; /* Rx/Tx buffer */
63: } scc_channel[2];
64: } scc_regmap_t;
65:
66:
67: #ifndef scc_set_datum
68: #define scc_set_datum(d,v) (d) = (v)
69: #define scc_get_datum(d,v) (v) = (d)
70: #endif
71:
72: #define scc_init_reg(scc,chan) { \
73: char tmp; \
74: scc_get_datum((scc)->scc_channel[(chan)].scc_command.datum,tmp); \
75: scc_get_datum((scc)->scc_channel[(chan)].scc_command.datum,tmp); \
76: }
77:
78: #define scc_read_reg(scc,chan,reg,val) { \
79: scc_set_datum((scc)->scc_channel[(chan)].scc_command.datum,reg); \
80: scc_get_datum((scc)->scc_channel[(chan)].scc_command.datum,val); \
81: }
82:
83: #define scc_read_reg_zero(scc,chan,val) { \
84: scc_get_datum((scc)->scc_channel[(chan)].scc_command.datum,val); \
85: }
86:
87: #define scc_write_reg(scc,chan,reg,val) { \
88: scc_set_datum((scc)->scc_channel[(chan)].scc_command.datum,reg); \
89: scc_set_datum((scc)->scc_channel[(chan)].scc_command.datum,val); \
90: }
91:
92: #define scc_write_reg_zero(scc,chan,val) { \
93: scc_set_datum((scc)->scc_channel[(chan)].scc_command.datum,val); \
94: }
95:
96: #define scc_read_data(scc,chan,val) { \
97: scc_get_datum((scc)->scc_channel[(chan)].scc_data.datum,val); \
98: }
99:
100: #define scc_write_data(scc,chan,val) { \
101: scc_set_datum((scc)->scc_channel[(chan)].scc_data.datum,val); \
102: }
103:
104: /*
105: * Addressable registers
106: */
107:
108: #define SCC_RR0 0 /* status register */
109: #define SCC_RR1 1 /* special receive conditions */
110: #define SCC_RR2 2 /* (modified) interrupt vector */
111: #define SCC_RR3 3 /* interrupts pending (cha A only) */
112: #define SCC_RR8 8 /* recv buffer (alias for data) */
113: #define SCC_RR10 10 /* sdlc status */
114: #define SCC_RR12 12 /* BRG constant, low part */
115: #define SCC_RR13 13 /* BRG constant, high part */
116: #define SCC_RR15 15 /* interrupts currently enabled */
117:
118: #define SCC_WR0 0 /* reg select, and commands */
119: #define SCC_WR1 1 /* interrupt and DMA enables */
120: #define SCC_WR2 2 /* interrupt vector */
121: #define SCC_WR3 3 /* receiver params and enables */
122: #define SCC_WR4 4 /* clock/char/parity params */
123: #define SCC_WR5 5 /* xmit params and enables */
124: #define SCC_WR6 6 /* synchr SYNCH/address */
125: #define SCC_WR7 7 /* synchr SYNCH/flag */
126: #define SCC_WR8 8 /* xmit buffer (alias for data) */
127: #define SCC_WR9 9 /* vectoring and resets */
128: #define SCC_WR10 10 /* synchr params */
129: #define SCC_WR11 11 /* clocking definitions */
130: #define SCC_WR12 12 /* BRG constant, low part */
131: #define SCC_WR13 13 /* BRG constant, high part */
132: #define SCC_WR14 14 /* BRG enables and commands */
133: #define SCC_WR15 15 /* interrupt enables */
134:
135: /*
136: * Read registers defines
137: */
138:
139: #define SCC_RR0_BREAK 0x80 /* break detected (rings twice), or */
140: #define SCC_RR0_ABORT 0x80 /* abort (synchr) */
141: #define SCC_RR0_TX_UNDERRUN 0x40 /* xmit buffer empty/end of message */
142: #define SCC_RR0_CTS 0x20 /* clear-to-send pin active (sampled
143: only on intr and after RESI cmd */
144: #define SCC_RR0_SYNCH 0x10 /* SYNCH found/still hunting */
145: #define SCC_RR0_DCD 0x08 /* carrier-detect (same as CTS) */
146: #define SCC_RR0_TX_EMPTY 0x04 /* xmit buffer empty */
147: #define SCC_RR0_ZERO_COUNT 0x02 /* ? */
148: #define SCC_RR0_RX_AVAIL 0x01 /* recv fifo not empty */
149:
150: #define SCC_RR1_EOF 0x80 /* end-of-frame, SDLC mode */
151: #define SCC_RR1_CRC_ERR 0x40 /* incorrect CRC or.. */
152: #define SCC_RR1_FRAME_ERR 0x40 /* ..bad frame */
153: #define SCC_RR1_RX_OVERRUN 0x20 /* rcv fifo overflow */
154: #define SCC_RR1_PARITY_ERR 0x10 /* incorrect parity in data */
155: #define SCC_RR1_RESIDUE0 0x08
156: #define SCC_RR1_RESIDUE1 0x04
157: #define SCC_RR1_RESIDUE2 0x02
158: #define SCC_RR1_ALL_SENT 0x01
159:
160: /* RR2 contains the interrupt vector unmodified (channel A) or
161: modified as follows (channel B, if vector-include-status) */
162:
163: #define SCC_RR2_STATUS(val) ((val)&0xf)
164:
165: #define SCC_RR2_B_XMIT_DONE 0x0
166: #define SCC_RR2_B_EXT_STATUS 0x2
167: #define SCC_RR2_B_RECV_DONE 0x4
168: #define SCC_RR2_B_RECV_SPECIAL 0x6
169: #define SCC_RR2_A_XMIT_DONE 0x8
170: #define SCC_RR2_A_EXT_STATUS 0xa
171: #define SCC_RR2_A_RECV_DONE 0xc
172: #define SCC_RR2_A_RECV_SPECIAL 0xe
173:
174: /* Interrupts pending, to be read from channel A only (B raz) */
175: #define SCC_RR3_zero 0xc0
176: #define SCC_RR3_RX_IP_A 0x20
177: #define SCC_RR3_TX_IP_A 0x10
178: #define SCC_RR3_EXT_IP_A 0x08
179: #define SCC_RR3_RX_IP_B 0x04
180: #define SCC_RR3_TX_IP_B 0x02
181: #define SCC_RR3_EXT_IP_B 0x01
182:
183: /* RR8 is the receive data buffer, a 3 deep FIFO */
184: #define SCC_RECV_BUFFER SCC_RR8
185: #define SCC_RECV_FIFO_DEEP 3
186:
187: #define SCC_RR10_1CLKS 0x80
188: #define SCC_RR10_2CLKS 0x40
189: #define SCC_RR10_zero 0x2d
190: #define SCC_RR10_LOOP_SND 0x10
191: #define SCC_RR10_ON_LOOP 0x02
192:
193: /* RR12/RR13 hold the timing base, upper byte in RR13 */
194:
195: #define scc_get_timing_base(scc,chan,val) { \
196: register char tmp; \
197: scc_read_reg(scc,chan,SCC_RR12,val);\
198: scc_read_reg(scc,chan,SCC_RR13,tmp);\
199: (val) = ((val)<<8)|(tmp&0xff);\
200: }
201:
202: #define SCC_RR15_BREAK_IE 0x80
203: #define SCC_RR15_TX_UNDERRUN_IE 0x40
204: #define SCC_RR15_CTS_IE 0x20
205: #define SCC_RR15_SYNCH_IE 0x10
206: #define SCC_RR15_DCD_IE 0x08
207: #define SCC_RR15_zero 0x05
208: #define SCC_RR15_ZERO_COUNT_IE 0x02
209:
210:
211: /*
212: * Write registers defines
213: */
214:
215: /* WR0 is used for commands too */
216: #define SCC_RESET_TXURUN_LATCH 0xc0
217: #define SCC_RESET_TX_CRC 0x80
218: #define SCC_RESET_RX_CRC 0x40
219: #define SCC_RESET_HIGHEST_IUS 0x38 /* channel A only */
220: #define SCC_RESET_ERROR 0x30
221: #define SCC_RESET_TX_IP 0x28
222: #define SCC_IE_NEXT_CHAR 0x20
223: #define SCC_SEND_SDLC_ABORT 0x18
224: #define SCC_RESET_EXT_IP 0x10
225:
226: #define SCC_WR1_DMA_ENABLE 0x80 /* dma control */
227: #define SCC_WR1_DMA_MODE 0x40 /* drive ~req for DMA controller */
228: #define SCC_WR1_DMA_RECV_DATA 0x20 /* from wire to host memory */
229: /* interrupt enable/conditions */
230: #define SCC_WR1_RXI_SPECIAL_O 0x18 /* on special only */
231: #define SCC_WR1_RXI_ALL_CHAR 0x10 /* on each char, or special */
232: #define SCC_WR1_RXI_FIRST_CHAR 0x08 /* on first char, or special */
233: #define SCC_WR1_RXI_DISABLE 0x00 /* never on recv */
234: #define SCC_WR1_PARITY_IE 0x04 /* on parity errors */
235: #define SCC_WR1_TX_IE 0x02
236: #define SCC_WR1_EXT_IE 0x01
237:
238: /* WR2 is common and contains the interrupt vector (high nibble) */
239:
240: #define SCC_WR3_RX_8_BITS 0xc0
241: #define SCC_WR3_RX_6_BITS 0x80
242: #define SCC_WR3_RX_7_BITS 0x40
243: #define SCC_WR3_RX_5_BITS 0x00
244: #define SCC_WR3_AUTO_ENABLE 0x20
245: #define SCC_WR3_HUNT_MODE 0x10
246: #define SCC_WR3_RX_CRC_ENABLE 0x08
247: #define SCC_WR3_SDLC_SRCH 0x04
248: #define SCC_WR3_INHIBIT_SYNCH 0x02
249: #define SCC_WR3_RX_ENABLE 0x01
250:
251: /* Should be re-written after reset */
252: #define SCC_WR4_CLK_x64 0xc0 /* clock divide factor */
253: #define SCC_WR4_CLK_x32 0x80
254: #define SCC_WR4_CLK_x16 0x40
255: #define SCC_WR4_CLK_x1 0x00
256: #define SCC_WR4_EXT_SYNCH_MODE 0x30 /* synch modes */
257: #define SCC_WR4_SDLC_MODE 0x20
258: #define SCC_WR4_16BIT_SYNCH 0x10
259: #define SCC_WR4_8BIT_SYNCH 0x00
260: #define SCC_WR4_2_STOP 0x0c /* asynch modes */
261: #define SCC_WR4_1_5_STOP 0x08
262: #define SCC_WR4_1_STOP 0x04
263: #define SCC_WR4_SYNCH_MODE 0x00
264: #define SCC_WR4_EVEN_PARITY 0x02
265: #define SCC_WR4_PARITY_ENABLE 0x01
266:
267: #define SCC_WR5_DTR 0x80 /* drive DTR pin */
268: #define SCC_WR5_TX_8_BITS 0x60
269: #define SCC_WR5_TX_6_BITS 0x40
270: #define SCC_WR5_TX_7_BITS 0x20
271: #define SCC_WR5_TX_5_BITS 0x00
272: #define SCC_WR5_SEND_BREAK 0x10
273: #define SCC_WR5_TX_ENABLE 0x08
274: #define SCC_WR5_CRC_16 0x04 /* CRC if non zero, .. */
275: #define SCC_WR5_SDLC 0x00 /* ..SDLC otherwise */
276: #define SCC_WR5_RTS 0x02 /* drive RTS pin */
277: #define SCC_WR5_TX_CRC_ENABLE 0x01
278:
279: /* Registers WR6 and WR7 are for synch modes data, with among other things: */
280:
281: #define SCC_WR6_BISYNCH_12 0x0f
282: #define SCC_WR6_SDLC_RANGE_MASK 0x0f
283: #define SCC_WR7_SDLC_FLAG 0x7e
284:
285: /* WR8 is the transmit data buffer (no FIFO) */
286: #define SCC_XMT_BUFFER SCC_WR8
287:
288: #define SCC_WR9_HW_RESET 0xc0 /* force hardware reset */
289: #define SCC_WR9_RESET_CHA_A 0x80
290: #define SCC_WR9_RESET_CHA_B 0x40
291: #define SCC_WR9_NON_VECTORED 0x20 /* mbz for Zilog chip */
292: #define SCC_WR9_STATUS_HIGH 0x10
293: #define SCC_WR9_MASTER_IE 0x08
294: #define SCC_WR9_DLC 0x04 /* disable-lower-chain */
295: #define SCC_WR9_NV 0x02 /* no vector */
296: #define SCC_WR9_VIS 0x01 /* vector-includes-status */
297:
298: #define SCC_WR10_CRC_PRESET 0x80
299: #define SCC_WR10_FM0 0x60
300: #define SCC_WR10_FM1 0x40
301: #define SCC_WR10_NRZI 0x20
302: #define SCC_WR10_NRZ 0x00
303: #define SCC_WR10_ACTIVE_ON_POLL 0x10
304: #define SCC_WR10_MARK_IDLE 0x08 /* flag if zero */
305: #define SCC_WR10_ABORT_ON_URUN 0x04 /* flag if zero */
306: #define SCC_WR10_LOOP_MODE 0x02
307: #define SCC_WR10_6BIT_SYNCH 0x01
308: #define SCC_WR10_8BIT_SYNCH 0x00
309:
310: #define SCC_WR11_RTxC_XTAL 0x80 /* RTxC pin is input (ext oscill) */
311: #define SCC_WR11_RCLK_DPLL 0x60 /* clock received data on dpll */
312: #define SCC_WR11_RCLK_BAUDR 0x40 /* .. on BRG */
313: #define SCC_WR11_RCLK_TRc_PIN 0x20 /* .. on TRxC pin */
314: #define SCC_WR11_RCLK_RTc_PIN 0x00 /* .. on RTxC pin */
315: #define SCC_WR11_XTLK_DPLL 0x18
316: #define SCC_WR11_XTLK_BAUDR 0x10
317: #define SCC_WR11_XTLK_TRc_PIN 0x08
318: #define SCC_WR11_XTLK_RTc_PIN 0x00
319: #define SCC_WR11_TRc_OUT 0x04 /* drive TRxC pin as output from..*/
320: #define SCC_WR11_TRcOUT_DPLL 0x03 /* .. the dpll */
321: #define SCC_WR11_TRcOUT_BAUDR 0x02 /* .. the BRG */
322: #define SCC_WR11_TRcOUT_XMTCLK 0x01 /* .. the xmit clock */
323: #define SCC_WR11_TRcOUT_XTAL 0x00 /* .. the external oscillator */
324:
325: /* WR12/WR13 are for timing base preset */
326: #define scc_set_timing_base(scc,chan,val) { \
327: scc_write_reg(scc,chan,SCC_RR12,val);\
328: scc_write_reg(scc,chan,SCC_RR13,(val)>>8);\
329: }
330:
331: /* More commands in this register */
332: #define SCC_WR14_NRZI_MODE 0xe0 /* synch modulations */
333: #define SCC_WR14_FM_MODE 0xc0
334: #define SCC_WR14_RTc_SOURCE 0xa0 /* clock is from pin .. */
335: #define SCC_WR14_BAUDR_SOURCE 0x80 /* .. or internal BRG */
336: #define SCC_WR14_DISABLE_DPLL 0x60
337: #define SCC_WR14_RESET_CLKMISS 0x40
338: #define SCC_WR14_SEARCH_MODE 0x20
339: /* ..and more bitsy */
340: #define SCC_WR14_LOCAL_LOOPB 0x10
341: #define SCC_WR14_AUTO_ECHO 0x08
342: #define SCC_WR14_DTR_REQUEST 0x04
343: #define SCC_WR14_BAUDR_SRC 0x02
344: #define SCC_WR14_BAUDR_ENABLE 0x01
345:
346: #define SCC_WR15_BREAK_IE 0x80
347: #define SCC_WR15_TX_UNDERRUN_IE 0x40
348: #define SCC_WR15_CTS_IE 0x20
349: #define SCC_WR15_SYNCHUNT_IE 0x10
350: #define SCC_WR15_DCD_IE 0x08
351: #define SCC_WR15_zero 0x05
352: #define SCC_WR15_ZERO_COUNT_IE 0x02
353:
354:
355: #endif /*_SCC_8530_H_*/
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.