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1.1 root 1: /*
2: * Mach Operating System
3: * Copyright (c) 1991,1990,1989 Carnegie Mellon University
4: * All Rights Reserved.
5: *
6: * Permission to use, copy, modify and distribute this software and its
7: * documentation is hereby granted, provided that both the copyright
8: * notice and this permission notice appear in all copies of the
9: * software, derivative works or modified versions, and any portions
10: * thereof, and that both notices appear in supporting documentation.
11: *
12: * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
13: * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
14: * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
15: *
16: * Carnegie Mellon requests users of this software to return to
17: *
18: * Software Distribution Coordinator or [email protected]
19: * School of Computer Science
20: * Carnegie Mellon University
21: * Pittsburgh PA 15213-3890
22: *
23: * any improvements or extensions that they make and grant Carnegie Mellon
24: * the rights to redistribute these changes.
25: */
26: /*
27: * File: vs42x_rb.h
28: * Author: Alessandro Forin, Carnegie Mellon University
29: * Date: 5/91
30: *
31: * This file contains definitions for the VS42X-RB Storage
32: * controller, which includes a Disk controller and a
33: * SCSI controller.
34: */
35:
36: #ifndef _VS42X_RB_H_
37: #define _VS42X_RB_H_
38:
39: /*
40: * Phys addresses for the Vax3100
41: */
42: #define VAX3100_STC_BASE 0x200c0000
43: #define VAX3100_STC_RAM_COMPAT 0x200d0000
44: #define VAX3100_STC_RAM 0x202d0000
45:
46: #define VAX3100_STC_HDC9224 0x00000000 /* offsets from BASE */
47: #define VAX3100_STC_5380_A 0x00000080
48: #define VAX3100_STC_5380_B 0x00000180
49: #define VAX3100_STC_DMAREG_A 0x000000a0
50: #define VAX3100_STC_DMAREG_B 0x000001a0
51: #define VAX3100_STC_RAM_MODE 0x000000e0
52:
53: #define VAX3100_STC_DMAREG_OFF (0xa0-0x80) /* offset from 5380 */
54:
55: #define SCI_REG_SIZE 512
56:
57: /*
58: * RAM Buffer for this storage system
59: */
60: #define SCI_RAM_SIZE 128*1024
61: #define SCI_RAM_COMPATSIZE 32*1024
62: #define SCI_RAM_EXPMODE 0x01 /* char-size mode register */
63:
64: /*
65: * DMA controller for the SCSI subsystem
66: * (Defines for the NCR 5380 are elsewhere)
67: */
68:
69: typedef struct {
70: unsigned int sci_dma_adr; /* +000000a0 */
71: char pad0[0xc0-0xa0-4];
72: unsigned int sci_dma_count; /* +000000c0 */
73: unsigned int sci_dma_dir; /* +000000c4 */
74: char pad1[0xe0-0xc4-4];
75: unsigned char sci_dma_rammode;/* +000000e0 */
76: } *sci_dmaregs_t;
77:
78: #define SCI_DMADR_PUT(ptr,adr) (ptr)->sci_dma_adr = (unsigned)(adr) & SCI_DMA_COUNT_MASK;
79: #define SCI_DMADR_GET(ptr,adr) (adr) = (ptr)->sci_dma_adr;
80:
81: #define SCI_DMA_COUNT_MASK 0x0001ffff
82: #define SCI_TC_GET(ptr,cnt) {\
83: (cnt) = (ptr)->sci_dma_count;\
84: if ((cnt) & 0x00010000) (cnt) |= ~SCI_DMA_COUNT_MASK;\
85: (cnt) = -(cnt);\
86: }
87: #define SCI_TC_PUT(ptr,cnt) (ptr)->sci_dma_count = -(cnt);
88:
89: #define SCI_DMA_DIR_READ 0x00000001
90: #define SCI_DMA_DIR_WRITE 0x00000000
91:
92: /*
93: * Disk controller subsytem (ST506/412), uses a
94: * HDC 9224 Universal Disk Controller chip and
95: * addresses up to 4 disks.
96: */
97: typedef struct {
98: unsigned char hdc_rap; /* rw: reg addres ptr */
99: char pad0[3];
100: unsigned char hdc_cmd; /* w: controller command */
101: #define hdc_status hdc_cmd /* r: interrupt status */
102: char pad1[3];
103: } *sci_hdcregs_t;
104:
105: /*
106: * Register Address Pointer
107: */
108: #define UDC_DMA7 0 /* rw: DMA address bits 7:0 */
109: #define UDC_DMA15 1 /* rw: DMA address bits 15:8 */
110: #define UDC_DMA23 2 /* rw: DMA address bits 23:16 */
111: #define UDC_DSECT 3 /* rw: desired sector */
112: #define UDC_DHEAD 4 /* wo: desired head */
113: #define UDC_CHEAD 4 /* ro: current head */
114: #define UDC_DCYL 5 /* wo: desired cylinder */
115: #define UDC_CCYL 5 /* ro: current cylinder */
116: #define UDC_SCNT 6 /* wo: sector count */
117: #define UDC_RTCNT 7 /* wo: retry count */
118: #define UDC_MODE 8 /* wo: operating mode */
119: #define UDC_CSTAT 8 /* ro: chip status */
120: #define UDC_TERM 9 /* wo: termination conditions */
121: #define UDC_DSTAT 9 /* ro: drive status */
122: #define UDC_DATA 10 /* rw: data */
123:
124: /*
125: * Controller Commands
126: */
127: #define HDCC_RESET 0x00
128:
129: #define HDCC_SET_REGP 0x40 /* low 4 bits is regnum */
130:
131: #define HDCC_DESELECT 0x01
132:
133: #define HDCC_SELECT 0x20
134: # define HDCC_SELECT_IDMASK 0x03
135: # define HDCC_SELECT_DR_HD 0x04
136: # define HDCC_SELECT_DR_SD 0x08
137: # define HDCC_SELECT_DR_DD 0x0c
138:
139: #define HDCC_RESTORE_HD 0x03
140:
141: #define HDCC_RESTORE_RX 0x02
142:
143: #define HDCC_STEP 0x04
144: # define HDCC_STEP_OUT 0x02
145: # define HDCC_STEP_SKWAIT 0x01
146:
147: #define HDCC_POLL 0x10 /* low 4 bits is drive mask */
148:
149: #define HDCC_SEEK 0x50
150: # define HDCC_SEEK_STEP 0x04
151: # define HDCC_SEEK_SKWAIT 0x02
152: # define HDCC_SEEK_VFY 0x01
153:
154: #define HDCC_FORMAT 0x60
155: # define HDCC_FORMAT_DDMARK 0x10
156:
157: #define HDCC_READ_T 0x5a
158: # define HDCC_READ_XDATA 0x01
159:
160: #define HDCC_READ_P 0x58
161:
162: #define HDCC_READ_L 0x5c
163: # define HDCC_READ_L_BYPASS 0x02
164:
165: #define HDCC_WRITE_P 0x80
166: # define HDCC_WRITE_BYPASS 0x40
167: # define HDCC_WRITE_DDMARK 0x10
168:
169: #define HDCC_WRITE_L 0xa0
170:
171: /*
172: * Interrupt Status Register
173: */
174: #define HDCI_BADSECT 0x01
175: #define HDCI_OVRUN 0x02
176: #define HDCI_RDYCHNG 0x04
177: #define HDCI_TERMCOD 0x18
178: # define HDC_T_SUCCESS 0x00
179: # define HDC_T_EREAD_ID 0x08
180: # define HDC_T_EVFY 0x10
181: # define HDC_T_EXFER 0x18
182: #define HDCI_DONE 0x20
183: #define HDCI_DMAREQ 0x40
184: #define HDCI_INT 0x80 /* interrupt pending */
185:
186: /*
187: * Desired/Current Head
188: */
189: #define UDC_HEAD_HMASK 0x0f /* desired head no */
190: #define UDC_HEAD_CMASK 0x70 /* desired cyl 10:8 */
191: #define UDC_HEAD_BADSEC 0x80
192:
193: /*
194: * Sector Count
195: */
196: #define HDC_MAXDATA 256*512
197:
198: /*
199: * Retry Count
200: */
201: #define UDC_RTCNT_MASK 0xf0
202: #define UDC_RTCNT_RXDIS 0x08 /* mbz */
203: #define UDC_RTCNT_INVRDY 0x04
204: #define UDC_RTCNT_MOTOR 0x02
205: #define UDC_RTCNT_LOSPEED 0x01
206:
207: /*
208: * Mode
209: */
210: #define UDC_MODE_HD 0x80 /* hard disk mode mb1 */
211: #define UDC_MODE_CHKCOD 0x60 /* error checkin code */
212: # define UDC_MODE_CRC 0x00
213: # define UDC_MODE_EECC 0x20 /* NA */
214: # define UDC_MODE_IECC 0x40 /* hard disks internal 32 ecc */
215: # define UDC_MODE_AECC 0x60 /* NA */
216: #define UDC_MODE_DENS 0x10 /* mbz */
217: #define UDC_MODE_SRATE 0x07
218: # define UDC_MODE_RATE_HD 0x00 /* hard disk */
219: # define UDC_MODE_RATE_DD 0x01 /* double den rx23 */
220: # define UDC_MODE_RATE_SD 0x02 /* single den rz23 */
221: # define UDC_MODE_RATE_RD 0x06 /* restore drive */
222:
223: #define UDC_MODE_RX23_DD 0x81
224: #define UDC_MODE_RX23_SD 0x82
225: #define UDC_MODE_RDxx 0xc0
226: #define UDC_MODE_RD_RESTORE 0xc6
227:
228: /*
229: * Status
230: */
231: #define UDC_CSTAT_RETRIED 0x80
232: #define UDC_CSTAT_ECC 0x40
233: #define UDC_CSTAT_ECC_ERR 0x20
234: #define UDC_CSTAT_DELDATA 0x10
235: #define UDC_CSTAT_SYN_ERR 0x08
236: #define UDC_CSTAT_COMP_ERR 0x04
237: #define UDC_CSTAT_SELMASK 0x03
238: # define UDC_CSTAT_SELHD0 0x00
239: # define UDC_CSTAT_SELHD1 0x01
240: # define UDC_CSTAT_SELRX 0x02
241: # define UDC_CSTAT_SELHD2 0x03
242:
243: /*
244: * Termination
245: */
246: #define UDC_TERM_CRCPRE 0x80 /* mb1 */
247: #define UDC_TERM_IDONE 0x20
248: #define UDC_TERM_DELDAT 0x10
249: #define UDC_TERM_STAT3 0x08 /* mbz */
250: #define UDC_TERM_WPROT 0x04
251: #define UDC_TERM_IRDCHNG 0x02
252: #define UDC_TERM_WFLT 0x01
253:
254: /*
255: * Drive status
256: */
257: #define UDC_DSTAT_SELACK 0x80
258: #define UDC_DSTAT_INDEX 0x40
259: #define UDC_DSTAT_SKCOM 0x20
260: #define UDC_DSTAT_TRK0 0x10
261: #define UDC_DSTAT_STAT3 0x08 /* mbz */
262: #define UDC_DSTAT_WPROT 0x04
263: #define UDC_DSTAT_READY 0x02
264: #define UDC_DSTAT_WFLT 0x01
265:
266:
267: #endif _VS42X_RB_H_
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