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1.1 root 1: /*
2: * Mach Operating System
3: * Copyright (c) 1991,1990,1989 Carnegie Mellon University
4: * All Rights Reserved.
5: *
6: * Permission to use, copy, modify and distribute this software and its
7: * documentation is hereby granted, provided that both the copyright
8: * notice and this permission notice appear in all copies of the
9: * software, derivative works or modified versions, and any portions
10: * thereof, and that both notices appear in supporting documentation.
11: *
12: * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
13: * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
14: * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
15: *
16: * Carnegie Mellon requests users of this software to return to
17: *
18: * Software Distribution Coordinator or [email protected]
19: * School of Computer Science
20: * Carnegie Mellon University
21: * Pittsburgh PA 15213-3890
22: *
23: * any improvements or extensions that they make and grant Carnegie Mellon
24: * the rights to redistribute these changes.
25: */
26: /* **********************************************************************
27: File: blitreg.h
28: Description: Bell Tech Blit card hardware description
29:
30: $ Header: $
31:
32: Copyright Ing. C. Olivetti & C. S.p.A. 1988, 1989.
33: All rights reserved.
34: ********************************************************************** */
35: /*
36: Copyright 1988, 1989 by Olivetti Advanced Technology Center, Inc.,
37: Cupertino, California.
38:
39: All Rights Reserved
40:
41: Permission to use, copy, modify, and distribute this software and
42: its documentation for any purpose and without fee is hereby
43: granted, provided that the above copyright notice appears in all
44: copies and that both the copyright notice and this permission notice
45: appear in supporting documentation, and that the name of Olivetti
46: not be used in advertising or publicity pertaining to distribution
47: of the software without specific, written prior permission.
48:
49: OLIVETTI DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE
50: INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS,
51: IN NO EVENT SHALL OLIVETTI BE LIABLE FOR ANY SPECIAL, INDIRECT, OR
52: CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
53: LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT,
54: NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUR OF OR IN CONNECTION
55: WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
56: */
57:
58: /*
59: * Some code taken from Bob Glossman's 1987 "minimal Blit Express
60: * driver", copyright unknown. Probably copyright Intel, too.
61: */
62:
63:
64: #ifndef blitreg_DEFINED
65: #define blitreg_DEFINED
66:
67:
68: /*
69: * Registers accessible through AT I/O space. These addresses can be
70: * changed by changing bits 4-8 of the Blit's DIP switch.
71: */
72:
73: #define BLIT_CONFIG_ADDR 0x304
74: #define BLIT_DIAG_ADDR 0x306
75:
76: #if defined(sun386) || defined(i386)
77:
78:
79: /*
80: * Layout of Blit control register.
81: */
82:
83: union blit_config_reg {
84: struct config_bits {
85: unsigned dos_segment : 4;
86: unsigned reset : 1;
87: unsigned mode : 1;
88: #define BLIT_UNIX_MODE 1
89: #define BLIT_DOS_MODE 0
90: unsigned invisible : 1;
91: #define BLIT_INVISIBLE 1
92: #define BLIT_VISIBLE 0
93: unsigned unused : 1;
94: } reg;
95: u_char byte;
96: };
97:
98:
99: /*
100: * Blit Diag register.
101: * The UNIX base address is currently hardwired to BLIT_BASE_ADDR.
102: */
103:
104: #define BLIT_BASE_ADDR 0xd80000 /* base of blit memory (phys addr) */
105:
106: union blit_diag_reg {
107: struct diag_bits {
108: unsigned unix_base_addr : 5; /* phys addr (ignored) */
109: unsigned led0 : 1;
110: unsigned led1 : 1;
111: unsigned led2 : 1;
112: #define BLIT_LED_ON 1
113: #define BLIT_LED_OFF 0
114: } reg;
115: u_char byte;
116: };
117:
118: #endif /* sun386 || i386 */
119:
120:
121: /*
122: * Graphics memory, 786 registers, static RAM, and EPROM, all
123: * accessible through mapped memory.
124: */
125:
126: #define BLIT_MONOWIDTH 1664
127: #define BLIT_MONOHEIGHT 1200
128: #define BLIT_MONOFBSIZE ((BLIT_MONOWIDTH*BLIT_MONOHEIGHT)/8)
129: /* byte size of monochrome fb */
130:
131: #define BLIT_MEMSIZE 0x100000 /* num bytes mapped graphics memory */
132:
133: #define BLIT_REGSIZE 128 /* bytes taken by 786 registers */
134: #define BLIT_REGPAD (0x10000 - BLIT_REGSIZE)
135: /* padding between reg's and SRAM */
136:
137: #define BLIT_SRAMSIZE 0x4000 /* num bytes mapped for SRAM */
138: #define BLIT_SRAMPAD (0x10000 - BLIT_SRAMSIZE)
139: /* padding between SRAM and EPROM */
140:
141: #define BLIT_EPROMSIZE 0x20000 /* num bytes mapped for EPROM */
142:
143:
144: /*
145: * Layout of the Blit's mapped memory. The physical address is (or
146: * will be, eventually) determined by the Diag register (above).
147: */
148:
149: struct blitdev {
150: u_char graphmem[BLIT_MEMSIZE];
151: u_char reg786[BLIT_REGSIZE];
152: u_char pad1[BLIT_REGPAD];
153: u_char sram[BLIT_SRAMSIZE];
154: u_char pad2[BLIT_SRAMPAD];
155: u_char eprom[BLIT_EPROMSIZE];
156: };
157:
158: #define BLIT_MAPPED_SIZE sizeof(struct blitdev)
159:
160:
161: /*
162: * Offsets for 786 registers (i.e., indices into reg786[]).
163: */
164:
165: #define INTER_RELOC 0x00 /* Internal Relocation Register */
166: #define BIU_CONTROL 0x04 /* BIU Control Register */
167: #define DRAM_REFRESH 0x06 /* DRAM Refresh control register */
168: #define DRAM_CONTROL 0x08 /* DRAM control register */
169: #define DP_PRIORITY 0x0A /* DP priority register */
170: #define GP_PRIORITY 0x0C /* GP priority register*/
171: #define EXT_PRIORITY 0x0E /* External Priority Register*/
172: #define GP_OPCODE_REG 0x20 /* GP opcode register */
173: #define GP_PARM1_REG 0x22 /* GP Parameter 1 Register */
174: #define GP_PARM2_REG 0x24 /* GP Parameter 2 Register*/
175: #define GP_STAT_REG 0x26 /* GP Status Register*/
176: #define DP_OPCODE_REG 0x40 /* DP opcode register */
177: #define DP_PARM1_REG 0x42 /* DP Parameter 1 Register*/
178: #define DP_PARM2_REG 0x44 /* DP Parameter 2 Register*/
179: #define DP_PARM3_REG 0x46 /* DP Parameter 3 Register*/
180: #define DP_STAT_REG 0x48 /* DP Status Register*/
181: #define DEF_VIDEO_REG 0x4A /* DP Default Video Register*/
182:
183:
184: /*
185: * 786 BIU Control Register values.
186: */
187:
188: #define BIU_WP1 0x02 /* Write Protect One; 1 = on */
189: #define BIU_16BIT 0x10 /* access 786 registers as words; 0 = bytes */
190:
191:
192: /*
193: * 786 DRAM/VRAM Control Register values.
194: */
195:
196: /* RW bits */
197: #define MEMROWS1 0
198: #define MEMROWS2 0x20
199: #define MEMROWS3 0x40
200: #define MEMROWS4 0x60
201:
202: /* DC bits */
203: #define PG_NONINTERLV 0
204: #define FASTPG_NONINTERLV 0x10
205: #define PG_INTERLV 0x08
206: #define FASTPG_INTERLV 0x18
207:
208: /* HT bits */
209: #define HEIGHT_8K 0
210: #define HEIGHT_16K 0x1
211: #define HEIGHT_32K 0x2
212: #define HEIGHT_64K 0x3
213: #define HEIGHT_128K 0x4
214: #define HEIGHT_256K 0x5
215: #define HEIGHT_512K 0x6
216: #define HEIGHT_1M 0x7
217:
218:
219: /*
220: * 786 Graphics Processor opcodes.
221: */
222:
223: #define GECL 0x001 /* end of command list */
224: #define OP_LINK 0x200 /* LINK - "link next cmd" */
225:
226:
227: /*
228: * 786 Display Processor opcodes.
229: */
230:
231: #define DECL 1 /* end of list */
232: #define DP_LOADALL 0x500
233:
234:
235: /*
236: * Macros for accessing 786 registers (see BIU_16BIT) and EPROM.
237: */
238:
239: #define WRITEREG8(base,offset,val) \
240: (base)->reg786[(offset)] = (val) & 0xff, \
241: (base)->reg786[(offset)+1] = ((val) & 0xff00) >> 8
242:
243: #define WRITEREG16(base,offset,val) \
244: (*((u_short *)((base)->reg786+(offset)))) = (val)
245:
246: #define READREG(base,offset) \
247: (*((u_short *)(((base)->reg786+(offset)))))
248:
249: #define WRITEROM(romp,offset,val) \
250: (*((u_short *)((romp)+(offset)))) = (val)
251:
252: #define READROM(romp,offset) \
253: (*((u_short *)(((romp)+(offset)))))
254:
255:
256: /*
257: * Layout of Display Processor Control Block Registers. This block is
258: * allocated somewhere in the Blit's graphics memory, and a pointer to
259: * it is passed to the Display Processor.
260: *
261: * NOTE: The 786 only sees the memory mapped by the Blit. Thus all
262: * addresses passed to the 786 are relative to the start of the Blit's
263: * mapped memory.
264: */
265:
266: typedef int addr786_t; /* 0 = start of Blit mapped memory */
267:
268: typedef struct {
269: u_short vidstat; /* video status */
270: u_short intrmask; /* interrupt mask */
271: u_short trip_point;
272: u_short frame_intr; /* frame interrupt */
273: u_short reserved1;
274: u_short crtmode; /* CRT controller mode */
275: u_short hsyncstop; /* monitor parameters */
276: u_short hfldstart;
277: u_short hfldstop;
278: u_short linelength;
279: u_short vsyncstop;
280: u_short vfldstart;
281: u_short vfldstop;
282: u_short vframelen;
283: u_short descl; /* descriptor pointer low part */
284: u_short desch; /* descriptor pointer high part */
285: u_short reserved2;
286: u_short xyzoom;
287: u_short fldcolor;
288: u_short bordercolor;
289: u_short bpp_pad1;
290: u_short bpp_pad2;
291: u_short bpp_pad4;
292: u_short csrmode; /* & CsrPad */
293: u_short cursorx; /* cursor x location */
294: u_short cursory; /* cursor y location */
295: u_short cursorpat[16]; /* cursor pattern */
296: } DPCONTROLBLK;
297:
298:
299: /*
300: * Values for 786 Display Processor Control Block Registers.
301: */
302:
303: /* video status */
304: #define DP_DSP_ON 1 /* display on */
305: #define DP_CSR_ON 2 /* cursor on */
306:
307: /* CRT controller modes */
308: #define CRTM_NONINTER 0 /* non-interlaced */
309: #define CRTM_INTERLCD 0x40 /* interlaced */
310: #define CRTM_INTERSYN 0x60 /* interlaced - sync */
311: #define CRTM_WIN_STAT_ENABLE 0x10 /* window status enable */
312: #define CRTM_SYNC_SLAVE_MODE 0x08 /* on = operate as slave */
313: #define CRTM_BLANK_SLAVE_MODE 0x04 /* on = Blank is input */
314: #define CRTM_NORMAL_SPEED 0x00
315: #define CRTM_HIGH_SPEED 0x01
316: #define CRTM_VRYHIGH_SPEED 0x02
317: #define CRTM_SUPHIGH_SPEED 0x03
318:
319: /* cursor style */
320: #define DP_CURSOR_16X16 0x8000 /* off = 8x8 */
321: #define DP_CURSOR_CROSSHAIR 0x4000 /* off = block cursor */
322: #define DP_CURSOR_TRANSPRNT 0x2000 /* off = cursor is opaque */
323:
324:
325: /*
326: * Types for dealing with 786 Display Processor.
327: */
328:
329: typedef struct {
330: u_short lines; /* (lines in strip) - 1 */
331: u_short linkl; /* link to next strip low part */
332: u_short linkh; /* link to next strip high part */
333: u_short tiles; /* C bit, (tiles in strip) - 1 */
334: } STRIPHEADER;
335:
336: /*
337: * If the C bit is turned on, the display processor "automatically
338: * displays the background color" for areas not defined by the strips.
339: * See section 3.1.3.2 of the '786 User's Manual.
340: */
341: #define DP_C_BIT 0x8000
342:
343: typedef struct {
344: u_short bitmapw; /* width of bitmap */
345: u_short meml; /* btb mem address low part */
346: u_short memh; /* btb mem address high part */
347: u_short bppss; /* bpp, start and stop fields */
348: u_short fetchcnt; /* fetch count */
349: u_short flags; /* various flags */
350: } TILEDESC;
351:
352:
353: /*
354: * Macros for encoding addresses for strip headers & tile descriptors.
355: * addr786 is relative to the start of the Blit's mapped memory.
356: */
357:
358: #define DP_ADDRLOW(addr786) (((int)(addr786)) & 0xffff)
359: #define DP_ADDRHIGH(addr786) ((((int)(addr786)) >> 16) & 0x3f)
360:
361:
362: /*
363: * Byte offsets to useful data words within the EPROM.
364: */
365:
366: #define EP_MAGIC1 0
367: #define EP_MAGIC1_VAL 0x7856
368: #define EP_MAGIC2 2
369: #define EP_MAGIC2_VAL 0x6587
370: #define EP_DPSTART 4 /* start of DP ctl block */
371: /* (0 = start of EPROM) */
372: #define EP_DPLEN 6 /* byte length of DP control block */
373:
374: #define EP_FONTSTART 8 /* start of font */
375: /* (0 = start of EPROM) */
376: #define EP_FONTLEN 10 /* byte length of font */
377: #define EP_CHARWIDTH 12 /* bit width of each char in font */
378: #define EP_CHARHEIGHT 14
379: #define EP_NUMCHARS 16 /* num chars in font */
380:
381: /* where in the bitmap the 25x80 console screen starts */
382: #define EP_XSTART 18
383: #define EP_YSTART 20
384:
385: #define EP_SCREENWIDTH 22 /* pixels per scan line */
386: #define EP_SCREENHEIGHT 24 /* number of scan lines */
387:
388: #define EP_FIXUP_X 26 /* magic numbers for displaying */
389: #define EP_FIXUP_Y 28 /* hardware cursor */
390:
391: #define EP_BPP 30 /* bits per pixel */
392:
393:
394: /*
395: * Miscellaneous.
396: */
397:
398: #define BLIT_BLACK_BIT 0 /* try saying that 3 times fast */
399: #define BLIT_WHITE_BIT 1
400: #define BLIT_BLACK_BYTE 0
401: #define BLIT_WHITE_BYTE 0xff
402:
403:
404: #endif /* blitreg_DEFINED */
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