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1.1 root 1: /*
2: * Mach Operating System
3: * Copyright (c) 1991,1990 Carnegie Mellon University
4: * All Rights Reserved.
5: *
6: * Permission to use, copy, modify and distribute this software and its
7: * documentation is hereby granted, provided that both the copyright
8: * notice and this permission notice appear in all copies of the
9: * software, derivative works or modified versions, and any portions
10: * thereof, and that both notices appear in supporting documentation.
11: *
12: * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
13: * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
14: * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
15: *
16: * Carnegie Mellon requests users of this software to return to
17: *
18: * Software Distribution Coordinator or [email protected]
19: * School of Computer Science
20: * Carnegie Mellon University
21: * Pittsburgh PA 15213-3890
22: *
23: * any improvements or extensions that they make and grant Carnegie Mellon
24: * the rights to redistribute these changes.
25: */
26: /*
27: * Olivetti serial port driver v1.0
28: * Copyright Ing. C. Olivetti & C. S.p.A. 1988, 1989
29: * All rights reserved.
30: *
31: */
32: /*
33: Copyright 1988, 1989 by Olivetti Advanced Technology Center, Inc.,
34: Cupertino, California.
35:
36: All Rights Reserved
37:
38: Permission to use, copy, modify, and distribute this software and
39: its documentation for any purpose and without fee is hereby
40: granted, provided that the above copyright notice appears in all
41: copies and that both the copyright notice and this permission notice
42: appear in supporting documentation, and that the name of Olivetti
43: not be used in advertising or publicity pertaining to distribution
44: of the software without specific, written prior permission.
45:
46: OLIVETTI DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE
47: INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS,
48: IN NO EVENT SHALL OLIVETTI BE LIABLE FOR ANY SPECIAL, INDIRECT, OR
49: CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
50: LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT,
51: NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUR OF OR IN CONNECTION
52: WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
53: */
54:
55: #define TXRX(addr) (addr + 0)
56: #define BAUD_LSB(addr) (addr + 0)
57: #define BAUD_MSB(addr) (addr + 1)
58: #define INTR_ENAB(addr) (addr + 1)
59: #define INTR_ID(addr) (addr + 2)
60: #define FIFO_CTL(addr) (addr + 2)
61: #define LINE_CTL(addr) (addr + 3)
62: #define MODEM_CTL(addr) (addr + 4)
63: #define LINE_STAT(addr) (addr + 5)
64: #define MODEM_STAT(addr)(addr + 6)
65: #define SCR(addr) (addr + 7)
66:
67: #define MODi 0
68: #define TRAi 2
69: #define RECi 4
70: #define LINi 6
71: #define CTIi 0xc
72: #define MASKi 0xf
73:
74: /* line control register */
75: #define iWLS0 0x01 /*word length select bit 0 */
76: #define iWLS1 0x02 /*word length select bit 2 */
77: #define iSTB 0x04 /* number of stop bits */
78: #define iPEN 0x08 /* parity enable */
79: #define iEPS 0x10 /* even parity select */
80: #define iSP 0x20 /* stick parity */
81: #define iSETBREAK 0x40 /* break key */
82: #define iDLAB 0x80 /* divisor latch access bit */
83: #define i5BITS 0x00 /* 5 bits per char */
84: #define i6BITS 0x01 /* 6 bits per char */
85: #define i7BITS 0x02 /* 7 bits per char */
86: #define i8BITS 0x03 /* 8 bits per char */
87:
88: /* line status register */
89: #define iDR 0x01 /* data ready */
90: #define iOR 0x02 /* overrun error */
91: #define iPE 0x04 /* parity error */
92: #define iFE 0x08 /* framing error */
93: #define iBRKINTR 0x10 /* a break has arrived */
94: #define iTHRE 0x20 /* tx hold reg is now empty */
95: #define iTSRE 0x40 /* tx shift reg is now empty */
96:
97: /* interrupt id regisger */
98: #define iMODEM_INTR 0x01
99: #define iTX_INTR 0x02
100: #define iRX_INTR 0x04
101: #define iERROR_INTR 0x08
102:
103: /* interrupt enable register */
104: #define iRX_ENAB 0x01
105: #define iTX_ENAB 0x02
106: #define iERROR_ENAB 0x04
107: #define iMODEM_ENAB 0x08
108:
109: /* modem control register */
110: #define iDTR 0x01 /* data terminal ready */
111: #define iRTS 0x02 /* request to send */
112: #define iOUT1 0x04 /* COM aux line -not used */
113: #define iOUT2 0x08 /* turns intr to 386 on/off */
114: #define iLOOP 0x10 /* loopback for diagnostics */
115:
116: /* modem status register */
117: #define iDCTS 0x01 /* delta clear to send */
118: #define iDDSR 0x02 /* delta data set ready */
119: #define iTERI 0x04 /* trail edge ring indicator */
120: #define iDRLSD 0x08 /* delta rx line sig detect */
121: #define iCTS 0x10 /* clear to send */
122: #define iDSR 0x20 /* data set ready */
123: #define iRI 0x40 /* ring indicator */
124: #define iRLSD 0x80 /* rx line sig detect */
125:
126: /* fifo control register (only in 16550) */
127: #define iFIFOENA 0x01 /* Enable fifos */
128: #define iCLRRCVRFIFO 0x02 /* Clear receive fifo */
129: #define iCLRXMITFIFO 0x04 /* Clear transmit fifo */
130: #define iDMAMODE 0x08 /* DMA transfer enable */
131: #define iFIFO1CH 0x00 /* Receive fifo trigger level 1 char */
132: #define iFIFO4CH 0x40 /* Receive fifo trigger level 4 chars*/
133: #define iFIFO8CH 0x80 /* Receive fifo trigger level 8 chars*/
134: #define iFIFO14CH 0xc0 /* Receive fifo trigger level 14 chars*/
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