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Annotation of Gnu-Mach/i386/i386at/gpl/if_nsreg.h, revision 1.1

1.1     ! root        1: /* 
        !             2:  * Copyright (c) 1994 Shantanu Goel
        !             3:  * All Rights Reserved.
        !             4:  * 
        !             5:  * Permission to use, copy, modify and distribute this software and its
        !             6:  * documentation is hereby granted, provided that both the copyright
        !             7:  * notice and this permission notice appear in all copies of the
        !             8:  * software, derivative works or modified versions, and any portions
        !             9:  * thereof, and that both notices appear in supporting documentation.
        !            10:  * 
        !            11:  * THE AUTHOR ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
        !            12:  * CONDITION.  THE AUTHOR DISCLAIMS ANY LIABILITY OF ANY KIND FOR
        !            13:  * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
        !            14:  */
        !            15: 
        !            16: /*
        !            17:  * Written 1992,1993 by Donald Becker.
        !            18:  * 
        !            19:  * Copyright 1993 United States Government as represented by the
        !            20:  * Director, National Security Agency.  This software may be used and
        !            21:  * distributed according to the terms of the GNU Public License,
        !            22:  * incorporated herein by reference.
        !            23:  *
        !            24:  * The Author may be reached as [email protected] or
        !            25:  * C/O Supercomputing Research Ctr., 17100 Science Dr., Bowie MD 20715
        !            26:  */
        !            27: 
        !            28: /*
        !            29:  * Generic NS8390 definitions.
        !            30:  * Derived from the Linux driver by Donald Becker.
        !            31:  */
        !            32: 
        !            33: #define ETHER_ADDR_LEN 6
        !            34: 
        !            35: /*
        !            36:  * 8390 state.
        !            37:  */
        !            38: struct nssoftc {
        !            39:        struct  ifnet sc_if;    /* interface header */
        !            40:        u_char  sc_addr[ETHER_ADDR_LEN];        /* station address */
        !            41:        /*
        !            42:         * The following are board specific.
        !            43:         * reset() - resets the NIC and board
        !            44:         * input() - read data into buffer from supplied offset
        !            45:         * output() - write data from buffer into supplied page
        !            46:         *            the data is padded if necessary and the actual
        !            47:         *            count is returned.
        !            48:         */
        !            49:        void    (*sc_reset)(struct nssoftc *);
        !            50:        void    (*sc_input)(struct nssoftc *, int, char *, int);
        !            51:        int     (*sc_output)(struct nssoftc *, int, char *, int);
        !            52:        int     sc_word16:1;    /* 16 bit (vs 8 bit) board */
        !            53:        int     sc_txing:1;     /* transmit active */
        !            54:        int     sc_pingpong:1;  /* using ping-pong driver */
        !            55:        int     sc_oactive:1;   /* transmitter is active */
        !            56:        u_char  sc_txstrtpg;    /* starting transmit page */
        !            57:        u_char  sc_rxstrtpg;    /* starting receive page */
        !            58:        u_char  sc_stoppg;      /* stop page */
        !            59:        u_char  sc_curpg;       /* current page */
        !            60:        short   sc_tx1;         /* packet lengths for ping-pong transmit */
        !            61:        short   sc_tx2;
        !            62:        short   sc_lasttx;
        !            63:        u_char  sc_timer;       /* watchdog */
        !            64:        int     sc_port;        /* I/O port of 8390 */
        !            65:        char    *sc_name;       /* name of board */
        !            66:        int     sc_unit;        /* unit in driver */
        !            67: };
        !            68: 
        !            69: #define TX_2X_PAGES    12
        !            70: #define TX_1X_PAGES    6
        !            71: #define TX_PAGES(ns)   ((ns)->sc_pingpong ? TX_2X_PAGES : TX_1X_PAGES)
        !            72: 
        !            73: /* Some generic ethernet register configurations. */
        !            74: #define E8390_TX_IRQ_MASK 0xa  /* For register EN0_ISR */
        !            75: #define E8390_RX_IRQ_MASK 0x5
        !            76: #define E8390_RXCONFIG    0x4  /* EN0_RXCR: broadcasts, no multicast,errors */
        !            77: #define E8390_RXOFF      0x20  /* EN0_RXCR: Accept no packets */
        !            78: #define E8390_TXCONFIG   0x00  /* EN0_TXCR: Normal transmit mode */
        !            79: #define E8390_TXOFF      0x02  /* EN0_TXCR: Transmitter off */
        !            80: 
        !            81: /*  Register accessed at EN_CMD, the 8390 base addr.  */
        !            82: #define E8390_STOP     0x01    /* Stop and reset the chip */
        !            83: #define E8390_START    0x02    /* Start the chip, clear reset */
        !            84: #define E8390_TRANS    0x04    /* Transmit a frame */
        !            85: #define E8390_RREAD    0x08    /* Remote read */
        !            86: #define E8390_RWRITE   0x10    /* Remote write  */
        !            87: #define E8390_NODMA    0x20    /* Remote DMA */
        !            88: #define E8390_PAGE0    0x00    /* Select page chip registers */
        !            89: #define E8390_PAGE1    0x40    /* using the two high-order bits */
        !            90: #define E8390_PAGE2    0x80    /* Page 3 is invalid. */
        !            91: 
        !            92: #define E8390_CMD      0x00    /* The command register (for all pages) */
        !            93: /* Page 0 register offsets. */
        !            94: #define EN0_CLDALO     0x01    /* Low byte of current local dma addr  RD */
        !            95: #define EN0_STARTPG    0x01    /* Starting page of ring bfr WR */
        !            96: #define EN0_CLDAHI     0x02    /* High byte of current local dma addr  RD */
        !            97: #define EN0_STOPPG     0x02    /* Ending page +1 of ring bfr WR */
        !            98: #define EN0_BOUNDARY   0x03    /* Boundary page of ring bfr RD WR */
        !            99: #define EN0_TSR                0x04    /* Transmit status reg RD */
        !           100: #define EN0_TPSR       0x04    /* Transmit starting page WR */
        !           101: #define EN0_NCR                0x05    /* Number of collision reg RD */
        !           102: #define EN0_TCNTLO     0x05    /* Low  byte of tx byte count WR */
        !           103: #define EN0_FIFO       0x06    /* FIFO RD */
        !           104: #define EN0_TCNTHI     0x06    /* High byte of tx byte count WR */
        !           105: #define EN0_ISR                0x07    /* Interrupt status reg RD WR */
        !           106: #define EN0_CRDALO     0x08    /* low byte of current remote dma address RD */
        !           107: #define EN0_RSARLO     0x08    /* Remote start address reg 0 */
        !           108: #define EN0_CRDAHI     0x09    /* high byte, current remote dma address RD */
        !           109: #define EN0_RSARHI     0x09    /* Remote start address reg 1 */
        !           110: #define EN0_RCNTLO     0x0a    /* Remote byte count reg WR */
        !           111: #define EN0_RCNTHI     0x0b    /* Remote byte count reg WR */
        !           112: #define EN0_RSR                0x0c    /* rx status reg RD */
        !           113: #define EN0_RXCR       0x0c    /* RX configuration reg WR */
        !           114: #define EN0_TXCR       0x0d    /* TX configuration reg WR */
        !           115: #define EN0_COUNTER0   0x0d    /* Rcv alignment error counter RD */
        !           116: #define EN0_DCFG       0x0e    /* Data configuration reg WR */
        !           117: #define EN0_COUNTER1   0x0e    /* Rcv CRC error counter RD */
        !           118: #define EN0_IMR                0x0f    /* Interrupt mask reg WR */
        !           119: #define EN0_COUNTER2   0x0f    /* Rcv missed frame error counter RD */
        !           120: 
        !           121: /* Bits in EN0_ISR - Interrupt status register */
        !           122: #define ENISR_RX       0x01    /* Receiver, no error */
        !           123: #define ENISR_TX       0x02    /* Transmitter, no error */
        !           124: #define ENISR_RX_ERR   0x04    /* Receiver, with error */
        !           125: #define ENISR_TX_ERR   0x08    /* Transmitter, with error */
        !           126: #define ENISR_OVER     0x10    /* Receiver overwrote the ring */
        !           127: #define ENISR_COUNTERS 0x20    /* Counters need emptying */
        !           128: #define ENISR_RDC      0x40    /* remote dma complete */
        !           129: #define ENISR_RESET    0x80    /* Reset completed */
        !           130: #define ENISR_ALL      0x3f    /* Interrupts we will enable */
        !           131: 
        !           132: /* Bits in EN0_DCFG - Data config register */
        !           133: #define ENDCFG_WTS     0x01    /* word transfer mode selection */
        !           134: 
        !           135: /* Page 1 register offsets. */
        !           136: #define EN1_PHYS   0x01        /* This board's physical enet addr RD WR */
        !           137: #define EN1_CURPAG 0x07        /* Current memory page RD WR */
        !           138: #define EN1_MULT   0x08        /* Multicast filter mask array (8 bytes) RD WR */
        !           139: 
        !           140: /* Bits in received packet status byte and EN0_RSR*/
        !           141: #define ENRSR_RXOK     0x01    /* Received a good packet */
        !           142: #define ENRSR_CRC      0x02    /* CRC error */
        !           143: #define ENRSR_FAE      0x04    /* frame alignment error */
        !           144: #define ENRSR_FO       0x08    /* FIFO overrun */
        !           145: #define ENRSR_MPA      0x10    /* missed pkt */
        !           146: #define ENRSR_PHY      0x20    /* physical/multicase address */
        !           147: #define ENRSR_DIS      0x40    /* receiver disable. set in monitor mode */
        !           148: #define ENRSR_DEF      0x80    /* deferring */
        !           149: 
        !           150: /* Transmitted packet status, EN0_TSR. */
        !           151: #define ENTSR_PTX 0x01 /* Packet transmitted without error */
        !           152: #define ENTSR_ND  0x02 /* The transmit wasn't deferred. */
        !           153: #define ENTSR_COL 0x04 /* The transmit collided at least once. */
        !           154: #define ENTSR_ABT 0x08  /* The transmit collided 16 times, and was deferred. */
        !           155: #define ENTSR_CRS 0x10 /* The carrier sense was lost. */
        !           156: #define ENTSR_FU  0x20  /* A "FIFO underrun" occured during transmit. */
        !           157: #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
        !           158: #define ENTSR_OWC 0x80  /* There was an out-of-window collision. */
        !           159: 
        !           160: /* The per-packet-header format. */
        !           161: struct nspkthdr {
        !           162:        u_char  status; /* status */
        !           163:        u_char  next;   /* pointer to next packet. */
        !           164:        u_short count;  /* header + packet length in bytes */
        !           165: };
        !           166: 
        !           167: void   nsinit(struct nssoftc *);
        !           168: void   nsstart(struct nssoftc *);
        !           169: void   nsintr(struct nssoftc *);

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