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1.1 root 1: /*
2: * linux/drivers/block/triton.c Version 1.06 Feb 6, 1996
3: *
4: * Copyright (c) 1995-1996 Mark Lord
5: * May be copied or modified under the terms of the GNU General Public License
6: */
7:
8: /*
9: * This module provides support for the Bus Master IDE DMA function
10: * of the Intel PCI Triton chipset (82371FB).
11: *
12: * DMA is currently supported only for hard disk drives (not cdroms).
13: *
14: * Support for cdroms will likely be added at a later date,
15: * after broader experience has been obtained with hard disks.
16: *
17: * Up to four drives may be enabled for DMA, and the Triton chipset will
18: * (hopefully) arbitrate the PCI bus among them. Note that the 82371FB chip
19: * provides a single "line buffer" for the BM IDE function, so performance of
20: * multiple (two) drives doing DMA simultaneously will suffer somewhat,
21: * as they contest for that resource bottleneck. This is handled transparently
22: * inside the 82371FB chip.
23: *
24: * By default, DMA support is prepared for use, but is currently enabled only
25: * for drives which support multi-word DMA mode2 (mword2), or which are
26: * recognized as "good" (see table below). Drives with only mode0 or mode1
27: * (single or multi) DMA should also work with this chipset/driver (eg. MC2112A)
28: * but are not enabled by default. Use "hdparm -i" to view modes supported
29: * by a given drive.
30: *
31: * The hdparm-2.4 (or later) utility can be used for manually enabling/disabling
32: * DMA support, but must be (re-)compiled against this kernel version or later.
33: *
34: * To enable DMA, use "hdparm -d1 /dev/hd?" on a per-drive basis after booting.
35: * If problems arise, ide.c will disable DMA operation after a few retries.
36: * This error recovery mechanism works and has been extremely well exercised.
37: *
38: * IDE drives, depending on their vintage, may support several different modes
39: * of DMA operation. The boot-time modes are indicated with a "*" in
40: * the "hdparm -i" listing, and can be changed with *knowledgeable* use of
41: * the "hdparm -X" feature. There is seldom a need to do this, as drives
42: * normally power-up with their "best" PIO/DMA modes enabled.
43: *
44: * Testing was done with an ASUS P55TP4XE/100 system and the following drives:
45: *
46: * Quantum Fireball 1080A (1Gig w/83kB buffer), DMA mode2, PIO mode4.
47: * - DMA mode2 works well (7.4MB/sec), despite the tiny on-drive buffer.
48: * - This drive also does PIO mode4, at about the same speed as DMA mode2.
49: * An awesome drive for the price!
50: *
51: * Fujitsu M1606TA (1Gig w/256kB buffer), DMA mode2, PIO mode4.
52: * - DMA mode2 gives horrible performance (1.6MB/sec), despite the good
53: * size of the on-drive buffer and a boasted 10ms average access time.
54: * - PIO mode4 was better, but peaked at a mere 4.5MB/sec.
55: *
56: * Micropolis MC2112A (1Gig w/508kB buffer), drive pre-dates EIDE and ATA2.
57: * - DMA works fine (2.2MB/sec), probably due to the large on-drive buffer.
58: * - This older drive can also be tweaked for fastPIO (3.7MB/sec) by using
59: * maximum clock settings (5,4) and setting all flags except prefetch.
60: *
61: * Western Digital AC31000H (1Gig w/128kB buffer), DMA mode1, PIO mode3.
62: * - DMA does not work reliably. The drive appears to be somewhat tardy
63: * in deasserting DMARQ at the end of a sector. This is evident in
64: * the observation that WRITEs work most of the time, depending on
65: * cache-buffer occupancy, but multi-sector reads seldom work.
66: *
67: * Testing was done with a Gigabyte GA-586 ATE system and the following drive:
68: * (Uwe Bonnes - [email protected])
69: *
70: * Western Digital AC31600H (1.6Gig w/128kB buffer), DMA mode2, PIO mode4.
71: * - much better than its 1Gig cousin, this drive is reported to work
72: * very well with DMA (7.3MB/sec).
73: *
74: * Other drives:
75: *
76: * Maxtor 7540AV (515Meg w/32kB buffer), DMA modes mword0/sword2, PIO mode3.
77: * - a budget drive, with budget performance, around 3MB/sec.
78: *
79: * Western Digital AC2850F (814Meg w/64kB buffer), DMA mode1, PIO mode3.
80: * - another "caviar" drive, similar to the AC31000, except that this one
81: * worked with DMA in at least one system. Throughput is about 3.8MB/sec
82: * for both DMA and PIO.
83: *
84: * Conner CFS850A (812Meg w/64kB buffer), DMA mode2, PIO mode4.
85: * - like most Conner models, this drive proves that even a fast interface
86: * cannot improve slow media. Both DMA and PIO peak around 3.5MB/sec.
87: *
88: * If you have any drive models to add, email your results to: [email protected]
89: * Keep an eye on /var/adm/messages for "DMA disabled" messages.
90: *
91: * Some people have reported trouble with Intel Zappa motherboards.
92: * This can be fixed by upgrading the AMI BIOS to version 1.00.04.BS0,
93: * available from ftp://ftp.intel.com/pub/bios/10004bs0.exe
94: * (thanks to Glen Morrell <[email protected]> for researching this).
95: *
96: * And, yes, Intel Zappa boards really *do* use the Triton IDE ports.
97: */
98: #include <linux/config.h>
99: #include <linux/types.h>
100: #include <linux/kernel.h>
101: #include <linux/timer.h>
102: #include <linux/mm.h>
103: #include <linux/ioport.h>
104: #include <linux/interrupt.h>
105: #include <linux/blkdev.h>
106: #include <linux/hdreg.h>
107: #include <linux/pci.h>
108: #include <linux/bios32.h>
109:
110: #include <asm/io.h>
111: #include <asm/dma.h>
112:
113: #include "ide.h"
114:
115: /*
116: * good_dma_drives() lists the model names (from "hdparm -i")
117: * of drives which do not support mword2 DMA but which are
118: * known to work fine with this interface under Linux.
119: */
120: const char *good_dma_drives[] = {"Micropolis 2112A",
121: "CONNER CTMA 4000"};
122:
123: /*
124: * Our Physical Region Descriptor (PRD) table should be large enough
125: * to handle the biggest I/O request we are likely to see. Since requests
126: * can have no more than 256 sectors, and since the typical blocksize is
127: * two sectors, we could get by with a limit of 128 entries here for the
128: * usual worst case. Most requests seem to include some contiguous blocks,
129: * further reducing the number of table entries required.
130: *
131: * The driver reverts to PIO mode for individual requests that exceed
132: * this limit (possible with 512 byte blocksizes, eg. MSDOS f/s), so handling
133: * 100% of all crazy scenarios here is not necessary.
134: *
135: * As it turns out though, we must allocate a full 4KB page for this,
136: * so the two PRD tables (ide0 & ide1) will each get half of that,
137: * allowing each to have about 256 entries (8 bytes each) from this.
138: */
139: #define PRD_BYTES 8
140: #define PRD_ENTRIES (PAGE_SIZE / (2 * PRD_BYTES))
141:
142: /*
143: * dma_intr() is the handler for disk read/write DMA interrupts
144: */
145: static void dma_intr (ide_drive_t *drive)
146: {
147: byte stat, dma_stat;
148: int i;
149: struct request *rq = HWGROUP(drive)->rq;
150: unsigned short dma_base = HWIF(drive)->dma_base;
151:
152: dma_stat = inb(dma_base+2); /* get DMA status */
153: outb(inb(dma_base)&~1, dma_base); /* stop DMA operation */
154: stat = GET_STAT(); /* get drive status */
155: if (OK_STAT(stat,DRIVE_READY,drive->bad_wstat|DRQ_STAT)) {
156: if ((dma_stat & 7) == 4) { /* verify good DMA status */
157: rq = HWGROUP(drive)->rq;
158: for (i = rq->nr_sectors; i > 0;) {
159: i -= rq->current_nr_sectors;
160: ide_end_request(1, HWGROUP(drive));
161: }
162: return;
163: }
164: printk("%s: bad DMA status: 0x%02x\n", drive->name, dma_stat);
165: }
166: sti();
167: ide_error(drive, "dma_intr", stat);
168: }
169:
170: /*
171: * build_dmatable() prepares a dma request.
172: * Returns 0 if all went okay, returns 1 otherwise.
173: */
174: static int build_dmatable (ide_drive_t *drive)
175: {
176: struct request *rq = HWGROUP(drive)->rq;
177: struct buffer_head *bh = rq->bh;
178: unsigned long size, addr, *table = HWIF(drive)->dmatable;
179: unsigned int count = 0;
180:
181: do {
182: /*
183: * Determine addr and size of next buffer area. We assume that
184: * individual virtual buffers are always composed linearly in
185: * physical memory. For example, we assume that any 8kB buffer
186: * is always composed of two adjacent physical 4kB pages rather
187: * than two possibly non-adjacent physical 4kB pages.
188: */
189: if (bh == NULL) { /* paging and tape requests have (rq->bh == NULL) */
190: addr = virt_to_bus (rq->buffer);
191: #ifdef CONFIG_BLK_DEV_IDETAPE
192: if (drive->media == ide_tape)
193: size = drive->tape.pc->request_transfer;
194: else
195: #endif /* CONFIG_BLK_DEV_IDETAPE */
196: size = rq->nr_sectors << 9;
197: } else {
198: /* group sequential buffers into one large buffer */
199: addr = virt_to_bus (bh->b_data);
200: size = bh->b_size;
201: while ((bh = bh->b_reqnext) != NULL) {
202: if ((addr + size) != virt_to_bus (bh->b_data))
203: break;
204: size += bh->b_size;
205: }
206: }
207:
208: /*
209: * Fill in the dma table, without crossing any 64kB boundaries.
210: * We assume 16-bit alignment of all blocks.
211: */
212: while (size) {
213: if (++count >= PRD_ENTRIES) {
214: printk("%s: DMA table too small\n", drive->name);
215: return 1; /* revert to PIO for this request */
216: } else {
217: unsigned long bcount = 0x10000 - (addr & 0xffff);
218: if (bcount > size)
219: bcount = size;
220: *table++ = addr;
221: *table++ = bcount;
222: addr += bcount;
223: size -= bcount;
224: }
225: }
226: } while (bh != NULL);
227: if (count) {
228: *--table |= 0x80000000; /* set End-Of-Table (EOT) bit */
229: return 0;
230: }
231: printk("%s: empty DMA table?\n", drive->name);
232: return 1; /* let the PIO routines handle this weirdness */
233: }
234:
235: static int config_drive_for_dma (ide_drive_t *drive)
236: {
237: const char **list;
238:
239: struct hd_driveid *id = drive->id;
240: if (id && (id->capability & 1)) {
241: /* Enable DMA on any drive that supports mword2 DMA */
242: if ((id->field_valid & 2) && (id->dma_mword & 0x404) == 0x404) {
243: drive->using_dma = 1;
244: return 0; /* DMA enabled */
245: }
246: /* Consult the list of known "good" drives */
247: list = good_dma_drives;
248: while (*list) {
249: if (!strcmp(*list++,id->model)) {
250: drive->using_dma = 1;
251: return 0; /* DMA enabled */
252: }
253: }
254: }
255: return 1; /* DMA not enabled */
256: }
257:
258: /*
259: * triton_dmaproc() initiates/aborts DMA read/write operations on a drive.
260: *
261: * The caller is assumed to have selected the drive and programmed the drive's
262: * sector address using CHS or LBA. All that remains is to prepare for DMA
263: * and then issue the actual read/write DMA/PIO command to the drive.
264: *
265: * For ATAPI devices, we just prepare for DMA and return. The caller should
266: * then issue the packet command to the drive and call us again with
267: * ide_dma_begin afterwards.
268: *
269: * Returns 0 if all went well.
270: * Returns 1 if DMA read/write could not be started, in which case
271: * the caller should revert to PIO for the current request.
272: */
273: static int triton_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
274: {
275: unsigned long dma_base = HWIF(drive)->dma_base;
276: unsigned int reading = (1 << 3);
277:
278: switch (func) {
279: case ide_dma_abort:
280: outb(inb(dma_base)&~1, dma_base); /* stop DMA */
281: return 0;
282: case ide_dma_check:
283: return config_drive_for_dma (drive);
284: case ide_dma_write:
285: reading = 0;
286: case ide_dma_read:
287: break;
288: case ide_dma_status_bad:
289: return ((inb(dma_base+2) & 7) != 4); /* verify good DMA status */
290: case ide_dma_transferred:
291: #if 0
292: return (number of bytes actually transferred);
293: #else
294: return (0);
295: #endif
296: case ide_dma_begin:
297: outb(inb(dma_base)|1, dma_base); /* begin DMA */
298: return 0;
299: default:
300: printk("triton_dmaproc: unsupported func: %d\n", func);
301: return 1;
302: }
303: if (build_dmatable (drive))
304: return 1;
305: outl(virt_to_bus (HWIF(drive)->dmatable), dma_base + 4); /* PRD table */
306: outb(reading, dma_base); /* specify r/w */
307: outb(0x26, dma_base+2); /* clear status bits */
308: #ifdef CONFIG_BLK_DEV_IDEATAPI
309: if (drive->media != ide_disk)
310: return 0;
311: #endif /* CONFIG_BLK_DEV_IDEATAPI */
312: ide_set_handler(drive, &dma_intr, WAIT_CMD); /* issue cmd to drive */
313: OUT_BYTE(reading ? WIN_READDMA : WIN_WRITEDMA, IDE_COMMAND_REG);
314: outb(inb(dma_base)|1, dma_base); /* begin DMA */
315: return 0;
316: }
317:
318: /*
319: * print_triton_drive_flags() displays the currently programmed options
320: * in the Triton chipset for a given drive.
321: *
322: * If fastDMA is "no", then slow ISA timings are used for DMA data xfers.
323: * If fastPIO is "no", then slow ISA timings are used for PIO data xfers.
324: * If IORDY is "no", then IORDY is assumed to always be asserted.
325: * If PreFetch is "no", then data pre-fetch/post are not used.
326: *
327: * When "fastPIO" and/or "fastDMA" are "yes", then faster PCI timings and
328: * back-to-back 16-bit data transfers are enabled, using the sample_CLKs
329: * and recovery_CLKs (PCI clock cycles) timing parameters for that interface.
330: */
331: static void print_triton_drive_flags (unsigned int unit, byte flags)
332: {
333: printk(" %s ", unit ? "slave :" : "master:");
334: printk( "fastDMA=%s", (flags&9) ? "on " : "off");
335: printk(" PreFetch=%s", (flags&4) ? "on " : "off");
336: printk(" IORDY=%s", (flags&2) ? "on " : "off");
337: printk(" fastPIO=%s\n", ((flags&9)==1) ? "on " : "off");
338: }
339:
340: static void init_triton_dma (ide_hwif_t *hwif, unsigned short base)
341: {
342: static unsigned long dmatable = 0;
343:
344: #if 0
345: printk(" %s: BusMaster DMA at 0x%04x-0x%04x", hwif->name, base, base+7);
346: #endif
347: if (check_region(base, 8)) {
348: #if 0
349: printk(" -- ERROR, PORTS ALREADY IN USE");
350: #endif
351: } else {
352: request_region(base, 8, "triton DMA");
353: hwif->dma_base = base;
354: if (!dmatable) {
355: /*
356: * Since we know we are on a PCI bus, we could
357: * actually use __get_free_pages() here instead
358: * of __get_dma_pages() -- no ISA limitations.
359: */
360: dmatable = __get_dma_pages(GFP_KERNEL, 0);
361: }
362: if (dmatable) {
363: hwif->dmatable = (unsigned long *) dmatable;
364: dmatable += (PRD_ENTRIES * PRD_BYTES);
365: outl(virt_to_bus(hwif->dmatable), base + 4);
366: hwif->dmaproc = &triton_dmaproc;
367: }
368: }
369: #if 0
370: printk("\n");
371: #endif
372: }
373:
374: /*
375: * calc_mode() returns the ATA PIO mode number, based on the number
376: * of cycle clks passed in. Assumes 33Mhz bus operation (30ns per clk).
377: */
378: byte calc_mode (byte clks)
379: {
380: if (clks == 3) return 5;
381: if (clks == 4) return 4;
382: if (clks < 6) return 3;
383: if (clks < 8) return 2;
384: if (clks < 13) return 1;
385: return 0;
386: }
387:
388: /*
389: * ide_init_triton() prepares the IDE driver for DMA operation.
390: * This routine is called once, from ide.c during driver initialization,
391: * for each triton chipset which is found (unlikely to be more than one).
392: */
393: void ide_init_triton (byte bus, byte fn)
394: {
395: int rc = 0, h;
396: int dma_enabled = 0;
397: unsigned short bmiba, pcicmd;
398: unsigned int timings;
399:
400: printk("ide: Triton BM-IDE on PCI bus %d function %d\n", bus, fn);
401: /*
402: * See if IDE and BM-DMA features are enabled:
403: */
404: if ((rc = pcibios_read_config_word(bus, fn, 0x04, &pcicmd)))
405: goto quit;
406: if ((pcicmd & 1) == 0) {
407: printk("ide: Triton IDE ports are not enabled\n");
408: goto quit;
409: }
410: if ((pcicmd & 4) == 0) {
411: printk("ide: Triton BM-DMA feature is not enabled -- upgrade your BIOS\n");
412: } else {
413: /*
414: * Get the bmiba base address
415: */
416: if ((rc = pcibios_read_config_word(bus, fn, 0x20, &bmiba)))
417: goto quit;
418: bmiba &= 0xfff0; /* extract port base address */
419: dma_enabled = 1;
420: }
421:
422: /*
423: * See if ide port(s) are enabled
424: */
425: if ((rc = pcibios_read_config_dword(bus, fn, 0x40, &timings)))
426: goto quit;
427: if (!(timings & 0x80008000)) {
428: printk("ide: neither Triton IDE port is enabled\n");
429: goto quit;
430: }
431:
432: /*
433: * Save the dma_base port addr for each interface
434: */
435: for (h = 0; h < MAX_HWIFS; ++h) {
436: byte s_clks, r_clks;
437: ide_hwif_t *hwif = &ide_hwifs[h];
438: unsigned short time;
439: if (hwif->io_base == 0x1f0) {
440: time = timings & 0xffff;
441: if ((timings & 0x8000) == 0) /* interface enabled? */
442: continue;
443: hwif->chipset = ide_triton;
444: if (dma_enabled)
445: init_triton_dma(hwif, bmiba);
446: } else if (hwif->io_base == 0x170) {
447: time = timings >> 16;
448: if ((timings & 0x8000) == 0) /* interface enabled? */
449: continue;
450: hwif->chipset = ide_triton;
451: if (dma_enabled)
452: init_triton_dma(hwif, bmiba + 8);
453: } else
454: continue;
455: s_clks = ((~time >> 12) & 3) + 2;
456: r_clks = ((~time >> 8) & 3) + 1;
457: #if 0
458: printk(" %s timing: (0x%04x) sample_CLKs=%d, recovery_CLKs=%d (PIO mode%d)\n",
459: hwif->name, time, s_clks, r_clks, calc_mode(s_clks+r_clks));
460: print_triton_drive_flags (0, time & 0xf);
461: print_triton_drive_flags (1, (time >> 4) & 0xf);
462: #endif
463: }
464:
465: quit: if (rc) printk("ide: pcibios access failed - %s\n", pcibios_strerror(rc));
466: }
467:
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