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Annotation of Gnu-Mach/i386/i386at/gpl/linux/net/8390.h, revision 1.1

1.1     ! root        1: /* Generic NS8390 register definitions. */
        !             2: /* This file is part of Donald Becker's 8390 drivers, and is distributed
        !             3:    under the same license.
        !             4:    Some of these names and comments originated from the Crynwr
        !             5:    packet drivers, which are distributed under the GPL. */
        !             6: 
        !             7: #ifndef _8390_h
        !             8: #define _8390_h
        !             9: 
        !            10: #include <linux/if_ether.h>
        !            11: #include <linux/ioport.h>
        !            12: #include <linux/skbuff.h>
        !            13: 
        !            14: #define TX_2X_PAGES 12
        !            15: #define TX_1X_PAGES 6
        !            16: #define TX_PAGES (ei_status.pingpong ? TX_2X_PAGES : TX_1X_PAGES)
        !            17: 
        !            18: #define ETHER_ADDR_LEN 6
        !            19: 
        !            20: /* The 8390 specific per-packet-header format. */
        !            21: struct e8390_pkt_hdr {
        !            22:   unsigned char status; /* status */
        !            23:   unsigned char next;   /* pointer to next packet. */
        !            24:   unsigned short count; /* header + packet length in bytes */
        !            25: };
        !            26: 
        !            27: /* From 8390.c */
        !            28: extern int ei_debug;
        !            29: extern struct sigaction ei_sigaction;
        !            30: 
        !            31: extern int ethif_init(struct device *dev);
        !            32: extern int ethdev_init(struct device *dev);
        !            33: extern void NS8390_init(struct device *dev, int startp);
        !            34: extern int ei_open(struct device *dev);
        !            35: extern int ei_close(struct device *dev);
        !            36: extern void ei_interrupt(int irq, struct pt_regs *regs);
        !            37: 
        !            38: #ifndef HAVE_AUTOIRQ
        !            39: /* From auto_irq.c */
        !            40: extern struct device *irq2dev_map[16];
        !            41: extern int autoirq_setup(int waittime);
        !            42: extern int autoirq_report(int waittime);
        !            43: #endif
        !            44: 
        !            45: /* Most of these entries should be in 'struct device' (or most of the
        !            46:    things in there should be here!) */
        !            47: /* You have one of these per-board */
        !            48: struct ei_device {
        !            49:   const char *name;
        !            50:   void (*reset_8390)(struct device *);
        !            51:   void (*get_8390_hdr)(struct device *, struct e8390_pkt_hdr *, int);
        !            52:   void (*block_output)(struct device *, int, const unsigned char *, int);
        !            53:   void (*block_input)(struct device *, int, struct sk_buff *, int);
        !            54:   unsigned open:1;
        !            55:   unsigned word16:1;  /* We have the 16-bit (vs 8-bit) version of the card. */
        !            56:   unsigned txing:1;            /* Transmit Active */
        !            57:   unsigned irqlock:1;          /* 8390's intrs disabled when '1'. */
        !            58:   unsigned dmaing:1;           /* Remote DMA Active */
        !            59:   unsigned pingpong:1;         /* Using the ping-pong driver */
        !            60:   unsigned char tx_start_page, rx_start_page, stop_page;
        !            61:   unsigned char current_page;  /* Read pointer in buffer  */
        !            62:   unsigned char interface_num; /* Net port (AUI, 10bT.) to use. */
        !            63:   unsigned char txqueue;       /* Tx Packet buffer queue length. */
        !            64:   short tx1, tx2;              /* Packet lengths for ping-pong tx. */
        !            65:   short lasttx;                        /* Alpha version consistency check. */
        !            66:   unsigned char reg0;          /* Register '0' in a WD8013 */
        !            67:   unsigned char reg5;          /* Register '5' in a WD8013 */
        !            68:   unsigned char saved_irq;     /* Original dev->irq value. */
        !            69:   /* The new statistics table. */
        !            70:   struct enet_statistics stat;
        !            71: };
        !            72: 
        !            73: /* The maximum number of 8390 interrupt service routines called per IRQ. */
        !            74: #define MAX_SERVICE 12
        !            75: 
        !            76: /* The maximum time waited (in jiffies) before assuming a Tx failed. (20ms) */
        !            77: #define TX_TIMEOUT (20*HZ/100)
        !            78: 
        !            79: #define ei_status (*(struct ei_device *)(dev->priv))
        !            80: 
        !            81: /* Some generic ethernet register configurations. */
        !            82: #define E8390_TX_IRQ_MASK 0xa  /* For register EN0_ISR */
        !            83: #define E8390_RX_IRQ_MASK  0x5
        !            84: #define E8390_RXCONFIG 0x4     /* EN0_RXCR: broadcasts, no multicast,errors */
        !            85: #define E8390_RXOFF 0x20       /* EN0_RXCR: Accept no packets */
        !            86: #define E8390_TXCONFIG 0x00    /* EN0_TXCR: Normal transmit mode */
        !            87: #define E8390_TXOFF 0x02       /* EN0_TXCR: Transmitter off */
        !            88: 
        !            89: /*  Register accessed at EN_CMD, the 8390 base addr.  */
        !            90: #define E8390_STOP     0x01    /* Stop and reset the chip */
        !            91: #define E8390_START    0x02    /* Start the chip, clear reset */
        !            92: #define E8390_TRANS    0x04    /* Transmit a frame */
        !            93: #define E8390_RREAD    0x08    /* Remote read */
        !            94: #define E8390_RWRITE   0x10    /* Remote write  */
        !            95: #define E8390_NODMA    0x20    /* Remote DMA */
        !            96: #define E8390_PAGE0    0x00    /* Select page chip registers */
        !            97: #define E8390_PAGE1    0x40    /* using the two high-order bits */
        !            98: #define E8390_PAGE2    0x80    /* Page 3 is invalid. */
        !            99: 
        !           100: #define E8390_CMD      0x00    /* The command register (for all pages) */
        !           101: /* Page 0 register offsets. */
        !           102: #define EN0_CLDALO     0x01    /* Low byte of current local dma addr  RD */
        !           103: #define EN0_STARTPG    0x01    /* Starting page of ring bfr WR */
        !           104: #define EN0_CLDAHI     0x02    /* High byte of current local dma addr  RD */
        !           105: #define EN0_STOPPG     0x02    /* Ending page +1 of ring bfr WR */
        !           106: #define EN0_BOUNDARY   0x03    /* Boundary page of ring bfr RD WR */
        !           107: #define EN0_TSR                0x04    /* Transmit status reg RD */
        !           108: #define EN0_TPSR       0x04    /* Transmit starting page WR */
        !           109: #define EN0_NCR                0x05    /* Number of collision reg RD */
        !           110: #define EN0_TCNTLO     0x05    /* Low  byte of tx byte count WR */
        !           111: #define EN0_FIFO       0x06    /* FIFO RD */
        !           112: #define EN0_TCNTHI     0x06    /* High byte of tx byte count WR */
        !           113: #define EN0_ISR                0x07    /* Interrupt status reg RD WR */
        !           114: #define EN0_CRDALO     0x08    /* low byte of current remote dma address RD */
        !           115: #define EN0_RSARLO     0x08    /* Remote start address reg 0 */
        !           116: #define EN0_CRDAHI     0x09    /* high byte, current remote dma address RD */
        !           117: #define EN0_RSARHI     0x09    /* Remote start address reg 1 */
        !           118: #define EN0_RCNTLO     0x0a    /* Remote byte count reg WR */
        !           119: #define EN0_RCNTHI     0x0b    /* Remote byte count reg WR */
        !           120: #define EN0_RSR                0x0c    /* rx status reg RD */
        !           121: #define EN0_RXCR       0x0c    /* RX configuration reg WR */
        !           122: #define EN0_TXCR       0x0d    /* TX configuration reg WR */
        !           123: #define EN0_COUNTER0   0x0d    /* Rcv alignment error counter RD */
        !           124: #define EN0_DCFG       0x0e    /* Data configuration reg WR */
        !           125: #define EN0_COUNTER1   0x0e    /* Rcv CRC error counter RD */
        !           126: #define EN0_IMR                0x0f    /* Interrupt mask reg WR */
        !           127: #define EN0_COUNTER2   0x0f    /* Rcv missed frame error counter RD */
        !           128: 
        !           129: /* Bits in EN0_ISR - Interrupt status register */
        !           130: #define ENISR_RX       0x01    /* Receiver, no error */
        !           131: #define ENISR_TX       0x02    /* Transmitter, no error */
        !           132: #define ENISR_RX_ERR   0x04    /* Receiver, with error */
        !           133: #define ENISR_TX_ERR   0x08    /* Transmitter, with error */
        !           134: #define ENISR_OVER     0x10    /* Receiver overwrote the ring */
        !           135: #define ENISR_COUNTERS 0x20    /* Counters need emptying */
        !           136: #define ENISR_RDC      0x40    /* remote dma complete */
        !           137: #define ENISR_RESET    0x80    /* Reset completed */
        !           138: #define ENISR_ALL      0x3f    /* Interrupts we will enable */
        !           139: 
        !           140: /* Bits in EN0_DCFG - Data config register */
        !           141: #define ENDCFG_WTS     0x01    /* word transfer mode selection */
        !           142: 
        !           143: /* Page 1 register offsets. */
        !           144: #define EN1_PHYS   0x01        /* This board's physical enet addr RD WR */
        !           145: #define EN1_CURPAG 0x07        /* Current memory page RD WR */
        !           146: #define EN1_MULT   0x08        /* Multicast filter mask array (8 bytes) RD WR */
        !           147: 
        !           148: /* Bits in received packet status byte and EN0_RSR*/
        !           149: #define ENRSR_RXOK     0x01    /* Received a good packet */
        !           150: #define ENRSR_CRC      0x02    /* CRC error */
        !           151: #define ENRSR_FAE      0x04    /* frame alignment error */
        !           152: #define ENRSR_FO       0x08    /* FIFO overrun */
        !           153: #define ENRSR_MPA      0x10    /* missed pkt */
        !           154: #define ENRSR_PHY      0x20    /* physical/multicase address */
        !           155: #define ENRSR_DIS      0x40    /* receiver disable. set in monitor mode */
        !           156: #define ENRSR_DEF      0x80    /* deferring */
        !           157: 
        !           158: /* Transmitted packet status, EN0_TSR. */
        !           159: #define ENTSR_PTX 0x01 /* Packet transmitted without error */
        !           160: #define ENTSR_ND  0x02 /* The transmit wasn't deferred. */
        !           161: #define ENTSR_COL 0x04 /* The transmit collided at least once. */
        !           162: #define ENTSR_ABT 0x08  /* The transmit collided 16 times, and was deferred. */
        !           163: #define ENTSR_CRS 0x10 /* The carrier sense was lost. */
        !           164: #define ENTSR_FU  0x20  /* A "FIFO underrun" occurred during transmit. */
        !           165: #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
        !           166: #define ENTSR_OWC 0x80  /* There was an out-of-window collision. */
        !           167: 
        !           168: #endif /* _8390_h */

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