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1.1 root 1: /* de4x5.c: A DIGITAL DE425/DE434/DE435/DE500 ethernet driver for Linux.
2:
3: Copyright 1994, 1995 Digital Equipment Corporation.
4:
5: This software may be used and distributed according to the terms of
6: the GNU Public License, incorporated herein by reference.
7:
8: This driver is written for the Digital Equipment Corporation series
9: of EtherWORKS ethernet cards:
10:
11: DE425 TP/COAX EISA
12: DE434 TP PCI
13: DE435 TP/COAX/AUI PCI
14: DE500 10/100 PCI Fasternet
15:
16: The driver has been tested on a relatively busy network using the DE425,
17: DE434, DE435 and DE500 cards and benchmarked with 'ttcp': it transferred
18: 16M of data to a DECstation 5000/200 as follows:
19:
20: TCP UDP
21: TX RX TX RX
22: DE425 1030k 997k 1170k 1128k
23: DE434 1063k 995k 1170k 1125k
24: DE435 1063k 995k 1170k 1125k
25: DE500 1063k 998k 1170k 1125k in 10Mb/s mode
26:
27: All values are typical (in kBytes/sec) from a sample of 4 for each
28: measurement. Their error is +/-20k on a quiet (private) network and also
29: depend on what load the CPU has.
30:
31: The author may be reached as [email protected] or Digital
32: Equipment Corporation, 550 King Street, Littleton MA 01460.
33:
34: =========================================================================
35: This driver has been written substantially from scratch, although its
36: inheritance of style and stack interface from 'ewrk3.c' and in turn from
37: Donald Becker's 'lance.c' should be obvious.
38:
39: Upto 15 EISA cards can be supported under this driver, limited primarily
40: by the available IRQ lines. I have checked different configurations of
41: multiple depca, EtherWORKS 3 cards and de4x5 cards and have not found a
42: problem yet (provided you have at least depca.c v0.38) ...
43:
44: PCI support has been added to allow the driver to work with the DE434
45: and DE435 cards. The I/O accesses are a bit of a kludge due to the
46: differences in the EISA and PCI CSR address offsets from the base
47: address.
48:
49: The ability to load this driver as a loadable module has been included
50: and used extensively during the driver development (to save those long
51: reboot sequences). Loadable module support under PCI has been achieved
52: by letting any I/O address less than 0x1000 be assigned as:
53:
54: 0xghh
55:
56: where g is the bus number (usually 0 until the BIOS's get fixed)
57: hh is the device number (max is 32 per bus).
58:
59: Essentially, the I/O address and IRQ information are ignored and filled
60: in later by the PCI BIOS during the PCI probe. Note that the board
61: should be in the system at boot time so that its I/O address and IRQ are
62: allocated by the PCI BIOS automatically. The special case of device 0 on
63: bus 0 is not allowed as the probe will think you're autoprobing a
64: module.
65:
66: To utilise this ability, you have to do 8 things:
67:
68: 0) have a copy of the loadable modules code installed on your system.
69: 1) copy de4x5.c from the /linux/drivers/net directory to your favourite
70: temporary directory.
71: 2) edit the source code near line 2762 to reflect the I/O address and
72: IRQ you're using, or assign these when loading by:
73:
74: insmod de4x5.o irq=x io=y
75:
76: 3) compile de4x5.c, but include -DMODULE in the command line to ensure
77: that the correct bits are compiled (see end of source code).
78: 4) if you are wanting to add a new card, goto 5. Otherwise, recompile a
79: kernel with the de4x5 configuration turned off and reboot.
80: 5) insmod de4x5.o
81: 6) run the net startup bits for your new eth?? interface manually
82: (usually /etc/rc.inet[12] at boot time).
83: 7) enjoy!
84:
85: Note that autoprobing is not allowed in loadable modules - the system is
86: already up and running and you're messing with interrupts.
87:
88: To unload a module, turn off the associated interface
89: 'ifconfig eth?? down' then 'rmmod de4x5'.
90:
91: Automedia detection is included so that in principal you can disconnect
92: from, e.g. TP, reconnect to BNC and things will still work (after a
93: pause whilst the driver figures out where its media went). My tests
94: using ping showed that it appears to work....
95:
96: A compile time switch to allow Znyx recognition has been added. This
97: "feature" is in no way supported nor tested in this driver and the user
98: may use it at his/her sole discretion. I have had 2 conflicting reports
99: that my driver will or won't work with Znyx. Try Donald Becker's
100: 'tulip.c' if this driver doesn't work for you. I will not be supporting
101: Znyx cards since I have no information on them and can't test them in a
102: system.
103:
104: TO DO:
105: ------
106:
107:
108: Revision History
109: ----------------
110:
111: Version Date Description
112:
113: 0.1 17-Nov-94 Initial writing. ALPHA code release.
114: 0.2 13-Jan-95 Added PCI support for DE435's.
115: 0.21 19-Jan-95 Added auto media detection.
116: 0.22 10-Feb-95 Fix interrupt handler call <[email protected]>.
117: Fix recognition bug reported by <[email protected]>.
118: Add request/release_region code.
119: Add loadable modules support for PCI.
120: Clean up loadable modules support.
121: 0.23 28-Feb-95 Added DC21041 and DC21140 support.
122: Fix missed frame counter value and initialisation.
123: Fixed EISA probe.
124: 0.24 11-Apr-95 Change delay routine to use <linux/udelay>.
125: Change TX_BUFFS_AVAIL macro.
126: Change media autodetection to allow manual setting.
127: Completed DE500 (DC21140) support.
128: 0.241 18-Apr-95 Interim release without DE500 Autosense Algorithm.
129: 0.242 10-May-95 Minor changes
130: 0.30 12-Jun-95 Timer fix for DC21140
131: Portability changes.
132: Add ALPHA changes from <[email protected]>.
133: Add DE500 semi automatic autosense.
134: Add Link Fail interrupt TP failure detection.
135: Add timer based link change detection.
136: Plugged a memory leak in de4x5_queue_pkt().
137: 0.31 13-Jun-95 Fixed PCI stuff for 1.3.1
138: 0.32 26-Jun-95 Added verify_area() calls in de4x5_ioctl() from
139: suggestion by <[email protected]>
140:
141: =========================================================================
142: */
143:
144: static const char *version = "de4x5.c:v0.32 6/26/95 [email protected]\n";
145:
146: #include <linux/module.h>
147:
148: #include <linux/kernel.h>
149: #include <linux/sched.h>
150: #include <linux/string.h>
151: #include <linux/interrupt.h>
152: #include <linux/ptrace.h>
153: #include <linux/errno.h>
154: #include <linux/ioport.h>
155: #include <linux/malloc.h>
156: #include <linux/bios32.h>
157: #include <linux/pci.h>
158: #include <linux/delay.h>
159: #include <asm/bitops.h>
160: #include <asm/io.h>
161: #include <asm/dma.h>
162: #include <asm/segment.h>
163:
164: #include <linux/netdevice.h>
165: #include <linux/etherdevice.h>
166: #include <linux/skbuff.h>
167:
168: #include <linux/time.h>
169: #include <linux/types.h>
170: #include <linux/unistd.h>
171:
172: #include "de4x5.h"
173:
174: #ifdef DE4X5_DEBUG
175: static int de4x5_debug = DE4X5_DEBUG;
176: #else
177: static int de4x5_debug = 1;
178: #endif
179:
180: #ifdef DE4X5_AUTOSENSE /* Should be done on a per adapter basis */
181: static int de4x5_autosense = DE4X5_AUTOSENSE;
182: #else
183: static int de4x5_autosense = AUTO; /* Do auto media/mode sensing */
184: #endif
185:
186: #ifdef DE4X5_FULL_DUPLEX /* Should be done on a per adapter basis */
187: static s32 de4x5_full_duplex = 1;
188: #else
189: static s32 de4x5_full_duplex = 0;
190: #endif
191:
192: #define DE4X5_NDA 0xffe0 /* No Device (I/O) Address */
193:
194: /*
195: ** Ethernet PROM defines
196: */
197: #define PROBE_LENGTH 32
198: #define ETH_PROM_SIG 0xAA5500FFUL
199:
200: /*
201: ** Ethernet Info
202: */
203: #define PKT_BUF_SZ 1536 /* Buffer size for each Tx/Rx buffer */
204: #define MAX_PKT_SZ 1514 /* Maximum ethernet packet length */
205: #define MAX_DAT_SZ 1500 /* Maximum ethernet data length */
206: #define MIN_DAT_SZ 1 /* Minimum ethernet data length */
207: #define PKT_HDR_LEN 14 /* Addresses and data length info */
208: #define FAKE_FRAME_LEN (MAX_PKT_SZ + 1)
209: #define QUEUE_PKT_TIMEOUT (3*HZ) /* 3 second timeout */
210:
211:
212: #define CRC_POLYNOMIAL_BE 0x04c11db7UL /* Ethernet CRC, big endian */
213: #define CRC_POLYNOMIAL_LE 0xedb88320UL /* Ethernet CRC, little endian */
214:
215: /*
216: ** EISA bus defines
217: */
218: #define DE4X5_EISA_IO_PORTS 0x0c00 /* I/O port base address, slot 0 */
219: #define DE4X5_EISA_TOTAL_SIZE 0xfff /* I/O address extent */
220:
221: #define MAX_EISA_SLOTS 16
222: #define EISA_SLOT_INC 0x1000
223:
224: #define DE4X5_SIGNATURE {"DE425",""}
225: #define DE4X5_NAME_LENGTH 8
226:
227: /*
228: ** PCI Bus defines
229: */
230: #define PCI_MAX_BUS_NUM 8
231: #define DE4X5_PCI_TOTAL_SIZE 0x80 /* I/O address extent */
232: #define DE4X5_CLASS_CODE 0x00020000 /* Network controller, Ethernet */
233:
234: /*
235: ** Memory Alignment. Each descriptor is 4 longwords long. To force a
236: ** particular alignment on the TX descriptor, adjust DESC_SKIP_LEN and
237: ** DESC_ALIGN. ALIGN aligns the start address of the private memory area
238: ** and hence the RX descriptor ring's first entry.
239: */
240: #define ALIGN4 ((u_long)4 - 1) /* 1 longword align */
241: #define ALIGN8 ((u_long)8 - 1) /* 2 longword align */
242: #define ALIGN16 ((u_long)16 - 1) /* 4 longword align */
243: #define ALIGN32 ((u_long)32 - 1) /* 8 longword align */
244: #define ALIGN64 ((u_long)64 - 1) /* 16 longword align */
245: #define ALIGN128 ((u_long)128 - 1) /* 32 longword align */
246:
247: #define ALIGN ALIGN32 /* Keep the DC21040 happy... */
248: #define CACHE_ALIGN CAL_16LONG
249: #define DESC_SKIP_LEN DSL_0 /* Must agree with DESC_ALIGN */
250: /*#define DESC_ALIGN u32 dummy[4]; / * Must agree with DESC_SKIP_LEN */
251: #define DESC_ALIGN
252:
253: #ifdef MACH
254: #define IS_NOT_DEC
255: #endif
256:
257: #ifndef IS_NOT_DEC /* See README.de4x5 for using this */
258: static int is_not_dec = 0;
259: #else
260: static int is_not_dec = 1;
261: #endif
262:
263: /*
264: ** DE4X5 IRQ ENABLE/DISABLE
265: */
266: #define ENABLE_IRQs { \
267: imr |= lp->irq_en;\
268: outl(imr, DE4X5_IMR); /* Enable the IRQs */\
269: }
270:
271: #define DISABLE_IRQs {\
272: imr = inl(DE4X5_IMR);\
273: imr &= ~lp->irq_en;\
274: outl(imr, DE4X5_IMR); /* Disable the IRQs */\
275: }
276:
277: #define UNMASK_IRQs {\
278: imr |= lp->irq_mask;\
279: outl(imr, DE4X5_IMR); /* Unmask the IRQs */\
280: }
281:
282: #define MASK_IRQs {\
283: imr = inl(DE4X5_IMR);\
284: imr &= ~lp->irq_mask;\
285: outl(imr, DE4X5_IMR); /* Mask the IRQs */\
286: }
287:
288: /*
289: ** DE4X5 START/STOP
290: */
291: #define START_DE4X5 {\
292: omr = inl(DE4X5_OMR);\
293: omr |= OMR_ST | OMR_SR;\
294: outl(omr, DE4X5_OMR); /* Enable the TX and/or RX */\
295: }
296:
297: #define STOP_DE4X5 {\
298: omr = inl(DE4X5_OMR);\
299: omr &= ~(OMR_ST|OMR_SR);\
300: outl(omr, DE4X5_OMR); /* Disable the TX and/or RX */ \
301: }
302:
303: /*
304: ** DE4X5 SIA RESET
305: */
306: #define RESET_SIA outl(0, DE4X5_SICR); /* Reset SIA connectivity regs */
307:
308: /*
309: ** DE500 AUTOSENSE TIMER INTERVAL (MILLISECS)
310: */
311: #define DE4X5_AUTOSENSE_MS 250
312:
313: /*
314: ** SROM Structure
315: */
316: struct de4x5_srom {
317: char reserved[18];
318: char version;
319: char num_adapters;
320: char ieee_addr[6];
321: char info[100];
322: short chksum;
323: };
324:
325: /*
326: ** DE4X5 Descriptors. Make sure that all the RX buffers are contiguous
327: ** and have sizes of both a power of 2 and a multiple of 4.
328: ** A size of 256 bytes for each buffer could be chosen because over 90% of
329: ** all packets in our network are <256 bytes long and 64 longword alignment
330: ** is possible. 1536 showed better 'ttcp' performance. Take your pick. 32 TX
331: ** descriptors are needed for machines with an ALPHA CPU.
332: */
333: #define NUM_RX_DESC 8 /* Number of RX descriptors */
334: #define NUM_TX_DESC 32 /* Number of TX descriptors */
335: #define BUFF_ALLOC_RETRIES 10 /* In case of memory shortage */
336: #define RX_BUFF_SZ 1536 /* Power of 2 for kmalloc and */
337: /* Multiple of 4 for DC21040 */
338: struct de4x5_desc {
339: volatile s32 status;
340: u32 des1;
341: u32 buf;
342: u32 next;
343: DESC_ALIGN
344: };
345:
346: /*
347: ** The DE4X5 private structure
348: */
349: #define DE4X5_PKT_STAT_SZ 16
350: #define DE4X5_PKT_BIN_SZ 128 /* Should be >=100 unless you
351: increase DE4X5_PKT_STAT_SZ */
352:
353: struct de4x5_private {
354: char adapter_name[80]; /* Adapter name */
355: struct de4x5_desc rx_ring[NUM_RX_DESC]; /* RX descriptor ring */
356: struct de4x5_desc tx_ring[NUM_TX_DESC]; /* TX descriptor ring */
357: struct sk_buff *skb[NUM_TX_DESC]; /* TX skb for freeing when sent */
358: int rx_new, rx_old; /* RX descriptor ring pointers */
359: int tx_new, tx_old; /* TX descriptor ring pointers */
360: char setup_frame[SETUP_FRAME_LEN]; /* Holds MCA and PA info. */
361: struct enet_statistics stats; /* Public stats */
362: struct {
363: u_int bins[DE4X5_PKT_STAT_SZ]; /* Private stats counters */
364: u_int unicast;
365: u_int multicast;
366: u_int broadcast;
367: u_int excessive_collisions;
368: u_int tx_underruns;
369: u_int excessive_underruns;
370: } pktStats;
371: char rxRingSize;
372: char txRingSize;
373: int bus; /* EISA or PCI */
374: int bus_num; /* PCI Bus number */
375: int chipset; /* DC21040, DC21041 or DC21140 */
376: s32 irq_mask; /* Interrupt Mask (Enable) bits */
377: s32 irq_en; /* Summary interrupt bits */
378: int media; /* Media (eg TP), mode (eg 100B)*/
379: int linkProb; /* Possible Link Problem */
380: int autosense; /* Allow/disallow autosensing */
381: int tx_enable; /* Enable descriptor polling */
382: int lostMedia; /* Possibly lost media */
383: int setup_f; /* Setup frame filtering type */
384: };
385:
386:
387: /*
388: ** The transmit ring full condition is described by the tx_old and tx_new
389: ** pointers by:
390: ** tx_old = tx_new Empty ring
391: ** tx_old = tx_new+1 Full ring
392: ** tx_old+txRingSize = tx_new+1 Full ring (wrapped condition)
393: */
394: #define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\
395: lp->tx_old+lp->txRingSize-lp->tx_new-1:\
396: lp->tx_old -lp->tx_new-1)
397:
398: /*
399: ** Public Functions
400: */
401: static int de4x5_open(struct device *dev);
402: static int de4x5_queue_pkt(struct sk_buff *skb, struct device *dev);
403: static void de4x5_interrupt(int irq, struct pt_regs *regs);
404: static int de4x5_close(struct device *dev);
405: static struct enet_statistics *de4x5_get_stats(struct device *dev);
406: static void set_multicast_list(struct device *dev);
407: static int de4x5_ioctl(struct device *dev, struct ifreq *rq, int cmd);
408:
409: /*
410: ** Private functions
411: */
412: static int de4x5_hw_init(struct device *dev, u_long iobase);
413: static int de4x5_init(struct device *dev);
414: static int de4x5_rx(struct device *dev);
415: static int de4x5_tx(struct device *dev);
416: static int de4x5_ast(struct device *dev);
417:
418: static int autoconf_media(struct device *dev);
419: static void create_packet(struct device *dev, char *frame, int len);
420: static void dce_us_delay(u32 usec);
421: static void dce_ms_delay(u32 msec);
422: static void load_packet(struct device *dev, char *buf, u32 flags, struct sk_buff *skb);
423: static void dc21040_autoconf(struct device *dev);
424: static void dc21041_autoconf(struct device *dev);
425: static void dc21140_autoconf(struct device *dev);
426: static int test_media(struct device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec);
427: /*static int test_sym_link(struct device *dev, u32 msec);*/
428: static int ping_media(struct device *dev);
429: static void reset_init_sia(struct device *dev, s32 sicr, s32 strr, s32 sigr);
430: static int test_ans(struct device *dev, s32 irqs, s32 irq_mask, s32 msec);
431: static void load_ms_timer(struct device *dev, u32 msec);
432: static int EISA_signature(char *name, s32 eisa_id);
433: static int DevicePresent(u_long iobase);
434: static short srom_rd(u_long address, u_char offset);
435: static void srom_latch(u_int command, u_long address);
436: static void srom_command(u_int command, u_long address);
437: static void srom_address(u_int command, u_long address, u_char offset);
438: static short srom_data(u_int command, u_long address);
439: /*static void srom_busy(u_int command, u_long address);*/
440: static void sendto_srom(u_int command, u_long addr);
441: static int getfrom_srom(u_long addr);
442: static void SetMulticastFilter(struct device *dev);
443: static int get_hw_addr(struct device *dev);
444:
445: static void eisa_probe(struct device *dev, u_long iobase);
446: static void pci_probe(struct device *dev, u_long iobase);
447: static struct device *alloc_device(struct device *dev, u_long iobase);
448: static char *build_setup_frame(struct device *dev, int mode);
449: static void disable_ast(struct device *dev);
450: static void enable_ast(struct device *dev, u32 time_out);
451: static void kick_tx(struct device *dev);
452:
453: #ifdef MODULE
454: int init_module(void);
455: void cleanup_module(void);
456: static int autoprobed = 1, loading_module = 1;
457: # else
458: static unsigned char de4x5_irq[] = {5,9,10,11};
459: static int autoprobed = 0, loading_module = 0;
460: #endif /* MODULE */
461:
462: static char name[DE4X5_NAME_LENGTH + 1];
463: static int num_de4x5s = 0, num_eth = 0;
464:
465: /*
466: ** Kludge to get around the fact that the CSR addresses have different
467: ** offsets in the PCI and EISA boards. Also note that the ethernet address
468: ** PROM is accessed differently.
469: */
470: static struct bus_type {
471: int bus;
472: int bus_num;
473: int device;
474: int chipset;
475: struct de4x5_srom srom;
476: int autosense;
477: } bus;
478:
479: /*
480: ** Miscellaneous defines...
481: */
482: #define RESET_DE4X5 {\
483: int i;\
484: i=inl(DE4X5_BMR);\
485: dce_ms_delay(1);\
486: outl(i | BMR_SWR, DE4X5_BMR);\
487: dce_ms_delay(1);\
488: outl(i, DE4X5_BMR);\
489: dce_ms_delay(1);\
490: for (i=0;i<5;i++) {inl(DE4X5_BMR); dce_ms_delay(1);}\
491: dce_ms_delay(1);\
492: }
493:
494:
495:
496: int de4x5_probe(struct device *dev)
497: {
498: int tmp = num_de4x5s, status = -ENODEV;
499: u_long iobase = dev->base_addr;
500:
501: if ((iobase == 0) && loading_module){
502: printk("Autoprobing is not supported when loading a module based driver.\n");
503: status = -EIO;
504: } else {
505: eisa_probe(dev, iobase);
506: pci_probe(dev, iobase);
507:
508: if ((tmp == num_de4x5s) && (iobase != 0) && loading_module) {
509: printk("%s: de4x5_probe() cannot find device at 0x%04lx.\n", dev->name,
510: iobase);
511: }
512:
513: /*
514: ** Walk the device list to check that at least one device
515: ** initialised OK
516: */
517: for (; (dev->priv == NULL) && (dev->next != NULL); dev = dev->next);
518:
519: if (dev->priv) status = 0;
520: if (iobase == 0) autoprobed = 1;
521: }
522:
523: return status;
524: }
525:
526: static int
527: de4x5_hw_init(struct device *dev, u_long iobase)
528: {
529: struct bus_type *lp = &bus;
530: int tmpbus, tmpchs, i, j, status=0;
531: char *tmp;
532:
533: /* Ensure we're not sleeping */
534: if (lp->chipset == DC21041) {
535: outl(0, PCI_CFDA);
536: dce_ms_delay(10);
537: }
538:
539: RESET_DE4X5;
540:
541: if ((inl(DE4X5_STS) & (STS_TS | STS_RS)) == 0) {
542: /*
543: ** Now find out what kind of DC21040/DC21041/DC21140 board we have.
544: */
545: if (lp->bus == PCI) {
546: if (!is_not_dec) {
547: if ((lp->chipset == DC21040) || (lp->chipset == DC21041)) {
548: strcpy(name, "DE435");
549: } else if (lp->chipset == DC21140) {
550: strcpy(name, "DE500"); /* Must read the SROM here! */
551: }
552: } else {
553: strcpy(name, "UNKNOWN");
554: }
555: } else {
556: EISA_signature(name, EISA_ID0);
557: }
558:
559: if (*name != '\0') { /* found a board signature */
560: dev->base_addr = iobase;
561: if (lp->bus == EISA) {
562: printk("%s: %s at %04lx (EISA slot %ld)",
563: dev->name, name, iobase, ((iobase>>12)&0x0f));
564: } else { /* PCI port address */
565: printk("%s: %s at %04lx (PCI bus %d, device %d)", dev->name, name,
566: iobase, lp->bus_num, lp->device);
567: }
568:
569: printk(", h/w address ");
570: status = get_hw_addr(dev);
571: for (i = 0; i < ETH_ALEN - 1; i++) { /* get the ethernet addr. */
572: printk("%2.2x:", dev->dev_addr[i]);
573: }
574: printk("%2.2x,\n", dev->dev_addr[i]);
575:
576: tmpbus = lp->bus;
577: tmpchs = lp->chipset;
578:
579: if (status == 0) {
580: struct de4x5_private *lp;
581:
582: /*
583: ** Reserve a section of kernel memory for the adapter
584: ** private area and the TX/RX descriptor rings.
585: */
586: dev->priv = (void *) kmalloc(sizeof(struct de4x5_private) + ALIGN,
587: GFP_KERNEL);
588: if (dev->priv == NULL)
589: return -ENOMEM;
590: /*
591: ** Align to a longword boundary
592: */
593: dev->priv = (void *)(((u_long)dev->priv + ALIGN) & ~ALIGN);
594: lp = (struct de4x5_private *)dev->priv;
595: memset(dev->priv, 0, sizeof(struct de4x5_private));
596: lp->bus = tmpbus;
597: lp->chipset = tmpchs;
598:
599: /*
600: ** Choose autosensing
601: */
602: if (de4x5_autosense & AUTO) {
603: lp->autosense = AUTO;
604: } else {
605: if (lp->chipset != DC21140) {
606: if ((lp->chipset == DC21040) && (de4x5_autosense & TP_NW)) {
607: de4x5_autosense = TP;
608: }
609: if ((lp->chipset == DC21041) && (de4x5_autosense & BNC_AUI)) {
610: de4x5_autosense = BNC;
611: }
612: lp->autosense = de4x5_autosense & 0x001f;
613: } else {
614: lp->autosense = de4x5_autosense & 0x00c0;
615: }
616: }
617:
618: sprintf(lp->adapter_name,"%s (%s)", name, dev->name);
619: request_region(iobase, (lp->bus == PCI ? DE4X5_PCI_TOTAL_SIZE :
620: DE4X5_EISA_TOTAL_SIZE),
621: lp->adapter_name);
622:
623: /*
624: ** Allocate contiguous receive buffers, long word aligned.
625: ** This could be a possible memory leak if the private area
626: ** is ever hosed.
627: */
628: for (tmp=NULL, j=0; (j<BUFF_ALLOC_RETRIES) && (tmp==NULL); j++) {
629: if ((tmp = (void *)kmalloc(RX_BUFF_SZ * NUM_RX_DESC + ALIGN,
630: GFP_KERNEL)) != NULL) {
631: tmp = (char *)(((u_long) tmp + ALIGN) & ~ALIGN);
632: for (i=0; i<NUM_RX_DESC; i++) {
633: lp->rx_ring[i].status = 0;
634: lp->rx_ring[i].des1 = RX_BUFF_SZ;
635: lp->rx_ring[i].buf = virt_to_bus(tmp + i * RX_BUFF_SZ);
636: lp->rx_ring[i].next = (u32)NULL;
637: }
638: barrier();
639: }
640: }
641:
642: if (tmp != NULL) {
643: lp->rxRingSize = NUM_RX_DESC;
644: lp->txRingSize = NUM_TX_DESC;
645:
646: /* Write the end of list marker to the descriptor lists */
647: lp->rx_ring[lp->rxRingSize - 1].des1 |= RD_RER;
648: lp->tx_ring[lp->txRingSize - 1].des1 |= TD_TER;
649:
650: /* Tell the adapter where the TX/RX rings are located. */
651: outl(virt_to_bus(lp->rx_ring), DE4X5_RRBA);
652: outl(virt_to_bus(lp->tx_ring), DE4X5_TRBA);
653:
654: /* Initialise the IRQ mask and Enable/Disable */
655: lp->irq_mask = IMR_RIM | IMR_TIM | IMR_TUM ;
656: lp->irq_en = IMR_NIM | IMR_AIM;
657:
658: lp->tx_enable = TRUE;
659:
660: if (dev->irq < 2) {
661: #ifndef MODULE
662: unsigned char irqnum;
663: s32 omr;
664: autoirq_setup(0);
665:
666: omr = inl(DE4X5_OMR);
667: outl(IMR_AIM|IMR_RUM, DE4X5_IMR); /* Unmask RUM interrupt */
668: outl(OMR_SR | omr, DE4X5_OMR); /* Start RX w/no descriptors */
669:
670: irqnum = autoirq_report(1);
671: if (!irqnum) {
672: printk(" and failed to detect IRQ line.\n");
673: status = -ENXIO;
674: } else {
675: for (dev->irq=0,i=0; (i<sizeof(de4x5_irq)) && (!dev->irq); i++) {
676: if (irqnum == de4x5_irq[i]) {
677: dev->irq = irqnum;
678: printk(" and uses IRQ%d.\n", dev->irq);
679: }
680: }
681:
682: if (!dev->irq) {
683: printk(" but incorrect IRQ line detected.\n");
684: status = -ENXIO;
685: }
686: }
687:
688: outl(0, DE4X5_IMR); /* Re-mask RUM interrupt */
689:
690: #endif /* MODULE */
691: } else {
692: printk(" and requires IRQ%d (not probed).\n", dev->irq);
693: }
694: } else {
695: printk("%s: Kernel could not allocate RX buffer memory.\n",
696: dev->name);
697: status = -ENXIO;
698: }
699: if (status) release_region(iobase, (lp->bus == PCI ?
700: DE4X5_PCI_TOTAL_SIZE :
701: DE4X5_EISA_TOTAL_SIZE));
702: } else {
703: printk(" which has an Ethernet PROM CRC error.\n");
704: status = -ENXIO;
705: }
706: } else {
707: status = -ENXIO;
708: }
709: } else {
710: status = -ENXIO;
711: }
712:
713: if (!status) {
714: if (de4x5_debug > 0) {
715: printk(version);
716: }
717:
718: /* The DE4X5-specific entries in the device structure. */
719: dev->open = &de4x5_open;
720: dev->hard_start_xmit = &de4x5_queue_pkt;
721: dev->stop = &de4x5_close;
722: dev->get_stats = &de4x5_get_stats;
723: dev->set_multicast_list = &set_multicast_list;
724: dev->do_ioctl = &de4x5_ioctl;
725:
726: dev->mem_start = 0;
727:
728: /* Fill in the generic field of the device structure. */
729: ether_setup(dev);
730:
731: /* Let the adapter sleep to save power */
732: if (lp->chipset == DC21041) {
733: outl(0, DE4X5_SICR);
734: outl(CFDA_PSM, PCI_CFDA);
735: }
736: } else { /* Incorrectly initialised hardware */
737: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
738: if (lp) {
739: kfree_s(bus_to_virt(lp->rx_ring[0].buf),
740: RX_BUFF_SZ * NUM_RX_DESC + ALIGN);
741: }
742: if (dev->priv) {
743: kfree_s(dev->priv, sizeof(struct de4x5_private) + ALIGN);
744: dev->priv = NULL;
745: }
746: }
747:
748: return status;
749: }
750:
751:
752: static int
753: de4x5_open(struct device *dev)
754: {
755: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
756: u_long iobase = dev->base_addr;
757: int i, status = 0;
758: s32 imr, omr, sts;
759:
760: /*
761: ** Wake up the adapter
762: */
763: if (lp->chipset == DC21041) {
764: outl(0, PCI_CFDA);
765: dce_ms_delay(10);
766: }
767:
768: if (request_irq(dev->irq, (void *)de4x5_interrupt, 0, lp->adapter_name)) {
769: printk("de4x5_open(): Requested IRQ%d is busy\n",dev->irq);
770: status = -EAGAIN;
771: } else {
772:
773: irq2dev_map[dev->irq] = dev;
774: /*
775: ** Re-initialize the DE4X5...
776: */
777: status = de4x5_init(dev);
778:
779: if (de4x5_debug > 1){
780: printk("%s: de4x5 open with irq %d\n",dev->name,dev->irq);
781: printk("\tphysical address: ");
782: for (i=0;i<6;i++){
783: printk("%2.2x:",(short)dev->dev_addr[i]);
784: }
785: printk("\n");
786: printk("Descriptor head addresses:\n");
787: printk("\t0x%8.8lx 0x%8.8lx\n",(u_long)lp->rx_ring,(u_long)lp->tx_ring);
788: printk("Descriptor addresses:\nRX: ");
789: for (i=0;i<lp->rxRingSize-1;i++){
790: if (i < 3) {
791: printk("0x%8.8lx ",(u_long)&lp->rx_ring[i].status);
792: }
793: }
794: printk("...0x%8.8lx\n",(u_long)&lp->rx_ring[i].status);
795: printk("TX: ");
796: for (i=0;i<lp->txRingSize-1;i++){
797: if (i < 3) {
798: printk("0x%8.8lx ", (u_long)&lp->tx_ring[i].status);
799: }
800: }
801: printk("...0x%8.8lx\n", (u_long)&lp->tx_ring[i].status);
802: printk("Descriptor buffers:\nRX: ");
803: for (i=0;i<lp->rxRingSize-1;i++){
804: if (i < 3) {
805: printk("0x%8.8x ",lp->rx_ring[i].buf);
806: }
807: }
808: printk("...0x%8.8x\n",lp->rx_ring[i].buf);
809: printk("TX: ");
810: for (i=0;i<lp->txRingSize-1;i++){
811: if (i < 3) {
812: printk("0x%8.8x ", lp->tx_ring[i].buf);
813: }
814: }
815: printk("...0x%8.8x\n", lp->tx_ring[i].buf);
816: printk("Ring size: \nRX: %d\nTX: %d\n",
817: (short)lp->rxRingSize,
818: (short)lp->txRingSize);
819: printk("\tstatus: %d\n", status);
820: }
821:
822: if (!status) {
823: dev->tbusy = 0;
824: dev->start = 1;
825: dev->interrupt = UNMASK_INTERRUPTS;
826: dev->trans_start = jiffies;
827:
828: START_DE4X5;
829:
830: /* Unmask and enable DE4X5 board interrupts */
831: imr = 0;
832: UNMASK_IRQs;
833:
834: /* Reset any pending (stale) interrupts */
835: sts = inl(DE4X5_STS);
836: outl(sts, DE4X5_STS);
837:
838: ENABLE_IRQs;
839: }
840: if (de4x5_debug > 1) {
841: printk("\tsts: 0x%08x\n", inl(DE4X5_STS));
842: printk("\tbmr: 0x%08x\n", inl(DE4X5_BMR));
843: printk("\timr: 0x%08x\n", inl(DE4X5_IMR));
844: printk("\tomr: 0x%08x\n", inl(DE4X5_OMR));
845: printk("\tsisr: 0x%08x\n", inl(DE4X5_SISR));
846: printk("\tsicr: 0x%08x\n", inl(DE4X5_SICR));
847: printk("\tstrr: 0x%08x\n", inl(DE4X5_STRR));
848: printk("\tsigr: 0x%08x\n", inl(DE4X5_SIGR));
849: }
850: }
851:
852: MOD_INC_USE_COUNT;
853:
854: return status;
855: }
856:
857: /*
858: ** Initialize the DE4X5 operating conditions. NB: a chip problem with the
859: ** DC21140 requires using perfect filtering mode for that chip. Since I can't
860: ** see why I'd want > 14 multicast addresses, I may change all chips to use
861: ** the perfect filtering mode. Keep the DMA burst length at 8: there seems
862: ** to be data corruption problems if it is larger (UDP errors seen from a
863: ** ttcp source).
864: */
865: static int
866: de4x5_init(struct device *dev)
867: {
868: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
869: u_long iobase = dev->base_addr;
870: int i, j, status = 0;
871: s32 bmr, omr;
872:
873: /* Lock out other processes whilst setting up the hardware */
874: set_bit(0, (void *)&dev->tbusy);
875:
876: RESET_DE4X5;
877:
878: bmr = inl(DE4X5_BMR);
879: bmr |= PBL_8 | DESC_SKIP_LEN | CACHE_ALIGN;
880: outl(bmr, DE4X5_BMR);
881:
882: if (lp->chipset != DC21140) {
883: omr = TR_96;
884: lp->setup_f = HASH_PERF;
885: } else {
886: omr = OMR_SDP | OMR_SF;
887: lp->setup_f = PERFECT;
888: }
889: outl(virt_to_bus(lp->rx_ring), DE4X5_RRBA);
890: outl(virt_to_bus(lp->tx_ring), DE4X5_TRBA);
891:
892: lp->rx_new = lp->rx_old = 0;
893: lp->tx_new = lp->tx_old = 0;
894:
895: for (i = 0; i < lp->rxRingSize; i++) {
896: lp->rx_ring[i].status = R_OWN;
897: }
898:
899: for (i = 0; i < lp->txRingSize; i++) {
900: lp->tx_ring[i].status = 0;
901: }
902:
903: barrier();
904:
905: /* Build the setup frame depending on filtering mode */
906: SetMulticastFilter(dev);
907:
908: if (lp->chipset != DC21140) {
909: load_packet(dev, lp->setup_frame, HASH_F|TD_SET|SETUP_FRAME_LEN, NULL);
910: } else {
911: load_packet(dev, lp->setup_frame, PERFECT_F|TD_SET|SETUP_FRAME_LEN, NULL);
912: }
913: outl(omr|OMR_ST, DE4X5_OMR);
914:
915: /* Poll for completion of setup frame (interrupts are disabled for now) */
916: for (j=0, i=jiffies;(i<=jiffies+HZ/100) && (j==0);) {
917: if (lp->tx_ring[lp->tx_new].status >= 0) j=1;
918: }
919: outl(omr, DE4X5_OMR); /* Stop everything! */
920:
921: if (j == 0) {
922: printk("%s: Setup frame timed out, status %08x\n", dev->name,
923: inl(DE4X5_STS));
924: status = -EIO;
925: }
926:
927: lp->tx_new = (++lp->tx_new) % lp->txRingSize;
928: lp->tx_old = lp->tx_new;
929:
930: /* Autoconfigure the connected port */
931: if (autoconf_media(dev) == 0) {
932: status = -EIO;
933: }
934:
935: return 0;
936: }
937:
938: /*
939: ** Writes a socket buffer address to the next available transmit descriptor
940: */
941: static int
942: de4x5_queue_pkt(struct sk_buff *skb, struct device *dev)
943: {
944: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
945: u_long iobase = dev->base_addr;
946: int i, status = 0;
947: s32 imr, omr, sts;
948:
949: /*
950: ** Clean out the TX ring asynchronously to interrupts - sometimes the
951: ** interrupts are lost by delayed descriptor status updates relative to
952: ** the irq assertion, especially with a busy PCI bus.
953: */
954: if (set_bit(0, (void*)&dev->tbusy) == 0) {
955: cli();
956: de4x5_tx(dev);
957: dev->tbusy = 0;
958: sti();
959: }
960:
961: /*
962: ** Transmitter timeout, possibly serious problems.
963: ** The 'lostMedia' threshold accounts for transient errors that
964: ** were noticed when switching media.
965: */
966: if (dev->tbusy || (lp->lostMedia > LOST_MEDIA_THRESHOLD)) {
967: u_long tickssofar = jiffies - dev->trans_start;
968: if ((tickssofar < QUEUE_PKT_TIMEOUT) &&
969: (lp->lostMedia <= LOST_MEDIA_THRESHOLD)) {
970: status = -1;
971: } else {
972: if (de4x5_debug >= 1) {
973: printk("%s: transmit timed out, status %08x, tbusy:%ld, lostMedia:%d tickssofar:%ld, resetting.\n",dev->name, inl(DE4X5_STS), dev->tbusy, lp->lostMedia, tickssofar);
974: }
975:
976: /* Stop and reset the TX and RX... */
977: STOP_DE4X5;
978:
979: /* Re-queue any skb's. */
980: for (i=lp->tx_old; i!=lp->tx_new; i=(++i)%lp->txRingSize) {
981: if (lp->skb[i] != NULL) {
982: if (lp->skb[i]->len != FAKE_FRAME_LEN) {
983: if (lp->tx_ring[i].status == T_OWN) {
984: dev_queue_xmit(lp->skb[i], dev, SOPRI_NORMAL);
985: } else { /* already sent */
986: dev_kfree_skb(lp->skb[i], FREE_WRITE);
987: }
988: } else {
989: dev_kfree_skb(lp->skb[i], FREE_WRITE);
990: }
991: lp->skb[i] = NULL;
992: }
993: }
994: if (skb->len != FAKE_FRAME_LEN) {
995: dev_queue_xmit(skb, dev, SOPRI_NORMAL);
996: } else {
997: dev_kfree_skb(skb, FREE_WRITE);
998: }
999:
1000: /* Initialise the hardware */
1001: status = de4x5_init(dev);
1002:
1003: /* Unmask DE4X5 board interrupts */
1004: if (!status) {
1005: /* Start here to clean stale interrupts later */
1006: dev->interrupt = UNMASK_INTERRUPTS;
1007: dev->start = 1;
1008: dev->tbusy = 0;
1009: dev->trans_start = jiffies;
1010:
1011: START_DE4X5;
1012:
1013: /* Unmask DE4X5 board interrupts */
1014: imr = 0;
1015: UNMASK_IRQs;
1016:
1017: /* Clear any pending (stale) interrupts */
1018: sts = inl(DE4X5_STS);
1019: outl(sts, DE4X5_STS);
1020:
1021: ENABLE_IRQs;
1022: } else {
1023: printk("%s: hardware initialisation failure, status %08x.\n",
1024: dev->name, inl(DE4X5_STS));
1025: }
1026: }
1027: } else if (skb == NULL) {
1028: dev_tint(dev);
1029: } else if (skb->len == FAKE_FRAME_LEN) { /* Don't TX a fake frame! */
1030: dev_kfree_skb(skb, FREE_WRITE);
1031: } else if (skb->len > 0) {
1032: /* Enforce 1 process per h/w access */
1033: if (set_bit(0, (void*)&dev->tbusy) != 0) {
1034: printk("%s: Transmitter access conflict.\n", dev->name);
1035: status = -1; /* Re-queue packet */
1036: } else {
1037: cli();
1038: if (TX_BUFFS_AVAIL) { /* Fill in a Tx ring entry */
1039: load_packet(dev, skb->data, TD_IC | TD_LS | TD_FS | skb->len, skb);
1040: if (lp->tx_enable) {
1041: outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
1042: }
1043:
1044: lp->tx_new = (++lp->tx_new) % lp->txRingSize; /* Ensure a wrap */
1045: dev->trans_start = jiffies;
1046:
1047: if (TX_BUFFS_AVAIL) {
1048: dev->tbusy = 0; /* Another pkt may be queued */
1049: }
1050: } else { /* Ring full - re-queue */
1051: status = -1;
1052: }
1053: sti();
1054: }
1055: }
1056:
1057: return status;
1058: }
1059:
1060: /*
1061: ** The DE4X5 interrupt handler.
1062: **
1063: ** I/O Read/Writes through intermediate PCI bridges are never 'posted',
1064: ** so that the asserted interrupt always has some real data to work with -
1065: ** if these I/O accesses are ever changed to memory accesses, ensure the
1066: ** STS write is read immediately to complete the transaction if the adapter
1067: ** is not on bus 0. Lost interrupts can still occur when the PCI bus load
1068: ** is high and descriptor status bits cannot be set before the associated
1069: ** interrupt is asserted and this routine entered.
1070: */
1071: static void
1072: de4x5_interrupt(int irq, struct pt_regs *regs)
1073: {
1074: struct device *dev = (struct device *)(irq2dev_map[irq]);
1075: struct de4x5_private *lp;
1076: s32 imr, omr, sts;
1077: u_long iobase;
1078:
1079: if (dev == NULL) {
1080: printk ("de4x5_interrupt(): irq %d for unknown device.\n", irq);
1081: } else {
1082: lp = (struct de4x5_private *)dev->priv;
1083: iobase = dev->base_addr;
1084:
1085: if (dev->interrupt)
1086: printk("%s: Re-entering the interrupt handler.\n", dev->name);
1087:
1088: DISABLE_IRQs; /* Ensure non re-entrancy */
1089: dev->interrupt = MASK_INTERRUPTS;
1090:
1091: while ((sts = inl(DE4X5_STS)) & lp->irq_mask) { /* Read IRQ status */
1092: outl(sts, DE4X5_STS); /* Reset the board interrupts */
1093:
1094: if (sts & (STS_RI | STS_RU)) /* Rx interrupt (packet[s] arrived) */
1095: de4x5_rx(dev);
1096:
1097: if (sts & (STS_TI | STS_TU)) /* Tx interrupt (packet sent) */
1098: de4x5_tx(dev);
1099:
1100: if (sts & STS_TM) /* Autosense tick */
1101: de4x5_ast(dev);
1102:
1103: if (sts & STS_LNF) { /* TP Link has failed */
1104: lp->lostMedia = LOST_MEDIA_THRESHOLD + 1;
1105: lp->irq_mask &= ~IMR_LFM;
1106: kick_tx(dev);
1107: }
1108:
1109: if (sts & STS_SE) { /* Bus Error */
1110: STOP_DE4X5;
1111: printk("%s: Fatal bus error occured, sts=%#8x, device stopped.\n",
1112: dev->name, sts);
1113: }
1114: }
1115:
1116: if (TX_BUFFS_AVAIL && dev->tbusy) {/* Any resources available? */
1117: dev->tbusy = 0; /* Clear TX busy flag */
1118: mark_bh(NET_BH);
1119: }
1120:
1121: dev->interrupt = UNMASK_INTERRUPTS;
1122: ENABLE_IRQs;
1123: }
1124:
1125: return;
1126: }
1127:
1128: static int
1129: de4x5_rx(struct device *dev)
1130: {
1131: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1132: int i, entry;
1133: s32 status;
1134: char *buf;
1135:
1136: for (entry = lp->rx_new; lp->rx_ring[entry].status >= 0;entry = lp->rx_new) {
1137: status = lp->rx_ring[entry].status;
1138:
1139: if (status & RD_FS) { /* Remember the start of frame */
1140: lp->rx_old = entry;
1141: }
1142:
1143: if (status & RD_LS) { /* Valid frame status */
1144: if (status & RD_ES) { /* There was an error. */
1145: lp->stats.rx_errors++; /* Update the error stats. */
1146: if (status & (RD_RF | RD_TL)) lp->stats.rx_frame_errors++;
1147: if (status & RD_CE) lp->stats.rx_crc_errors++;
1148: if (status & RD_OF) lp->stats.rx_fifo_errors++;
1149: } else { /* A valid frame received */
1150: struct sk_buff *skb;
1151: short pkt_len = (short)(lp->rx_ring[entry].status >> 16) - 4;
1152:
1153: if ((skb = dev_alloc_skb(pkt_len+2)) != NULL) {
1154: skb->dev = dev;
1155:
1156: skb_reserve(skb,2); /* Align */
1157: if (entry < lp->rx_old) { /* Wrapped buffer */
1158: short len = (lp->rxRingSize - lp->rx_old) * RX_BUFF_SZ;
1159: memcpy(skb_put(skb,len), bus_to_virt(lp->rx_ring[lp->rx_old].buf), len);
1160: memcpy(skb_put(skb,pkt_len-len), bus_to_virt(lp->rx_ring[0].buf), pkt_len - len);
1161: } else { /* Linear buffer */
1162: memcpy(skb_put(skb,pkt_len), bus_to_virt(lp->rx_ring[lp->rx_old].buf), pkt_len);
1163: }
1164:
1165: /* Push up the protocol stack */
1166: skb->protocol=eth_type_trans(skb,dev);
1167: netif_rx(skb);
1168:
1169: /* Update stats */
1170: lp->stats.rx_packets++;
1171: for (i=1; i<DE4X5_PKT_STAT_SZ-1; i++) {
1172: if (pkt_len < (i*DE4X5_PKT_BIN_SZ)) {
1173: lp->pktStats.bins[i]++;
1174: i = DE4X5_PKT_STAT_SZ;
1175: }
1176: }
1177: buf = skb->data; /* Look at the dest addr */
1178: if (buf[0] & 0x01) { /* Multicast/Broadcast */
1179: if ((*(s32 *)&buf[0] == -1) && (*(s16 *)&buf[4] == -1)) {
1180: lp->pktStats.broadcast++;
1181: } else {
1182: lp->pktStats.multicast++;
1183: }
1184: } else if ((*(s32 *)&buf[0] == *(s32 *)&dev->dev_addr[0]) &&
1185: (*(s16 *)&buf[4] == *(s16 *)&dev->dev_addr[4])) {
1186: lp->pktStats.unicast++;
1187: }
1188:
1189: lp->pktStats.bins[0]++; /* Duplicates stats.rx_packets */
1190: if (lp->pktStats.bins[0] == 0) { /* Reset counters */
1191: memset((char *)&lp->pktStats, 0, sizeof(lp->pktStats));
1192: }
1193: } else {
1194: printk("%s: Insufficient memory; nuking packet.\n", dev->name);
1195: lp->stats.rx_dropped++; /* Really, deferred. */
1196: break;
1197: }
1198: }
1199:
1200: /* Change buffer ownership for this last frame, back to the adapter */
1201: for (; lp->rx_old!=entry; lp->rx_old=(++lp->rx_old)%lp->rxRingSize) {
1202: lp->rx_ring[lp->rx_old].status = R_OWN;
1203: barrier();
1204: }
1205: lp->rx_ring[entry].status = R_OWN;
1206: barrier();
1207: }
1208:
1209: /*
1210: ** Update entry information
1211: */
1212: lp->rx_new = (++lp->rx_new) % lp->rxRingSize;
1213: }
1214:
1215: return 0;
1216: }
1217:
1218: /*
1219: ** Buffer sent - check for TX buffer errors.
1220: */
1221: static int
1222: de4x5_tx(struct device *dev)
1223: {
1224: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1225: u_long iobase = dev->base_addr;
1226: int entry;
1227: s32 status;
1228:
1229: for (entry = lp->tx_old; entry != lp->tx_new; entry = lp->tx_old) {
1230: status = lp->tx_ring[entry].status;
1231: if (status < 0) { /* Buffer not sent yet */
1232: break;
1233: } else if (status & TD_ES) { /* An error happened */
1234: lp->stats.tx_errors++;
1235: if (status & TD_NC) lp->stats.tx_carrier_errors++;
1236: if (status & TD_LC) lp->stats.tx_window_errors++;
1237: if (status & TD_UF) lp->stats.tx_fifo_errors++;
1238: if (status & TD_LC) lp->stats.collisions++;
1239: if (status & TD_EC) lp->pktStats.excessive_collisions++;
1240: if (status & TD_DE) lp->stats.tx_aborted_errors++;
1241:
1242: if ((status != 0x7fffffff) && /* Not setup frame */
1243: (status & (TD_LO | TD_NC | TD_EC | TD_LF))) {
1244: lp->lostMedia++;
1245: if (lp->lostMedia > LOST_MEDIA_THRESHOLD) { /* Trip autosense */
1246: kick_tx(dev);
1247: }
1248: } else {
1249: outl(POLL_DEMAND, DE4X5_TPD); /* Restart a stalled TX */
1250: }
1251: } else { /* Packet sent */
1252: lp->stats.tx_packets++;
1253: lp->lostMedia = 0; /* Remove transient problem */
1254: }
1255: /* Free the buffer if it's not a setup frame. */
1256: if (lp->skb[entry] != NULL) {
1257: dev_kfree_skb(lp->skb[entry], FREE_WRITE);
1258: lp->skb[entry] = NULL;
1259: }
1260:
1261: /* Update all the pointers */
1262: lp->tx_old = (++lp->tx_old) % lp->txRingSize;
1263: }
1264:
1265: return 0;
1266: }
1267:
1268: static int
1269: de4x5_ast(struct device *dev)
1270: {
1271: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1272: u_long iobase = dev->base_addr;
1273: s32 gep;
1274:
1275: disable_ast(dev);
1276:
1277: if (lp->chipset == DC21140) {
1278: gep = inl(DE4X5_GEP);
1279: if (((lp->media == _100Mb) && (gep & GEP_SLNK)) ||
1280: ((lp->media == _10Mb) && (gep & GEP_LNP)) ||
1281: ((lp->media == _10Mb) && !(gep & GEP_SLNK)) ||
1282: (lp->media == NC)) {
1283: if (lp->linkProb || ((lp->media == NC) && (!(gep & GEP_LNP)))) {
1284: lp->lostMedia = LOST_MEDIA_THRESHOLD + 1;
1285: lp->linkProb = 0;
1286: kick_tx(dev);
1287: } else {
1288: switch(lp->media) {
1289: case NC:
1290: lp->linkProb = 0;
1291: enable_ast(dev, DE4X5_AUTOSENSE_MS);
1292: break;
1293:
1294: case _10Mb:
1295: lp->linkProb = 1; /* Flag a potential problem */
1296: enable_ast(dev, 1500);
1297: break;
1298:
1299: case _100Mb:
1300: lp->linkProb = 1; /* Flag a potential problem */
1301: enable_ast(dev, 4000);
1302: break;
1303: }
1304: }
1305: } else {
1306: lp->linkProb = 0; /* Link OK */
1307: enable_ast(dev, DE4X5_AUTOSENSE_MS);
1308: }
1309: }
1310:
1311: return 0;
1312: }
1313:
1314: static int
1315: de4x5_close(struct device *dev)
1316: {
1317: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1318: u_long iobase = dev->base_addr;
1319: s32 imr, omr;
1320:
1321: dev->start = 0;
1322: dev->tbusy = 1;
1323:
1324: if (de4x5_debug > 1) {
1325: printk("%s: Shutting down ethercard, status was %8.8x.\n",
1326: dev->name, inl(DE4X5_STS));
1327: }
1328:
1329: /*
1330: ** We stop the DE4X5 here... mask interrupts and stop TX & RX
1331: */
1332: DISABLE_IRQs;
1333:
1334: STOP_DE4X5;
1335:
1336: /*
1337: ** Free the associated irq
1338: */
1339: free_irq(dev->irq);
1340: irq2dev_map[dev->irq] = 0;
1341:
1342: MOD_DEC_USE_COUNT;
1343:
1344: /* Put the adapter to sleep to save power */
1345: if (lp->chipset == DC21041) {
1346: outl(0, DE4X5_SICR);
1347: outl(CFDA_PSM, PCI_CFDA);
1348: }
1349:
1350: return 0;
1351: }
1352:
1353: static struct enet_statistics *
1354: de4x5_get_stats(struct device *dev)
1355: {
1356: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1357: u_long iobase = dev->base_addr;
1358:
1359: lp->stats.rx_missed_errors = (int) (inl(DE4X5_MFC) & (MFC_OVFL | MFC_CNTR));
1360:
1361: return &lp->stats;
1362: }
1363:
1364: static void load_packet(struct device *dev, char *buf, u32 flags, struct sk_buff *skb)
1365: {
1366: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1367:
1368: lp->tx_ring[lp->tx_new].buf = virt_to_bus(buf);
1369: lp->tx_ring[lp->tx_new].des1 &= TD_TER;
1370: lp->tx_ring[lp->tx_new].des1 |= flags;
1371: lp->skb[lp->tx_new] = skb;
1372: barrier();
1373: lp->tx_ring[lp->tx_new].status = T_OWN;
1374: barrier();
1375:
1376: return;
1377: }
1378: /*
1379: ** Set or clear the multicast filter for this adaptor.
1380: ** num_addrs == -1 Promiscuous mode, receive all packets - now supported.
1381: ** Can also use the ioctls.
1382: ** num_addrs == 0 Normal mode, clear multicast list
1383: ** num_addrs > 0 Multicast mode, receive normal and MC packets, and do
1384: ** best-effort filtering.
1385: ** num_addrs == HASH_TABLE_LEN
1386: ** Set all multicast bits (pass all multicasts).
1387: */
1388: static void
1389: set_multicast_list(struct device *dev)
1390: {
1391: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1392: u_long iobase = dev->base_addr;
1393:
1394: /* First, double check that the adapter is open */
1395: if (irq2dev_map[dev->irq] != NULL) {
1396: if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
1397: u32 omr;
1398: omr = inl(DE4X5_OMR);
1399: omr |= OMR_PR;
1400: outl(omr, DE4X5_OMR);
1401: } else {
1402: SetMulticastFilter(dev);
1403: if (lp->setup_f == HASH_PERF) {
1404: load_packet(dev, lp->setup_frame, TD_IC | HASH_F | TD_SET |
1405: SETUP_FRAME_LEN, NULL);
1406: } else {
1407: load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
1408: SETUP_FRAME_LEN, NULL);
1409: }
1410:
1411: lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1412: outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
1413: dev->trans_start = jiffies;
1414: }
1415: }
1416:
1417: return;
1418: }
1419:
1420: /*
1421: ** Calculate the hash code and update the logical address filter
1422: ** from a list of ethernet multicast addresses.
1423: ** Little endian crc one liner from Matt Thomas, DEC.
1424: */
1425: static void SetMulticastFilter(struct device *dev)
1426: {
1427: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1428: struct dev_mc_list *dmi=dev->mc_list;
1429: u_long iobase = dev->base_addr;
1430: int i, j, bit, byte;
1431: u16 hashcode;
1432: u32 omr, crc, poly = CRC_POLYNOMIAL_LE;
1433: char *pa;
1434: unsigned char *addrs;
1435:
1436: omr = inl(DE4X5_OMR);
1437: omr &= ~OMR_PR;
1438: pa = build_setup_frame(dev, ALL); /* Build the basic frame */
1439:
1440: if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 14)) {
1441: omr |= OMR_PM; /* Pass all multicasts */
1442: } else if (lp->setup_f == HASH_PERF) {
1443: /* Now update the MCA table */
1444: for (i=0;i<dev->mc_count;i++) { /* for each address in the list */
1445: addrs=dmi->dmi_addr;
1446: dmi=dmi->next;
1447: if ((*addrs & 0x01) == 1) { /* multicast address? */
1448: crc = 0xffffffff; /* init CRC for each address */
1449: for (byte=0;byte<ETH_ALEN;byte++) { /* for each address byte */
1450: /* process each address bit */
1451: for (bit = *addrs++,j=0;j<8;j++, bit>>=1) {
1452: crc = (crc >> 1) ^ (((crc ^ bit) & 0x01) ? poly : 0);
1453: }
1454: }
1455: hashcode = crc & HASH_BITS; /* hashcode is 9 LSb of CRC */
1456:
1457: byte = hashcode >> 3; /* bit[3-8] -> byte in filter */
1458: bit = 1 << (hashcode & 0x07); /* bit[0-2] -> bit in byte */
1459:
1460: byte <<= 1; /* calc offset into setup frame */
1461: if (byte & 0x02) {
1462: byte -= 1;
1463: }
1464: lp->setup_frame[byte] |= bit;
1465: }
1466: }
1467: } else { /* Perfect filtering */
1468: for (j=0; j<dev->mc_count; j++) {
1469: addrs=dmi->dmi_addr;
1470: dmi=dmi->next;
1471: for (i=0; i<ETH_ALEN; i++) {
1472: *(pa + (i&1)) = *addrs++;
1473: if (i & 0x01) pa += 4;
1474: }
1475: }
1476: }
1477: outl(omr, DE4X5_OMR);
1478:
1479: return;
1480: }
1481:
1482: /*
1483: ** EISA bus I/O device probe. Probe from slot 1 since slot 0 is usually
1484: ** the motherboard. Upto 15 EISA devices are supported.
1485: */
1486: static void eisa_probe(struct device *dev, u_long ioaddr)
1487: {
1488: int i, maxSlots, status;
1489: u_short vendor, device;
1490: s32 cfid;
1491: u_long iobase;
1492: struct bus_type *lp = &bus;
1493: char name[DE4X5_STRLEN];
1494:
1495: if (!ioaddr && autoprobed) return ; /* Been here before ! */
1496: if ((ioaddr < 0x1000) && (ioaddr > 0)) return; /* PCI MODULE special */
1497:
1498: lp->bus = EISA;
1499:
1500: if (ioaddr == 0) { /* Autoprobing */
1501: iobase = EISA_SLOT_INC; /* Get the first slot address */
1502: i = 1;
1503: maxSlots = MAX_EISA_SLOTS;
1504: } else { /* Probe a specific location */
1505: iobase = ioaddr;
1506: i = (ioaddr >> 12);
1507: maxSlots = i + 1;
1508: }
1509:
1510: for (status = -ENODEV; (i<maxSlots) && (dev!=NULL); i++, iobase+=EISA_SLOT_INC) {
1511: if (EISA_signature(name, EISA_ID)) {
1512: cfid = inl(PCI_CFID);
1513: device = (u_short)(cfid >> 16);
1514: vendor = (u_short) cfid;
1515:
1516: lp->bus = EISA;
1517: lp->chipset = device;
1518: if (DevicePresent(EISA_APROM) == 0) {
1519: /* Write the PCI Configuration Registers */
1520: outl(PCI_COMMAND_IO | PCI_COMMAND_MASTER, PCI_CFCS);
1521: outl(0x00004000, PCI_CFLT);
1522: outl(iobase, PCI_CBIO);
1523:
1524: if (check_region(iobase, DE4X5_EISA_TOTAL_SIZE) == 0) {
1525: if ((dev = alloc_device(dev, iobase)) != NULL) {
1526: if ((status = de4x5_hw_init(dev, iobase)) == 0) {
1527: num_de4x5s++;
1528: }
1529: num_eth++;
1530: }
1531: } else if (autoprobed) {
1532: printk("%s: region already allocated at 0x%04lx.\n", dev->name, iobase);
1533: }
1534: }
1535: }
1536: }
1537:
1538: return;
1539: }
1540:
1541: /*
1542: ** PCI bus I/O device probe
1543: ** NB: PCI I/O accesses and Bus Mastering are enabled by the PCI BIOS, not
1544: ** the driver. Some PCI BIOS's, pre V2.1, need the slot + features to be
1545: ** enabled by the user first in the set up utility. Hence we just check for
1546: ** enabled features and silently ignore the card if they're not.
1547: **
1548: ** STOP PRESS: Some BIOS's __require__ the driver to enable the bus mastering
1549: ** bit. Here, check for I/O accesses and then set BM. If you put the card in
1550: ** a non BM slot, you're on your own (and complain to the PC vendor that your
1551: ** PC doesn't conform to the PCI standard)!
1552: */
1553: #define PCI_DEVICE (dev_num << 3)
1554: #define PCI_LAST_DEV 32
1555:
1556: static void pci_probe(struct device *dev, u_long ioaddr)
1557: {
1558: u_char irq;
1559: u_char pb, pbus, dev_num, dnum, dev_fn;
1560: u_short vendor, device, index, status;
1561: u_int class = DE4X5_CLASS_CODE;
1562: u_int iobase;
1563: struct bus_type *lp = &bus;
1564:
1565: if (!ioaddr && autoprobed) return ; /* Been here before ! */
1566:
1567: if (pcibios_present()) {
1568: lp->bus = PCI;
1569:
1570: if (ioaddr < 0x1000) {
1571: pbus = (u_short)(ioaddr >> 8);
1572: dnum = (u_short)(ioaddr & 0xff);
1573: } else {
1574: pbus = 0;
1575: dnum = 0;
1576: }
1577:
1578: for (index=0;
1579: (pcibios_find_class(class, index, &pb, &dev_fn)!= PCIBIOS_DEVICE_NOT_FOUND);
1580: index++) {
1581: dev_num = PCI_SLOT(dev_fn);
1582:
1583: if ((!pbus && !dnum) || ((pbus == pb) && (dnum == dev_num))) {
1584: pcibios_read_config_word(pb, PCI_DEVICE, PCI_VENDOR_ID, &vendor);
1585: pcibios_read_config_word(pb, PCI_DEVICE, PCI_DEVICE_ID, &device);
1586: if (is_DC21040 || is_DC21041 || is_DC21140) {
1587: /* Set the device number information */
1588: lp->device = dev_num;
1589: lp->bus_num = pb;
1590:
1591: /* Set the chipset information */
1592: lp->chipset = device;
1593:
1594: /* Get the board I/O address */
1595: pcibios_read_config_dword(pb, PCI_DEVICE, PCI_BASE_ADDRESS_0, &iobase);
1596: iobase &= CBIO_MASK;
1597:
1598: /* Fetch the IRQ to be used */
1599: pcibios_read_config_byte(pb, PCI_DEVICE, PCI_INTERRUPT_LINE, &irq);
1600:
1601: /* Check if I/O accesses and Bus Mastering are enabled */
1602: pcibios_read_config_word(pb, PCI_DEVICE, PCI_COMMAND, &status);
1603: if (status & PCI_COMMAND_IO) {
1604: if (!(status & PCI_COMMAND_MASTER)) {
1605: status |= PCI_COMMAND_MASTER;
1606: pcibios_write_config_word(pb, PCI_DEVICE, PCI_COMMAND, status);
1607: pcibios_read_config_word(pb, PCI_DEVICE, PCI_COMMAND, &status);
1608: }
1609: if (status & PCI_COMMAND_MASTER) {
1610: if ((DevicePresent(DE4X5_APROM) == 0) || is_not_dec) {
1611: if (check_region(iobase, DE4X5_PCI_TOTAL_SIZE) == 0) {
1612: if ((dev = alloc_device(dev, iobase)) != NULL) {
1613: dev->irq = irq;
1614: if ((status = de4x5_hw_init(dev, iobase)) == 0) {
1615: num_de4x5s++;
1616: }
1617: num_eth++;
1618: }
1619: } else if (autoprobed) {
1620: printk("%s: region already allocated at 0x%04x.\n", dev->name, (u_short)iobase);
1621: }
1622: }
1623: }
1624: }
1625: }
1626: }
1627: }
1628: }
1629:
1630: return;
1631: }
1632:
1633: /*
1634: ** Allocate the device by pointing to the next available space in the
1635: ** device structure. Should one not be available, it is created.
1636: */
1637: static struct device *alloc_device(struct device *dev, u_long iobase)
1638: {
1639: int addAutoProbe = 0;
1640: struct device *tmp = NULL, *ret;
1641: int (*init)(struct device *) = NULL;
1642:
1643: /*
1644: ** Check the device structures for an end of list or unused device
1645: */
1646: if (!loading_module) {
1647: while (dev->next != NULL) {
1648: if ((dev->base_addr == DE4X5_NDA) || (dev->base_addr == 0)) break;
1649: dev = dev->next; /* walk through eth device list */
1650: num_eth++; /* increment eth device number */
1651: }
1652:
1653: /*
1654: ** If an autoprobe is requested for another device, we must re-insert
1655: ** the request later in the list. Remember the current position first.
1656: */
1657: if ((dev->base_addr == 0) && (num_de4x5s > 0)) {
1658: addAutoProbe++;
1659: tmp = dev->next; /* point to the next device */
1660: init = dev->init; /* remember the probe function */
1661: }
1662:
1663: /*
1664: ** If at end of list and can't use current entry, malloc one up.
1665: ** If memory could not be allocated, print an error message.
1666: */
1667: if ((dev->next == NULL) &&
1668: !((dev->base_addr == DE4X5_NDA) || (dev->base_addr == 0))){
1669: dev->next = (struct device *)kmalloc(sizeof(struct device) + 8,
1670: GFP_KERNEL);
1671:
1672: dev = dev->next; /* point to the new device */
1673: if (dev == NULL) {
1674: printk("eth%d: Device not initialised, insufficient memory\n",
1675: num_eth);
1676: } else {
1677: /*
1678: ** If the memory was allocated, point to the new memory area
1679: ** and initialize it (name, I/O address, next device (NULL) and
1680: ** initialisation probe routine).
1681: */
1682: dev->name = (char *)(dev + sizeof(struct device));
1683: if (num_eth > 9999) {
1684: sprintf(dev->name,"eth????"); /* New device name */
1685: } else {
1686: sprintf(dev->name,"eth%d", num_eth);/* New device name */
1687: }
1688: dev->base_addr = iobase; /* assign the io address */
1689: dev->next = NULL; /* mark the end of list */
1690: dev->init = &de4x5_probe; /* initialisation routine */
1691: num_de4x5s++;
1692: }
1693: }
1694: ret = dev; /* return current struct, or NULL */
1695:
1696: /*
1697: ** Now figure out what to do with the autoprobe that has to be inserted.
1698: ** Firstly, search the (possibly altered) list for an empty space.
1699: */
1700: if (ret != NULL) {
1701: if (addAutoProbe) {
1702: for (; (tmp->next!=NULL) && (tmp->base_addr!=DE4X5_NDA); tmp=tmp->next);
1703:
1704: /*
1705: ** If no more device structures and can't use the current one, malloc
1706: ** one up. If memory could not be allocated, print an error message.
1707: */
1708: if ((tmp->next == NULL) && !(tmp->base_addr == DE4X5_NDA)) {
1709: tmp->next = (struct device *)kmalloc(sizeof(struct device) + 8,
1710: GFP_KERNEL);
1711: tmp = tmp->next; /* point to the new device */
1712: if (tmp == NULL) {
1713: printk("%s: Insufficient memory to extend the device list.\n",
1714: dev->name);
1715: } else {
1716: /*
1717: ** If the memory was allocated, point to the new memory area
1718: ** and initialize it (name, I/O address, next device (NULL) and
1719: ** initialisation probe routine).
1720: */
1721: tmp->name = (char *)(tmp + sizeof(struct device));
1722: if (num_eth > 9999) {
1723: sprintf(tmp->name,"eth????"); /* New device name */
1724: } else {
1725: sprintf(tmp->name,"eth%d", num_eth);/* New device name */
1726: }
1727: tmp->base_addr = 0; /* re-insert the io address */
1728: tmp->next = NULL; /* mark the end of list */
1729: tmp->init = init; /* initialisation routine */
1730: }
1731: } else { /* structure already exists */
1732: tmp->base_addr = 0; /* re-insert the io address */
1733: }
1734: }
1735: }
1736: } else {
1737: ret = dev;
1738: }
1739:
1740: return ret;
1741: }
1742:
1743: /*
1744: ** Auto configure the media here rather than setting the port at compile
1745: ** time. This routine is called by de4x5_init() when a loss of media is
1746: ** detected (excessive collisions, loss of carrier, no carrier or link fail
1747: ** [TP]) to check whether the user has been sneaky and changed the port on us.
1748: */
1749: static int autoconf_media(struct device *dev)
1750: {
1751: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1752: u_long iobase = dev->base_addr;
1753:
1754: lp->tx_enable = YES;
1755: if (de4x5_debug > 0 ) {
1756: if (lp->chipset != DC21140) {
1757: printk("%s: Searching for media... ",dev->name);
1758: } else {
1759: printk("%s: Searching for mode... ",dev->name);
1760: }
1761: }
1762:
1763: if (lp->chipset == DC21040) {
1764: lp->media = (lp->autosense == AUTO ? TP : lp->autosense);
1765: dc21040_autoconf(dev);
1766: } else if (lp->chipset == DC21041) {
1767: lp->media = (lp->autosense == AUTO ? TP_NW : lp->autosense);
1768: dc21041_autoconf(dev);
1769: } else if (lp->chipset == DC21140) {
1770: disable_ast(dev);
1771: lp->media = (lp->autosense == AUTO ? _10Mb : lp->autosense);
1772: dc21140_autoconf(dev);
1773: }
1774:
1775: if (de4x5_debug > 0 ) {
1776: if (lp->chipset != DC21140) {
1777: printk("media is %s\n", (lp->media == NC ? "unconnected!" :
1778: (lp->media == TP ? "TP." :
1779: (lp->media == ANS ? "TP/Nway." :
1780: (lp->media == BNC ? "BNC." :
1781: (lp->media == AUI ? "AUI." :
1782: "BNC/AUI."
1783: ))))));
1784: } else {
1785: printk("mode is %s\n",(lp->media == NC ? "link down.":
1786: (lp->media == _100Mb ? "100Mb/s." :
1787: (lp->media == _10Mb ? "10Mb/s." :
1788: "\?\?\?"
1789: ))));
1790: }
1791: }
1792:
1793: if (lp->media) {
1794: lp->lostMedia = 0;
1795: inl(DE4X5_MFC); /* Zero the lost frames counter */
1796: if ((lp->media == TP) || (lp->media == ANS)) {
1797: lp->irq_mask |= IMR_LFM;
1798: }
1799: }
1800: dce_ms_delay(10);
1801:
1802: return (lp->media);
1803: }
1804:
1805: static void dc21040_autoconf(struct device *dev)
1806: {
1807: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1808: u_long iobase = dev->base_addr;
1809: int i, linkBad;
1810: s32 sisr = 0, t_3s = 3000;
1811:
1812: switch (lp->media) {
1813: case TP:
1814: reset_init_sia(dev, 0x8f01, 0xffff, 0x0000);
1815: for (linkBad=1,i=0;(i<t_3s) && linkBad && !(sisr & SISR_NCR);i++) {
1816: if (((sisr = inl(DE4X5_SISR)) & SISR_LKF) == 0) linkBad = 0;
1817: dce_ms_delay(1);
1818: }
1819: if (linkBad && (lp->autosense == AUTO)) {
1820: lp->media = BNC_AUI;
1821: dc21040_autoconf(dev);
1822: }
1823: break;
1824:
1825: case BNC:
1826: case AUI:
1827: case BNC_AUI:
1828: reset_init_sia(dev, 0x8f09, 0x0705, 0x0006);
1829: dce_ms_delay(500);
1830: linkBad = ping_media(dev);
1831: if (linkBad && (lp->autosense == AUTO)) {
1832: lp->media = EXT_SIA;
1833: dc21040_autoconf(dev);
1834: }
1835: break;
1836:
1837: case EXT_SIA:
1838: reset_init_sia(dev, 0x3041, 0x0000, 0x0006);
1839: dce_ms_delay(500);
1840: linkBad = ping_media(dev);
1841: if (linkBad && (lp->autosense == AUTO)) {
1842: lp->media = NC;
1843: dc21040_autoconf(dev);
1844: }
1845: break;
1846:
1847: case NC:
1848: #ifndef __alpha__
1849: reset_init_sia(dev, 0x8f01, 0xffff, 0x0000);
1850: break;
1851: #else
1852: /* JAE: for Alpha, default to BNC/AUI, *not* TP */
1853: reset_init_sia(dev, 0x8f09, 0x0705, 0x0006);
1854: #endif /* i386 */
1855: }
1856:
1857: return;
1858: }
1859:
1860: /*
1861: ** Autoconfigure the media when using the DC21041. AUI needs to be tested
1862: ** before BNC, because the BNC port will indicate activity if it's not
1863: ** terminated correctly. The only way to test for that is to place a loopback
1864: ** packet onto the network and watch for errors.
1865: */
1866: static void dc21041_autoconf(struct device *dev)
1867: {
1868: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1869: u_long iobase = dev->base_addr;
1870: s32 sts, irqs, irq_mask, omr;
1871:
1872: switch (lp->media) {
1873: case TP_NW:
1874: omr = inl(DE4X5_OMR); /* Set up full duplex for the autonegotiate */
1875: outl(omr | OMR_FD, DE4X5_OMR);
1876: irqs = STS_LNF | STS_LNP;
1877: irq_mask = IMR_LFM | IMR_LPM;
1878: sts = test_media(dev, irqs, irq_mask, 0xef01, 0xffff, 0x0008, 2400);
1879: if (sts & STS_LNP) {
1880: lp->media = ANS;
1881: } else {
1882: lp->media = AUI;
1883: }
1884: dc21041_autoconf(dev);
1885: break;
1886:
1887: case ANS:
1888: irqs = STS_LNP;
1889: irq_mask = IMR_LPM;
1890: sts = test_ans(dev, irqs, irq_mask, 3000);
1891: if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
1892: lp->media = TP;
1893: dc21041_autoconf(dev);
1894: }
1895: break;
1896:
1897: case TP:
1898: omr = inl(DE4X5_OMR); /* Set up half duplex for TP */
1899: outl(omr & ~OMR_FD, DE4X5_OMR);
1900: irqs = STS_LNF | STS_LNP;
1901: irq_mask = IMR_LFM | IMR_LPM;
1902: sts = test_media(dev, irqs, irq_mask, 0xef01, 0xff3f, 0x0008, 2400);
1903: if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
1904: if (inl(DE4X5_SISR) & SISR_NRA) { /* Non selected port activity */
1905: lp->media = AUI;
1906: } else {
1907: lp->media = BNC;
1908: }
1909: dc21041_autoconf(dev);
1910: }
1911: break;
1912:
1913: case AUI:
1914: omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
1915: outl(omr & ~OMR_FD, DE4X5_OMR);
1916: irqs = 0;
1917: irq_mask = 0;
1918: sts = test_media(dev, irqs, irq_mask, 0xef09, 0xf7fd, 0x000e, 1000);
1919: if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
1920: lp->media = BNC;
1921: dc21041_autoconf(dev);
1922: }
1923: break;
1924:
1925: case BNC:
1926: omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
1927: outl(omr & ~OMR_FD, DE4X5_OMR);
1928: irqs = 0;
1929: irq_mask = 0;
1930: sts = test_media(dev, irqs, irq_mask, 0xef09, 0xf7fd, 0x0006, 1000);
1931: if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
1932: lp->media = NC;
1933: } else { /* Ensure media connected */
1934: if (ping_media(dev)) lp->media = NC;
1935: }
1936: break;
1937:
1938: case NC:
1939: omr = inl(DE4X5_OMR); /* Set up full duplex for the autonegotiate */
1940: outl(omr | OMR_FD, DE4X5_OMR);
1941: reset_init_sia(dev, 0xef01, 0xffff, 0x0008);/* Initialise the SIA */
1942: break;
1943: }
1944:
1945: return;
1946: }
1947:
1948: /*
1949: ** Reduced feature version (temporary I hope)
1950: */
1951: static void dc21140_autoconf(struct device *dev)
1952: {
1953: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1954: u_long iobase = dev->base_addr;
1955: s32 omr;
1956:
1957: switch(lp->media) {
1958: case _100Mb: /* Set 100Mb/s, MII Port with PCS Function and Scrambler */
1959: omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR));
1960: omr |= (de4x5_full_duplex ? OMR_FD : 0); /* Set up Full Duplex */
1961: outl(omr | OMR_PS | OMR_HBD | OMR_PCS | OMR_SCR, DE4X5_OMR);
1962: outl(GEP_FDXD | GEP_MODE, DE4X5_GEP);
1963: break;
1964:
1965: case _10Mb: /* Set conventional 10Mb/s ENDEC interface */
1966: omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR));
1967: omr |= (de4x5_full_duplex ? OMR_FD : 0); /* Set up Full Duplex */
1968: outl(omr | OMR_TTM, DE4X5_OMR);
1969: outl(GEP_FDXD, DE4X5_GEP);
1970: break;
1971: }
1972:
1973: return;
1974: }
1975:
1976: static int
1977: test_media(struct device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec)
1978: {
1979: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1980: u_long iobase = dev->base_addr;
1981: s32 sts, time, csr12;
1982:
1983: reset_init_sia(dev, csr13, csr14, csr15);
1984:
1985: /* Set link_fail_inhibit_timer */
1986: load_ms_timer(dev, msec);
1987:
1988: /* clear all pending interrupts */
1989: sts = inl(DE4X5_STS);
1990: outl(sts, DE4X5_STS);
1991:
1992: /* clear csr12 NRA and SRA bits */
1993: csr12 = inl(DE4X5_SISR);
1994: outl(csr12, DE4X5_SISR);
1995:
1996: /* Poll for timeout - timer interrupt doesn't work correctly */
1997: do {
1998: time = inl(DE4X5_GPT) & GPT_VAL;
1999: sts = inl(DE4X5_STS);
2000: } while ((time != 0) && !(sts & irqs));
2001:
2002: sts = inl(DE4X5_STS);
2003:
2004: return sts;
2005: }
2006: /*
2007: static int test_sym_link(struct device *dev, u32 msec)
2008: {
2009: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2010: u_long iobase = dev->base_addr;
2011: u32 gep, time;
2012:
2013: / * Set link_fail_inhibit_timer * /
2014: load_ms_timer(dev, msec);
2015:
2016: / * Poll for timeout or SYM_LINK=0 * /
2017: do {
2018: time = inl(DE4X5_GPT) & GPT_VAL;
2019: gep = inl(DE4X5_GEP) & (GEP_SLNK | GEP_LNP);
2020: } while ((time > 0) && (gep & GEP_SLNK));
2021:
2022: return gep;
2023: }
2024: */
2025: /*
2026: ** Send a packet onto the media and watch for send errors that indicate the
2027: ** media is bad or unconnected.
2028: */
2029: static int ping_media(struct device *dev)
2030: {
2031: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2032: u_long iobase = dev->base_addr;
2033: int i, entry, linkBad;
2034: s32 omr, t_3s = 4000;
2035: char frame[64];
2036:
2037: create_packet(dev, frame, sizeof(frame));
2038:
2039: entry = lp->tx_new; /* Remember the ring position */
2040: load_packet(dev, frame, TD_LS | TD_FS | sizeof(frame),NULL);
2041:
2042: omr = inl(DE4X5_OMR);
2043: outl(omr|OMR_ST, DE4X5_OMR);
2044:
2045: lp->tx_new = (++lp->tx_new) % lp->txRingSize;
2046: lp->tx_old = lp->tx_new;
2047:
2048: /* Poll for completion of frame (interrupts are disabled for now)... */
2049: for (linkBad=1,i=0;(i<t_3s) && linkBad;i++) {
2050: if ((inl(DE4X5_SISR) & SISR_NCR) == 1) break;
2051: if (lp->tx_ring[entry].status >= 0) linkBad=0;
2052: dce_ms_delay(1);
2053: }
2054: outl(omr, DE4X5_OMR);
2055:
2056: return ((linkBad || (lp->tx_ring[entry].status & TD_ES)) ? 1 : 0);
2057: }
2058:
2059: /*
2060: ** Check the Auto Negotiation State. Return OK when a link pass interrupt
2061: ** is received and the auto-negotiation status is NWAY OK.
2062: */
2063: static int test_ans(struct device *dev, s32 irqs, s32 irq_mask, s32 msec)
2064: {
2065: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2066: u_long iobase = dev->base_addr;
2067: s32 sts, ans;
2068:
2069: outl(irq_mask, DE4X5_IMR);
2070:
2071: /* Set timeout limit */
2072: load_ms_timer(dev, msec);
2073:
2074: /* clear all pending interrupts */
2075: sts = inl(DE4X5_STS);
2076: outl(sts, DE4X5_STS);
2077:
2078: /* Poll for interrupts */
2079: do {
2080: ans = inl(DE4X5_SISR) & SISR_ANS;
2081: sts = inl(DE4X5_STS);
2082: } while (!(sts & irqs) && (ans ^ ANS_NWOK) != 0);
2083:
2084: return ((sts & STS_LNP) && ((ans ^ ANS_NWOK) == 0) ? STS_LNP : 0);
2085: }
2086:
2087: /*
2088: **
2089: */
2090: static void reset_init_sia(struct device *dev, s32 sicr, s32 strr, s32 sigr)
2091: {
2092: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2093: u_long iobase = dev->base_addr;
2094:
2095: RESET_SIA;
2096: outl(sigr, DE4X5_SIGR);
2097: outl(strr, DE4X5_STRR);
2098: outl(sicr, DE4X5_SICR);
2099:
2100: return;
2101: }
2102:
2103: /*
2104: ** Load the timer on the DC21041 and 21140. Max time is 13.42 secs.
2105: */
2106: static void load_ms_timer(struct device *dev, u32 msec)
2107: {
2108: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2109: u_long iobase = dev->base_addr;
2110: s32 i = 2048, j;
2111:
2112: if (lp->chipset == DC21140) {
2113: j = inl(DE4X5_OMR);
2114: if ((j & OMR_TTM) && (j & OMR_PS)) { /* 10Mb/s MII */
2115: i = 8192;
2116: } else if ((~j & OMR_TTM) && (j & OMR_PS)) { /* 100Mb/s MII */
2117: i = 819;
2118: }
2119: }
2120:
2121: outl((s32)(msec * 10000)/i, DE4X5_GPT);
2122:
2123: return;
2124: }
2125:
2126: /*
2127: ** Create an Ethernet packet with an invalid CRC
2128: */
2129: static void create_packet(struct device *dev, char *frame, int len)
2130: {
2131: int i;
2132: char *buf = frame;
2133:
2134: for (i=0; i<ETH_ALEN; i++) { /* Use this source address */
2135: *buf++ = dev->dev_addr[i];
2136: }
2137: for (i=0; i<ETH_ALEN; i++) { /* Use this destination address */
2138: *buf++ = dev->dev_addr[i];
2139: }
2140:
2141: *buf++ = 0; /* Packet length (2 bytes) */
2142: *buf++ = 1;
2143:
2144: return;
2145: }
2146:
2147: /*
2148: ** Known delay in microseconds
2149: */
2150: static void dce_us_delay(u32 usec)
2151: {
2152: udelay(usec);
2153:
2154: return;
2155: }
2156:
2157: /*
2158: ** Known delay in milliseconds, in millisecond steps.
2159: */
2160: static void dce_ms_delay(u32 msec)
2161: {
2162: u_int i;
2163:
2164: for (i=0; i<msec; i++) {
2165: dce_us_delay(1000);
2166: }
2167:
2168: return;
2169: }
2170:
2171:
2172: /*
2173: ** Look for a particular board name in the EISA configuration space
2174: */
2175: static int EISA_signature(char *name, s32 eisa_id)
2176: {
2177: u_int i;
2178: const char *signatures[] = DE4X5_SIGNATURE;
2179: char ManCode[DE4X5_STRLEN];
2180: union {
2181: s32 ID;
2182: char Id[4];
2183: } Eisa;
2184: int status = 0;
2185:
2186: *name = '\0';
2187: Eisa.ID = inl(eisa_id);
2188:
2189: ManCode[0]=(((Eisa.Id[0]>>2)&0x1f)+0x40);
2190: ManCode[1]=(((Eisa.Id[1]&0xe0)>>5)+((Eisa.Id[0]&0x03)<<3)+0x40);
2191: ManCode[2]=(((Eisa.Id[2]>>4)&0x0f)+0x30);
2192: ManCode[3]=((Eisa.Id[2]&0x0f)+0x30);
2193: ManCode[4]=(((Eisa.Id[3]>>4)&0x0f)+0x30);
2194: ManCode[5]='\0';
2195:
2196: for (i=0;(*signatures[i] != '\0') && (*name == '\0');i++) {
2197: if (strstr(ManCode, signatures[i]) != NULL) {
2198: strcpy(name,ManCode);
2199: status = 1;
2200: }
2201: }
2202:
2203: return status; /* return the device name string */
2204: }
2205:
2206: /*
2207: ** Look for a special sequence in the Ethernet station address PROM that
2208: ** is common across all DIGITAL network adapter products.
2209: **
2210: ** Search the Ethernet address ROM for the signature. Since the ROM address
2211: ** counter can start at an arbitrary point, the search must include the entire
2212: ** probe sequence length plus the (length_of_the_signature - 1).
2213: ** Stop the search IMMEDIATELY after the signature is found so that the
2214: ** PROM address counter is correctly positioned at the start of the
2215: ** ethernet address for later read out.
2216: */
2217:
2218: static int DevicePresent(u_long aprom_addr)
2219: {
2220: union {
2221: struct {
2222: u32 a;
2223: u32 b;
2224: } llsig;
2225: char Sig[sizeof(u32) << 1];
2226: } dev;
2227: char data;
2228: int i, j, tmp, status = 0;
2229: short sigLength;
2230: struct bus_type *lp = &bus;
2231:
2232: dev.llsig.a = ETH_PROM_SIG;
2233: dev.llsig.b = ETH_PROM_SIG;
2234: sigLength = sizeof(u32) << 1;
2235:
2236: if (lp->chipset == DC21040) {
2237: for (i=0,j=0;(j<sigLength) && (i<PROBE_LENGTH+sigLength-1);i++) {
2238: if (lp->bus == PCI) {
2239: while ((tmp = inl(aprom_addr)) < 0);
2240: data = (char)tmp;
2241: } else {
2242: data = inb(aprom_addr);
2243: }
2244: if (dev.Sig[j] == data) { /* track signature */
2245: j++;
2246: } else { /* lost signature; begin search again */
2247: if (data == dev.Sig[0]) {
2248: j=1;
2249: } else {
2250: j=0;
2251: }
2252: }
2253: }
2254:
2255: if (j!=sigLength) {
2256: status = -ENODEV; /* search failed */
2257: }
2258:
2259: } else { /* use new srom */
2260: short *p = (short *)&lp->srom;
2261: for (i=0; i<(sizeof(struct de4x5_srom)>>1); i++) {
2262: *p++ = srom_rd(aprom_addr, i);
2263: }
2264: }
2265:
2266: return status;
2267: }
2268:
2269: static int get_hw_addr(struct device *dev)
2270: {
2271: u_long iobase = dev->base_addr;
2272: int i, k, tmp, status = 0;
2273: u_short j,chksum;
2274: struct bus_type *lp = &bus;
2275:
2276: for (i=0,k=0,j=0;j<3;j++) {
2277: k <<= 1 ;
2278: if (k > 0xffff) k-=0xffff;
2279:
2280: if (lp->bus == PCI) {
2281: if (lp->chipset == DC21040) {
2282: while ((tmp = inl(DE4X5_APROM)) < 0);
2283: k += (u_char) tmp;
2284: dev->dev_addr[i++] = (u_char) tmp;
2285: while ((tmp = inl(DE4X5_APROM)) < 0);
2286: k += (u_short) (tmp << 8);
2287: dev->dev_addr[i++] = (u_char) tmp;
2288: } else {
2289: dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
2290: dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
2291: }
2292: } else {
2293: k += (u_char) (tmp = inb(EISA_APROM));
2294: dev->dev_addr[i++] = (u_char) tmp;
2295: k += (u_short) ((tmp = inb(EISA_APROM)) << 8);
2296: dev->dev_addr[i++] = (u_char) tmp;
2297: }
2298:
2299: if (k > 0xffff) k-=0xffff;
2300: }
2301: if (k == 0xffff) k=0;
2302:
2303: if (lp->bus == PCI) {
2304: if (lp->chipset == DC21040) {
2305: while ((tmp = inl(DE4X5_APROM)) < 0);
2306: chksum = (u_char) tmp;
2307: while ((tmp = inl(DE4X5_APROM)) < 0);
2308: chksum |= (u_short) (tmp << 8);
2309: if (k != chksum) status = -1;
2310: }
2311: } else {
2312: chksum = (u_char) inb(EISA_APROM);
2313: chksum |= (u_short) (inb(EISA_APROM) << 8);
2314: if (k != chksum) status = -1;
2315: }
2316:
2317:
2318: return status;
2319: }
2320:
2321: /*
2322: ** SROM Read
2323: */
2324: static short srom_rd(u_long addr, u_char offset)
2325: {
2326: sendto_srom(SROM_RD | SROM_SR, addr);
2327:
2328: srom_latch(SROM_RD | SROM_SR | DT_CS, addr);
2329: srom_command(SROM_RD | SROM_SR | DT_IN | DT_CS, addr);
2330: srom_address(SROM_RD | SROM_SR | DT_CS, addr, offset);
2331:
2332: return srom_data(SROM_RD | SROM_SR | DT_CS, addr);
2333: }
2334:
2335: static void srom_latch(u_int command, u_long addr)
2336: {
2337: sendto_srom(command, addr);
2338: sendto_srom(command | DT_CLK, addr);
2339: sendto_srom(command, addr);
2340:
2341: return;
2342: }
2343:
2344: static void srom_command(u_int command, u_long addr)
2345: {
2346: srom_latch(command, addr);
2347: srom_latch(command, addr);
2348: srom_latch((command & 0x0000ff00) | DT_CS, addr);
2349:
2350: return;
2351: }
2352:
2353: static void srom_address(u_int command, u_long addr, u_char offset)
2354: {
2355: int i;
2356: char a;
2357:
2358: a = (char)(offset << 2);
2359: for (i=0; i<6; i++, a <<= 1) {
2360: srom_latch(command | ((a < 0) ? DT_IN : 0), addr);
2361: }
2362: dce_us_delay(1);
2363:
2364: i = (getfrom_srom(addr) >> 3) & 0x01;
2365: if (i != 0) {
2366: printk("Bad SROM address phase.....\n");
2367: /* printk(".");*/
2368: }
2369:
2370: return;
2371: }
2372:
2373: static short srom_data(u_int command, u_long addr)
2374: {
2375: int i;
2376: short word = 0;
2377: s32 tmp;
2378:
2379: for (i=0; i<16; i++) {
2380: sendto_srom(command | DT_CLK, addr);
2381: tmp = getfrom_srom(addr);
2382: sendto_srom(command, addr);
2383:
2384: word = (word << 1) | ((tmp >> 3) & 0x01);
2385: }
2386:
2387: sendto_srom(command & 0x0000ff00, addr);
2388:
2389: return word;
2390: }
2391:
2392: /*
2393: static void srom_busy(u_int command, u_long addr)
2394: {
2395: sendto_srom((command & 0x0000ff00) | DT_CS, addr);
2396:
2397: while (!((getfrom_srom(addr) >> 3) & 0x01)) {
2398: dce_ms_delay(1);
2399: }
2400:
2401: sendto_srom(command & 0x0000ff00, addr);
2402:
2403: return;
2404: }
2405: */
2406:
2407: static void sendto_srom(u_int command, u_long addr)
2408: {
2409: outl(command, addr);
2410: dce_us_delay(1);
2411:
2412: return;
2413: }
2414:
2415: static int getfrom_srom(u_long addr)
2416: {
2417: s32 tmp;
2418:
2419: tmp = inl(addr);
2420: dce_us_delay(1);
2421:
2422: return tmp;
2423: }
2424:
2425: static char *build_setup_frame(struct device *dev, int mode)
2426: {
2427: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2428: int i;
2429: char *pa = lp->setup_frame;
2430:
2431: /* Initialise the setup frame */
2432: if (mode == ALL) {
2433: memset(lp->setup_frame, 0, SETUP_FRAME_LEN);
2434: }
2435:
2436: if (lp->setup_f == HASH_PERF) {
2437: for (pa=lp->setup_frame+IMPERF_PA_OFFSET, i=0; i<ETH_ALEN; i++) {
2438: *(pa + i) = dev->dev_addr[i]; /* Host address */
2439: if (i & 0x01) pa += 2;
2440: }
2441: *(lp->setup_frame + (HASH_TABLE_LEN >> 3) - 3) = 0x80; /* B'cast address */
2442: } else {
2443: for (i=0; i<ETH_ALEN; i++) { /* Host address */
2444: *(pa + (i&1)) = dev->dev_addr[i];
2445: if (i & 0x01) pa += 4;
2446: }
2447: for (i=0; i<ETH_ALEN; i++) { /* Broadcast address */
2448: *(pa + (i&1)) = (char) 0xff;
2449: if (i & 0x01) pa += 4;
2450: }
2451: }
2452:
2453: return pa; /* Points to the next entry */
2454: }
2455:
2456: static void enable_ast(struct device *dev, u32 time_out)
2457: {
2458: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2459: u_long iobase = dev->base_addr;
2460:
2461: lp->irq_mask |= IMR_TMM;
2462: outl(lp->irq_mask, DE4X5_IMR);
2463: load_ms_timer(dev, time_out);
2464:
2465: return;
2466: }
2467:
2468: static void disable_ast(struct device *dev)
2469: {
2470: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2471: u_long iobase = dev->base_addr;
2472:
2473: lp->irq_mask &= ~IMR_TMM;
2474: outl(lp->irq_mask, DE4X5_IMR);
2475: load_ms_timer(dev, 0);
2476:
2477: return;
2478: }
2479:
2480: static void kick_tx(struct device *dev)
2481: {
2482: struct sk_buff *skb;
2483:
2484: if ((skb = alloc_skb(0, GFP_ATOMIC)) != NULL) {
2485: skb->len= FAKE_FRAME_LEN;
2486: skb->arp=1;
2487: skb->dev=dev;
2488: dev_queue_xmit(skb, dev, SOPRI_NORMAL);
2489: }
2490:
2491: return;
2492: }
2493:
2494: /*
2495: ** Perform IOCTL call functions here. Some are privileged operations and the
2496: ** effective uid is checked in those cases.
2497: */
2498: static int de4x5_ioctl(struct device *dev, struct ifreq *rq, int cmd)
2499: {
2500: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2501: struct de4x5_ioctl *ioc = (struct de4x5_ioctl *) &rq->ifr_data;
2502: u_long iobase = dev->base_addr;
2503: int i, j, status = 0;
2504: s32 omr;
2505: union {
2506: u8 addr[(HASH_TABLE_LEN * ETH_ALEN)];
2507: u16 sval[(HASH_TABLE_LEN * ETH_ALEN) >> 1];
2508: u32 lval[(HASH_TABLE_LEN * ETH_ALEN) >> 2];
2509: } tmp;
2510:
2511: switch(ioc->cmd) {
2512: case DE4X5_GET_HWADDR: /* Get the hardware address */
2513: ioc->len = ETH_ALEN;
2514: status = verify_area(VERIFY_WRITE, (void *)ioc->data, ioc->len);
2515: if (status)
2516: break;
2517: for (i=0; i<ETH_ALEN; i++) {
2518: tmp.addr[i] = dev->dev_addr[i];
2519: }
2520: memcpy_tofs(ioc->data, tmp.addr, ioc->len);
2521:
2522: break;
2523: case DE4X5_SET_HWADDR: /* Set the hardware address */
2524: status = verify_area(VERIFY_READ, (void *)ioc->data, ETH_ALEN);
2525: if (status)
2526: break;
2527: status = -EPERM;
2528: if (!suser())
2529: break;
2530: status = 0;
2531: memcpy_fromfs(tmp.addr, ioc->data, ETH_ALEN);
2532: for (i=0; i<ETH_ALEN; i++) {
2533: dev->dev_addr[i] = tmp.addr[i];
2534: }
2535: build_setup_frame(dev, PHYS_ADDR_ONLY);
2536: /* Set up the descriptor and give ownership to the card */
2537: while (set_bit(0, (void *)&dev->tbusy) != 0);/* Wait for lock to free*/
2538: if (lp->setup_f == HASH_PERF) {
2539: load_packet(dev, lp->setup_frame, TD_IC | HASH_F | TD_SET |
2540: SETUP_FRAME_LEN, NULL);
2541: } else {
2542: load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
2543: SETUP_FRAME_LEN, NULL);
2544: }
2545: lp->tx_new = (++lp->tx_new) % lp->txRingSize;
2546: outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
2547: dev->tbusy = 0; /* Unlock the TX ring */
2548:
2549: break;
2550: case DE4X5_SET_PROM: /* Set Promiscuous Mode */
2551: if (suser()) {
2552: omr = inl(DE4X5_OMR);
2553: omr |= OMR_PR;
2554: outl(omr, DE4X5_OMR);
2555: } else {
2556: status = -EPERM;
2557: }
2558:
2559: break;
2560: case DE4X5_CLR_PROM: /* Clear Promiscuous Mode */
2561: if (suser()) {
2562: omr = inl(DE4X5_OMR);
2563: omr &= ~OMR_PR;
2564: outb(omr, DE4X5_OMR);
2565: } else {
2566: status = -EPERM;
2567: }
2568:
2569: break;
2570: case DE4X5_SAY_BOO: /* Say "Boo!" to the kernel log file */
2571: printk("%s: Boo!\n", dev->name);
2572:
2573: break;
2574: case DE4X5_GET_MCA: /* Get the multicast address table */
2575: ioc->len = (HASH_TABLE_LEN >> 3);
2576: status = verify_area(VERIFY_WRITE, ioc->data, ioc->len);
2577: if (status)
2578: break;
2579: memcpy_tofs(ioc->data, lp->setup_frame, ioc->len);
2580:
2581: break;
2582: case DE4X5_SET_MCA: /* Set a multicast address */
2583: if (suser()) {
2584: if (ioc->len != HASH_TABLE_LEN) { /* MCA changes */
2585: if (!(status = verify_area(VERIFY_READ, (void *)ioc->data, ETH_ALEN * ioc->len))) {
2586: memcpy_fromfs(tmp.addr, ioc->data, ETH_ALEN * ioc->len);
2587: set_multicast_list(dev);
2588: }
2589: } else {
2590: set_multicast_list(dev);
2591: }
2592: } else {
2593: status = -EPERM;
2594: }
2595:
2596: break;
2597: case DE4X5_CLR_MCA: /* Clear all multicast addresses */
2598: if (suser()) {
2599: set_multicast_list(dev);
2600: } else {
2601: status = -EPERM;
2602: }
2603:
2604: break;
2605: case DE4X5_MCA_EN: /* Enable pass all multicast addressing */
2606: if (suser()) {
2607: omr = inl(DE4X5_OMR);
2608: omr |= OMR_PM;
2609: outl(omr, DE4X5_OMR);
2610: } else {
2611: status = -EPERM;
2612: }
2613:
2614: break;
2615: case DE4X5_GET_STATS: /* Get the driver statistics */
2616: ioc->len = sizeof(lp->pktStats);
2617: status = verify_area(VERIFY_WRITE, (void *)ioc->data, ioc->len);
2618: if (status)
2619: break;
2620:
2621: cli();
2622: memcpy_tofs(ioc->data, &lp->pktStats, ioc->len);
2623: sti();
2624:
2625: break;
2626: case DE4X5_CLR_STATS: /* Zero out the driver statistics */
2627: if (suser()) {
2628: cli();
2629: memset(&lp->pktStats, 0, sizeof(lp->pktStats));
2630: sti();
2631: } else {
2632: status = -EPERM;
2633: }
2634:
2635: break;
2636: case DE4X5_GET_OMR: /* Get the OMR Register contents */
2637: tmp.addr[0] = inl(DE4X5_OMR);
2638: if (!(status = verify_area(VERIFY_WRITE, (void *)ioc->data, 1))) {
2639: memcpy_tofs(ioc->data, tmp.addr, 1);
2640: }
2641:
2642: break;
2643: case DE4X5_SET_OMR: /* Set the OMR Register contents */
2644: if (suser()) {
2645: if (!(status = verify_area(VERIFY_READ, (void *)ioc->data, 1))) {
2646: memcpy_fromfs(tmp.addr, ioc->data, 1);
2647: outl(tmp.addr[0], DE4X5_OMR);
2648: }
2649: } else {
2650: status = -EPERM;
2651: }
2652:
2653: break;
2654: case DE4X5_GET_REG: /* Get the DE4X5 Registers */
2655: j = 0;
2656: tmp.lval[0] = inl(DE4X5_STS); j+=4;
2657: tmp.lval[1] = inl(DE4X5_BMR); j+=4;
2658: tmp.lval[2] = inl(DE4X5_IMR); j+=4;
2659: tmp.lval[3] = inl(DE4X5_OMR); j+=4;
2660: tmp.lval[4] = inl(DE4X5_SISR); j+=4;
2661: tmp.lval[5] = inl(DE4X5_SICR); j+=4;
2662: tmp.lval[6] = inl(DE4X5_STRR); j+=4;
2663: tmp.lval[7] = inl(DE4X5_SIGR); j+=4;
2664: ioc->len = j;
2665: if (!(status = verify_area(VERIFY_WRITE, (void *)ioc->data, ioc->len))) {
2666: memcpy_tofs(ioc->data, tmp.addr, ioc->len);
2667: }
2668: break;
2669:
2670: #define DE4X5_DUMP 0x0f /* Dump the DE4X5 Status */
2671:
2672: case DE4X5_DUMP:
2673: j = 0;
2674: tmp.addr[j++] = dev->irq;
2675: for (i=0; i<ETH_ALEN; i++) {
2676: tmp.addr[j++] = dev->dev_addr[i];
2677: }
2678: tmp.addr[j++] = lp->rxRingSize;
2679: tmp.lval[j>>2] = (long)lp->rx_ring; j+=4;
2680: tmp.lval[j>>2] = (long)lp->tx_ring; j+=4;
2681:
2682: for (i=0;i<lp->rxRingSize-1;i++){
2683: if (i < 3) {
2684: tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
2685: }
2686: }
2687: tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
2688: for (i=0;i<lp->txRingSize-1;i++){
2689: if (i < 3) {
2690: tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
2691: }
2692: }
2693: tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
2694:
2695: for (i=0;i<lp->rxRingSize-1;i++){
2696: if (i < 3) {
2697: tmp.lval[j>>2] = (s32)lp->rx_ring[i].buf; j+=4;
2698: }
2699: }
2700: tmp.lval[j>>2] = (s32)lp->rx_ring[i].buf; j+=4;
2701: for (i=0;i<lp->txRingSize-1;i++){
2702: if (i < 3) {
2703: tmp.lval[j>>2] = (s32)lp->tx_ring[i].buf; j+=4;
2704: }
2705: }
2706: tmp.lval[j>>2] = (s32)lp->tx_ring[i].buf; j+=4;
2707:
2708: for (i=0;i<lp->rxRingSize;i++){
2709: tmp.lval[j>>2] = lp->rx_ring[i].status; j+=4;
2710: }
2711: for (i=0;i<lp->txRingSize;i++){
2712: tmp.lval[j>>2] = lp->tx_ring[i].status; j+=4;
2713: }
2714:
2715: tmp.lval[j>>2] = inl(DE4X5_STS); j+=4;
2716: tmp.lval[j>>2] = inl(DE4X5_BMR); j+=4;
2717: tmp.lval[j>>2] = inl(DE4X5_IMR); j+=4;
2718: tmp.lval[j>>2] = inl(DE4X5_OMR); j+=4;
2719: tmp.lval[j>>2] = inl(DE4X5_SISR); j+=4;
2720: tmp.lval[j>>2] = inl(DE4X5_SICR); j+=4;
2721: tmp.lval[j>>2] = inl(DE4X5_STRR); j+=4;
2722: tmp.lval[j>>2] = inl(DE4X5_SIGR); j+=4;
2723:
2724: tmp.addr[j++] = lp->txRingSize;
2725: tmp.addr[j++] = dev->tbusy;
2726:
2727: ioc->len = j;
2728: if (!(status = verify_area(VERIFY_WRITE, (void *)ioc->data, ioc->len))) {
2729: memcpy_tofs(ioc->data, tmp.addr, ioc->len);
2730: }
2731:
2732: break;
2733: default:
2734: status = -EOPNOTSUPP;
2735: }
2736:
2737: return status;
2738: }
2739:
2740: #ifdef MODULE
2741: static char devicename[9] = { 0, };
2742: static struct device thisDE4X5 = {
2743: devicename, /* device name is inserted by linux/drivers/net/net_init.c */
2744: 0, 0, 0, 0,
2745: 0x2000, 10, /* I/O address, IRQ */
2746: 0, 0, 0, NULL, de4x5_probe };
2747:
2748: static int io=0x000b; /* EDIT THESE LINES FOR YOUR CONFIGURATION */
2749: static int irq=10; /* or use the insmod io= irq= options */
2750:
2751: int
2752: init_module(void)
2753: {
2754: thisDE4X5.base_addr=io;
2755: thisDE4X5.irq=irq;
2756: if (register_netdev(&thisDE4X5) != 0)
2757: return -EIO;
2758: return 0;
2759: }
2760:
2761: void
2762: cleanup_module(void)
2763: {
2764: struct de4x5_private *lp = (struct de4x5_private *) thisDE4X5.priv;
2765:
2766: if (lp) {
2767: kfree_s(bus_to_virt(lp->rx_ring[0].buf), RX_BUFF_SZ * NUM_RX_DESC + ALIGN);
2768: }
2769: kfree_s(thisDE4X5.priv, sizeof(struct de4x5_private) + ALIGN);
2770: thisDE4X5.priv = NULL;
2771:
2772: release_region(thisDE4X5.base_addr, (lp->bus == PCI ?
2773: DE4X5_PCI_TOTAL_SIZE :
2774: DE4X5_EISA_TOTAL_SIZE));
2775: unregister_netdev(&thisDE4X5);
2776: }
2777: #endif /* MODULE */
2778:
2779:
2780: /*
2781: * Local variables:
2782: * kernel-compile-command: "gcc -D__KERNEL__ -I/usr/src/linux/net/inet -Wall -Wstrict-prototypes -O2 -m486 -c de4x5.c"
2783: *
2784: * module-compile-command: "gcc -D__KERNEL__ -DMODULE -I/usr/src/linux/net/inet -Wall -Wstrict-prototypes -O2 -m486 -c de4x5.c"
2785: * End:
2786: */
2787:
2788:
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