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1.1 ! root 1: /* AM53/79C974 (PCscsi) driver release 0.5 ! 2: * ! 3: * The architecture and much of the code of this device ! 4: * driver was originally developed by Drew Eckhardt for ! 5: * the NCR5380. The following copyrights apply: ! 6: * For the architecture and all parts similar to the NCR5380: ! 7: * Copyright 1993, Drew Eckhardt ! 8: * Visionary Computing ! 9: * (Unix and Linux consulting and custom programming) ! 10: * [email protected] ! 11: * +1 (303) 666-5836 ! 12: * ! 13: * The AM53C974_nobios_detect code was origininally developed by ! 14: * Robin Cutshaw ([email protected]) and is used here in a ! 15: * modified form. ! 16: * ! 17: * For the other parts: ! 18: * Copyright 1994, D. Frieauff ! 19: * EMail: [email protected] ! 20: * Phone: x49-7545-8-2256 , x49-7541-42305 ! 21: */ ! 22: ! 23: /* ! 24: * $Log: AM53C974.h,v $ ! 25: * Revision 1.1.1.1 1997/02/25 21:27:44 thomas ! 26: * Initial source ! 27: * ! 28: * Revision 1.1.1.1 1996/10/30 01:39:58 thomas ! 29: * Imported from UK22 ! 30: * ! 31: * Revision 1.1 1996/03/25 20:25:06 goel ! 32: * Linux driver merge. ! 33: * ! 34: */ ! 35: ! 36: #ifndef AM53C974_H ! 37: #define AM53C974_H ! 38: ! 39: #include <linux/scsicam.h> ! 40: ! 41: /*************************************************************************************** ! 42: * Default setting of the controller's SCSI id. Edit and uncomment this only if your * ! 43: * BIOS does not correctly initialize the controller's SCSI id. * ! 44: * If you don't get a warning during boot, it is correctly initialized. * ! 45: ****************************************************************************************/ ! 46: /* #define AM53C974_SCSI_ID 7 */ ! 47: ! 48: /*************************************************************************************** ! 49: * Default settings for sync. negotiation enable, transfer rate and sync. offset. * ! 50: * These settings can be replaced by LILO overrides (append) with the following syntax: * ! 51: * AM53C974=host-scsi-id, target-scsi-id, max-rate, max-offset * ! 52: * Sync. negotiation is disabled by default and will be enabled for those targets which * ! 53: * are specified in the LILO override * ! 54: ****************************************************************************************/ ! 55: #define DEFAULT_SYNC_NEGOTIATION_ENABLED 0 /* 0 or 1 */ ! 56: #define DEFAULT_RATE 5 /* MHz, min: 3; max: 10 */ ! 57: #define DEFAULT_SYNC_OFFSET 0 /* bytes, min: 0; max: 15; use 0 for async. mode */ ! 58: ! 59: ! 60: /* --------------------- don't edit below here --------------------- */ ! 61: ! 62: #define AM53C974_DRIVER_REVISION_MAJOR 0 ! 63: #define AM53C974_DRIVER_REVISION_MINOR 5 ! 64: #define SEPARATOR_LINE \ ! 65: "--------------------------------------------------------------------------\n" ! 66: ! 67: /* debug control */ ! 68: /* #define AM53C974_DEBUG */ ! 69: /* #define AM53C974_DEBUG_MSG */ ! 70: /* #define AM53C974_DEBUG_KEYWAIT */ ! 71: /* #define AM53C974_DEBUG_INIT */ ! 72: /* #define AM53C974_DEBUG_QUEUE */ ! 73: /* #define AM53C974_DEBUG_INFO */ ! 74: /* #define AM53C974_DEBUG_LINKED */ ! 75: /* #define VERBOSE_AM53C974_DEBUG */ ! 76: /* #define AM53C974_DEBUG_INTR */ ! 77: /* #define AM53C974_DEB_RESEL */ ! 78: #define AM53C974_DEBUG_ABORT ! 79: /* #define AM53C974_OPTION_DEBUG_PROBE_ONLY */ ! 80: ! 81: /* special options/constants */ ! 82: #define DEF_CLK 40 /* chip clock freq. in MHz */ ! 83: #define MIN_PERIOD 4 /* for negotiation: min. number of clocks per cycle */ ! 84: #define MAX_PERIOD 13 /* for negotiation: max. number of clocks per cycle */ ! 85: #define MAX_OFFSET 15 /* for negotiation: max. offset (0=async) */ ! 86: ! 87: #define DEF_SCSI_TIMEOUT 245 /* STIMREG value, 40 Mhz */ ! 88: #define DEF_STP 8 /* STPREG value assuming 5.0 MB/sec, FASTCLK, FASTSCSI */ ! 89: #define DEF_SOF_RAD 0 /* REQ/ACK deassertion delay */ ! 90: #define DEF_SOF_RAA 0 /* REQ/ACK assertion delay */ ! 91: #define DEF_ETM 0 /* CNTLREG1, ext. timing mode */ ! 92: #define DEF_PERE 1 /* CNTLREG1, parity error reporting */ ! 93: #define DEF_CLKF 0 /* CLKFREG, 0=40 Mhz */ ! 94: #define DEF_ENF 1 /* CNTLREG2, enable features */ ! 95: #define DEF_ADIDCHK 0 /* CNTLREG3, additional ID check */ ! 96: #define DEF_FASTSCSI 1 /* CNTLREG3, fast SCSI */ ! 97: #define DEF_FASTCLK 1 /* CNTLREG3, fast clocking, 5 MB/sec at 40MHz chip clk */ ! 98: #define DEF_GLITCH 1 /* CNTLREG4, glitch eater, 0=12ns, 1=35ns, 2=25ns, 3=off */ ! 99: #define DEF_PWD 0 /* CNTLREG4, reduced power feature */ ! 100: #define DEF_RAE 0 /* CNTLREG4, RAE active negation on REQ, ACK only */ ! 101: #define DEF_RADE 1 /* 1CNTLREG4, active negation on REQ, ACK and data */ ! 102: ! 103: /*** PCI block ***/ ! 104: /* standard registers are defined in <linux/pci.h> */ ! 105: #ifndef PCI_VENDOR_ID_AMD ! 106: #define PCI_VENDOR_ID_AMD 0x1022 ! 107: #define PCI_DEVICE_ID_AMD_SCSI 0x2020 ! 108: #endif ! 109: #define PCI_BASE_MASK 0xFFFFFFE0 ! 110: #define PCI_COMMAND_PERREN 0x40 ! 111: #define PCI_SCRATCH_REG_0 0x40 /* 16 bits */ ! 112: #define PCI_SCRATCH_REG_1 0x42 /* 16 bits */ ! 113: #define PCI_SCRATCH_REG_2 0x44 /* 16 bits */ ! 114: #define PCI_SCRATCH_REG_3 0x46 /* 16 bits */ ! 115: #define PCI_SCRATCH_REG_4 0x48 /* 16 bits */ ! 116: #define PCI_SCRATCH_REG_5 0x4A /* 16 bits */ ! 117: #define PCI_SCRATCH_REG_6 0x4C /* 16 bits */ ! 118: #define PCI_SCRATCH_REG_7 0x4E /* 16 bits */ ! 119: ! 120: /*** SCSI block ***/ ! 121: #define CTCLREG 0x00 /* r current transf. count, low byte */ ! 122: #define CTCMREG 0x04 /* r current transf. count, middle byte */ ! 123: #define CTCHREG 0x38 /* r current transf. count, high byte */ ! 124: #define STCLREG 0x00 /* w start transf. count, low byte */ ! 125: #define STCMREG 0x04 /* w start transf. count, middle byte */ ! 126: #define STCHREG 0x38 /* w start transf. count, high byte */ ! 127: #define FFREG 0x08 /* rw SCSI FIFO reg. */ ! 128: #define STIMREG 0x14 /* w SCSI timeout reg. */ ! 129: ! 130: #define SDIDREG 0x10 /* w SCSI destination ID reg. */ ! 131: #define SDIREG_MASK 0x07 /* mask */ ! 132: ! 133: #define STPREG 0x18 /* w synchronous transf. period reg. */ ! 134: #define STPREG_STP 0x1F /* synchr. transfer period */ ! 135: ! 136: #define CLKFREG 0x24 /* w clock factor reg. */ ! 137: #define CLKFREG_MASK 0x07 /* mask */ ! 138: ! 139: #define CMDREG 0x0C /* rw SCSI command reg. */ ! 140: #define CMDREG_DMA 0x80 /* set DMA mode (set together with opcodes below) */ ! 141: #define CMDREG_IT 0x10 /* information transfer */ ! 142: #define CMDREG_ICCS 0x11 /* initiator command complete steps */ ! 143: #define CMDREG_MA 0x12 /* message accepted */ ! 144: #define CMDREG_TPB 0x98 /* transfer pad bytes, DMA mode only */ ! 145: #define CMDREG_SATN 0x1A /* set ATN */ ! 146: #define CMDREG_RATN 0x1B /* reset ATN */ ! 147: #define CMDREG_SOAS 0x41 /* select without ATN steps */ ! 148: #define CMDREG_SAS 0x42 /* select with ATN steps (1 msg byte) */ ! 149: #define CMDREG_SASS 0x43 /* select with ATN and stop steps */ ! 150: #define CMDREG_ESR 0x44 /* enable selection/reselection */ ! 151: #define CMDREG_DSR 0x45 /* disable selection/reselection */ ! 152: #define CMDREG_SA3S 0x46 /* select with ATN 3 steps (3 msg bytes) */ ! 153: #define CMDREG_NOP 0x00 /* no operation */ ! 154: #define CMDREG_CFIFO 0x01 /* clear FIFO */ ! 155: #define CMDREG_RDEV 0x02 /* reset device */ ! 156: #define CMDREG_RBUS 0x03 /* reset SCSI bus */ ! 157: ! 158: #define STATREG 0x10 /* r SCSI status reg. */ ! 159: #define STATREG_INT 0x80 /* SCSI interrupt condition detected */ ! 160: #define STATREG_IOE 0x40 /* SCSI illegal operation error detected */ ! 161: #define STATREG_PE 0x20 /* SCSI parity error detected */ ! 162: #define STATREG_CTZ 0x10 /* CTC reg decremented to zero */ ! 163: #define STATREG_MSG 0x04 /* SCSI MSG phase (latched?) */ ! 164: #define STATREG_CD 0x02 /* SCSI C/D phase (latched?) */ ! 165: #define STATREG_IO 0x01 /* SCSI I/O phase (latched?) */ ! 166: #define STATREG_PHASE 0x07 /* SCSI phase mask */ ! 167: ! 168: #define INSTREG 0x14 /* r interrupt status reg. */ ! 169: #define INSTREG_SRST 0x80 /* SCSI reset detected */ ! 170: #define INSTREG_ICMD 0x40 /* SCSI invalid command detected */ ! 171: #define INSTREG_DIS 0x20 /* target disconnected or sel/resel timeout*/ ! 172: #define INSTREG_SR 0x10 /* device on bus has service request */ ! 173: #define INSTREG_SO 0x08 /* successful operation */ ! 174: #define INSTREG_RESEL 0x04 /* device reselected as initiator */ ! 175: ! 176: #define ISREG 0x18 /* r internal state reg. */ ! 177: #define ISREG_SOF 0x08 /* synchronous offset flag (act. low) */ ! 178: #define ISREG_IS 0x07 /* status of intermediate op. */ ! 179: #define ISREG_OK_NO_STOP 0x04 /* selection successful */ ! 180: #define ISREG_OK_STOP 0x01 /* selection successful */ ! 181: ! 182: #define CFIREG 0x1C /* r current FIFO/internal state reg. */ ! 183: #define CFIREG_IS 0xE0 /* status of intermediate op. */ ! 184: #define CFIREG_CF 0x1F /* number of bytes in SCSI FIFO */ ! 185: ! 186: #define SOFREG 0x1C /* w synchr. offset reg. */ ! 187: #define SOFREG_RAD 0xC0 /* REQ/ACK deassertion delay (sync.) */ ! 188: #define SOFREG_RAA 0x30 /* REQ/ACK assertion delay (sync.) */ ! 189: #define SOFREG_SO 0x0F /* synch. offset (sync.) */ ! 190: ! 191: #define CNTLREG1 0x20 /* rw control register one */ ! 192: #define CNTLREG1_ETM 0x80 /* set extended timing mode */ ! 193: #define CNTLREG1_DISR 0x40 /* disable interrupt on SCSI reset */ ! 194: #define CNTLREG1_PERE 0x10 /* enable parity error reporting */ ! 195: #define CNTLREG1_SID 0x07 /* host adapter SCSI ID */ ! 196: ! 197: #define CNTLREG2 0x2C /* rw control register two */ ! 198: #define CNTLREG2_ENF 0x40 /* enable features */ ! 199: ! 200: #define CNTLREG3 0x30 /* rw control register three */ ! 201: #define CNTLREG3_ADIDCHK 0x80 /* additional ID check */ ! 202: #define CNTLREG3_FASTSCSI 0x10 /* fast SCSI */ ! 203: #define CNTLREG3_FASTCLK 0x08 /* fast SCSI clocking */ ! 204: ! 205: #define CNTLREG4 0x34 /* rw control register four */ ! 206: #define CNTLREG4_GLITCH 0xC0 /* glitch eater */ ! 207: #define CNTLREG4_PWD 0x20 /* reduced power feature */ ! 208: #define CNTLREG4_RAE 0x08 /* write only, active negot. ctrl. */ ! 209: #define CNTLREG4_RADE 0x04 /* active negot. ctrl. */ ! 210: #define CNTLREG4_RES 0x10 /* reserved bit, must be 1 */ ! 211: ! 212: /*** DMA block ***/ ! 213: #define DMACMD 0x40 /* rw command */ ! 214: #define DMACMD_DIR 0x80 /* transfer direction (1=read from device) */ ! 215: #define DMACMD_INTE_D 0x40 /* DMA transfer interrupt enable */ ! 216: #define DMACMD_INTE_P 0x20 /* page transfer interrupt enable */ ! 217: #define DMACMD_MDL 0x10 /* map to memory descriptor list */ ! 218: #define DMACMD_DIAG 0x04 /* diagnostics, set to 0 */ ! 219: #define DMACMD_IDLE 0x00 /* idle cmd */ ! 220: #define DMACMD_BLAST 0x01 /* flush FIFO to memory */ ! 221: #define DMACMD_ABORT 0x02 /* terminate DMA */ ! 222: #define DMACMD_START 0x03 /* start DMA */ ! 223: ! 224: #define DMASTATUS 0x54 /* r status register */ ! 225: #define DMASTATUS_BCMPLT 0x20 /* BLAST complete */ ! 226: #define DMASTATUS_SCSIINT 0x10 /* SCSI interrupt pending */ ! 227: #define DMASTATUS_DONE 0x08 /* DMA transfer terminated */ ! 228: #define DMASTATUS_ABORT 0x04 /* DMA transfer aborted */ ! 229: #define DMASTATUS_ERROR 0x02 /* DMA transfer error */ ! 230: #define DMASTATUS_PWDN 0x02 /* power down indicator */ ! 231: ! 232: #define DMASTC 0x44 /* rw starting transfer count */ ! 233: #define DMASPA 0x48 /* rw starting physical address */ ! 234: #define DMAWBC 0x4C /* r working byte counter */ ! 235: #define DMAWAC 0x50 /* r working address counter */ ! 236: #define DMASMDLA 0x58 /* rw starting MDL address */ ! 237: #define DMAWMAC 0x5C /* r working MDL counter */ ! 238: ! 239: /*** SCSI phases ***/ ! 240: #define PHASE_MSGIN 0x07 ! 241: #define PHASE_MSGOUT 0x06 ! 242: #define PHASE_RES_1 0x05 ! 243: #define PHASE_RES_0 0x04 ! 244: #define PHASE_STATIN 0x03 ! 245: #define PHASE_CMDOUT 0x02 ! 246: #define PHASE_DATAIN 0x01 ! 247: #define PHASE_DATAOUT 0x00 ! 248: ! 249: struct AM53C974_hostdata { ! 250: volatile unsigned in_reset:1; /* flag, says bus reset pending */ ! 251: volatile unsigned aborted:1; /* flag, says aborted */ ! 252: volatile unsigned selecting:1; /* selection started, but not yet finished */ ! 253: volatile unsigned disconnecting: 1; /* disconnection started, but not yet finished */ ! 254: volatile unsigned dma_busy:1; /* dma busy when service request for info transfer received */ ! 255: volatile unsigned char msgout[10]; /* message to output in MSGOUT_PHASE */ ! 256: volatile unsigned char last_message[10]; /* last message OUT */ ! 257: volatile Scsi_Cmnd *issue_queue; /* waiting to be issued */ ! 258: volatile Scsi_Cmnd *disconnected_queue; /* waiting for reconnect */ ! 259: volatile Scsi_Cmnd *sel_cmd; /* command for selection */ ! 260: volatile Scsi_Cmnd *connected; /* currently connected command */ ! 261: volatile unsigned char busy[8]; /* index = target, bit = lun */ ! 262: unsigned char sync_per[8]; /* synchronous transfer period (in effect) */ ! 263: unsigned char sync_off[8]; /* synchronous offset (in effect) */ ! 264: unsigned char sync_neg[8]; /* sync. negotiation performed (in effect) */ ! 265: unsigned char sync_en[8]; /* sync. negotiation performed (in effect) */ ! 266: unsigned char max_rate[8]; /* max. transfer rate (setup) */ ! 267: unsigned char max_offset[8]; /* max. sync. offset (setup), only valid if corresponding sync_en is nonzero */ ! 268: }; ! 269: ! 270: #define AM53C974 { \ ! 271: NULL, /* pointer to next in list */ \ ! 272: NULL, /* long * usage_count */ \ ! 273: NULL, /* struct proc_dir_entry *proc_dir */ \ ! 274: NULL, /* int (*proc_info)(char *, char **, off_t, int, int, int); */ \ ! 275: "AM53C974", /* name */ \ ! 276: AM53C974_detect, /* int (* detect)(struct SHT *) */ \ ! 277: NULL, /* int (*release)(struct Scsi_Host *) */ \ ! 278: AM53C974_info, /* const char *(* info)(struct Scsi_Host *) */ \ ! 279: AM53C974_command, /* int (* command)(Scsi_Cmnd *) */ \ ! 280: AM53C974_queue_command, /* int (* queuecommand)(Scsi_Cmnd *, \ ! 281: void (*done)(Scsi_Cmnd *)) */ \ ! 282: AM53C974_abort, /* int (* abort)(Scsi_Cmnd *) */ \ ! 283: AM53C974_reset, /* int (* reset)(Scsi_Cmnd *) */ \ ! 284: NULL, /* int (* slave_attach)(int, int) */ \ ! 285: scsicam_bios_param, /* int (* bios_param)(Disk *, int, int[]) */ \ ! 286: 12, /* can_queue */ \ ! 287: -1, /* this_id */ \ ! 288: SG_ALL, /* sg_tablesize */ \ ! 289: 1, /* cmd_per_lun */ \ ! 290: 0, /* present, i.e. how many adapters of this kind */ \ ! 291: 0, /* unchecked_isa_dma */ \ ! 292: DISABLE_CLUSTERING /* use_clustering */ \ ! 293: } ! 294: ! 295: void AM53C974_setup(char *str, int *ints); ! 296: int AM53C974_detect(Scsi_Host_Template *tpnt); ! 297: int AM53C974_biosparm(Disk *disk, int dev, int *info_array); ! 298: const char *AM53C974_info(struct Scsi_Host *); ! 299: int AM53C974_command(Scsi_Cmnd *SCpnt); ! 300: int AM53C974_queue_command(Scsi_Cmnd *cmd, void (*done)(Scsi_Cmnd *)); ! 301: int AM53C974_abort(Scsi_Cmnd *cmd); ! 302: int AM53C974_reset (Scsi_Cmnd *cmd); ! 303: ! 304: #define AM53C974_local_declare() unsigned long io_port ! 305: #define AM53C974_setio(instance) io_port = instance->io_port ! 306: #define AM53C974_read_8(addr) inb(io_port + (addr)) ! 307: #define AM53C974_write_8(addr,x) outb((x), io_port + (addr)) ! 308: #define AM53C974_read_16(addr) inw(io_port + (addr)) ! 309: #define AM53C974_write_16(addr,x) outw((x), io_port + (addr)) ! 310: #define AM53C974_read_32(addr) inl(io_port + (addr)) ! 311: #define AM53C974_write_32(addr,x) outl((x), io_port + (addr)) ! 312: ! 313: #define AM53C974_poll_int() { do { statreg = AM53C974_read_8(STATREG); } \ ! 314: while (!(statreg & STATREG_INT)) ; \ ! 315: AM53C974_read_8(INSTREG) ; } /* clear int */ ! 316: #define AM53C974_cfifo() (AM53C974_read_8(CFIREG) & CFIREG_CF) ! 317: ! 318: /* These are "special" values for the tag parameter passed to AM53C974_select. */ ! 319: #define TAG_NEXT -1 /* Use next free tag */ ! 320: #define TAG_NONE -2 /* Establish I_T_L nexus instead of I_T_L_Q ! 321: * even on SCSI-II devices */ ! 322: ! 323: /************ LILO overrides *************/ ! 324: typedef struct _override_t { ! 325: int host_scsi_id; /* SCSI id of the bus controller */ ! 326: int target_scsi_id; /* SCSI id of target */ ! 327: int max_rate; /* max. transfer rate */ ! 328: int max_offset; /* max. sync. offset, 0 = asynchronous */ ! 329: } override_t; ! 330: ! 331: /************ PCI stuff *************/ ! 332: #define AM53C974_PCIREG_OPEN() outb(0xF1, 0xCF8); outb(0, 0xCFA) ! 333: #define AM53C974_PCIREG_CLOSE() outb(0, 0xCF8) ! 334: #define AM53C974_PCIREG_READ_BYTE(instance,a) ( inb((a) + (instance)->io_port) ) ! 335: #define AM53C974_PCIREG_READ_WORD(instance,a) ( inw((a) + (instance)->io_port) ) ! 336: #define AM53C974_PCIREG_READ_DWORD(instance,a) ( inl((a) + (instance)->io_port) ) ! 337: #define AM53C974_PCIREG_WRITE_BYTE(instance,x,a) ( outb((x), (a) + (instance)->io_port) ) ! 338: #define AM53C974_PCIREG_WRITE_WORD(instance,x,a) ( outw((x), (a) + (instance)->io_port) ) ! 339: #define AM53C974_PCIREG_WRITE_DWORD(instance,x,a) ( outl((x), (a) + (instance)->io_port) ) ! 340: ! 341: typedef struct _pci_config_t { ! 342: /* start of official PCI config space header */ ! 343: union { ! 344: unsigned int device_vendor; ! 345: struct { ! 346: unsigned short vendor; ! 347: unsigned short device; ! 348: } dv; ! 349: } dv_id; ! 350: #define _device_vendor dv_id.device_vendor ! 351: #define _vendor dv_id.dv.vendor ! 352: #define _device dv_id.dv.device ! 353: union { ! 354: unsigned int status_command; ! 355: struct { ! 356: unsigned short command; ! 357: unsigned short status; ! 358: } sc; ! 359: } stat_cmd; ! 360: #define _status_command stat_cmd.status_command ! 361: #define _command stat_cmd.sc.command ! 362: #define _status stat_cmd.sc.status ! 363: union { ! 364: unsigned int class_revision; ! 365: struct { ! 366: unsigned char rev_id; ! 367: unsigned char prog_if; ! 368: unsigned char sub_class; ! 369: unsigned char base_class; ! 370: } cr; ! 371: } class_rev; ! 372: #define _class_revision class_rev.class_revision ! 373: #define _rev_id class_rev.cr.rev_id ! 374: #define _prog_if class_rev.cr.prog_if ! 375: #define _sub_class class_rev.cr.sub_class ! 376: #define _base_class class_rev.cr.base_class ! 377: union { ! 378: unsigned int bist_header_latency_cache; ! 379: struct { ! 380: unsigned char cache_line_size; ! 381: unsigned char latency_timer; ! 382: unsigned char header_type; ! 383: unsigned char bist; ! 384: } bhlc; ! 385: } bhlc; ! 386: #define _bist_header_latency_cache bhlc.bist_header_latency_cache ! 387: #define _cache_line_size bhlc.bhlc.cache_line_size ! 388: #define _latency_timer bhlc.bhlc.latency_timer ! 389: #define _header_type bhlc.bhlc.header_type ! 390: #define _bist bhlc.bhlc.bist ! 391: unsigned int _base0; ! 392: unsigned int _base1; ! 393: unsigned int _base2; ! 394: unsigned int _base3; ! 395: unsigned int _base4; ! 396: unsigned int _base5; ! 397: unsigned int rsvd1; ! 398: unsigned int rsvd2; ! 399: unsigned int _baserom; ! 400: unsigned int rsvd3; ! 401: unsigned int rsvd4; ! 402: union { ! 403: unsigned int max_min_ipin_iline; ! 404: struct { ! 405: unsigned char int_line; ! 406: unsigned char int_pin; ! 407: unsigned char min_gnt; ! 408: unsigned char max_lat; ! 409: } mmii; ! 410: } mmii; ! 411: #define _max_min_ipin_iline mmii.max_min_ipin_iline ! 412: #define _int_line mmii.mmii.int_line ! 413: #define _int_pin mmii.mmii.int_pin ! 414: #define _min_gnt mmii.mmii.min_gnt ! 415: #define _max_lat mmii.mmii.max_lat ! 416: /* end of official PCI config space header */ ! 417: unsigned short _ioaddr; /* config type 1 - private I/O addr */ ! 418: unsigned int _pcibus; /* config type 2 - private bus id */ ! 419: unsigned int _cardnum; /* config type 2 - private card number */ ! 420: } pci_config_t; ! 421: ! 422: #endif /* AM53C974_H */
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