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Annotation of Gnu-Mach/i386/i386at/gpl/linux/scsi/NCR5380.h, revision 1.1

1.1     ! root        1: /* 
        !             2:  * NCR 5380 defines
        !             3:  *
        !             4:  * Copyright 1993, Drew Eckhardt
        !             5:  *     Visionary Computing
        !             6:  *     (Unix consulting and custom programming)
        !             7:  *     [email protected]
        !             8:  *      +1 (303) 666-5836
        !             9:  *
        !            10:  * DISTRIBUTION RELEASE 6
        !            11:  *
        !            12:  * For more information, please consult 
        !            13:  *
        !            14:  * NCR 5380 Family
        !            15:  * SCSI Protocol Controller
        !            16:  * Databook
        !            17:  * NCR Microelectronics
        !            18:  * 1635 Aeroplaza Drive
        !            19:  * Colorado Springs, CO 80916
        !            20:  * 1+ (719) 578-3400
        !            21:  * 1+ (800) 334-5454
        !            22:  */
        !            23: 
        !            24: /*
        !            25:  * $Log: NCR5380.h,v $
        !            26:  * Revision 1.1.1.1  1997/02/25 21:27:44  thomas
        !            27:  * Initial source
        !            28:  *
        !            29:  * Revision 1.1.1.1  1996/10/30 01:39:59  thomas
        !            30:  * Imported from UK22
        !            31:  *
        !            32:  * Revision 1.1  1996/03/25  20:25:09  goel
        !            33:  * Linux driver merge.
        !            34:  *
        !            35:  */
        !            36: 
        !            37: #ifndef NCR5380_H
        !            38: #define NCR5380_H
        !            39: 
        !            40: #define NCR5380_PUBLIC_RELEASE 6
        !            41: #define NCR53C400_PUBLIC_RELEASE 2
        !            42: 
        !            43: #define NDEBUG_ARBITRATION     0x1
        !            44: #define NDEBUG_AUTOSENSE       0x2
        !            45: #define NDEBUG_DMA             0x4
        !            46: #define NDEBUG_HANDSHAKE       0x8
        !            47: #define NDEBUG_INFORMATION     0x10
        !            48: #define NDEBUG_INIT            0x20
        !            49: #define NDEBUG_INTR            0x40
        !            50: #define NDEBUG_LINKED          0x80
        !            51: #define NDEBUG_MAIN            0x100
        !            52: #define NDEBUG_NO_DATAOUT      0x200
        !            53: #define NDEBUG_NO_WRITE                0x400
        !            54: #define NDEBUG_PIO             0x800
        !            55: #define NDEBUG_PSEUDO_DMA      0x1000
        !            56: #define NDEBUG_QUEUES          0x2000
        !            57: #define NDEBUG_RESELECTION     0x4000
        !            58: #define NDEBUG_SELECTION       0x8000
        !            59: #define NDEBUG_USLEEP          0x10000
        !            60: #define NDEBUG_LAST_BYTE_SENT  0x20000
        !            61: #define NDEBUG_RESTART_SELECT  0x40000
        !            62: #define NDEBUG_EXTENDED                0x80000
        !            63: #define NDEBUG_C400_PREAD      0x100000
        !            64: #define NDEBUG_C400_PWRITE     0x200000
        !            65: #define NDEBUG_LISTS           0x400000
        !            66: 
        !            67: /* 
        !            68:  * The contents of the OUTPUT DATA register are asserted on the bus when
        !            69:  * either arbitration is occurring or the phase-indicating signals (
        !            70:  * IO, CD, MSG) in the TARGET COMMAND register and the ASSERT DATA
        !            71:  * bit in the INITIATOR COMMAND register is set.
        !            72:  */
        !            73: 
        !            74: #define OUTPUT_DATA_REG         0       /* wo DATA lines on SCSI bus */
        !            75: #define CURRENT_SCSI_DATA_REG   0       /* ro same */
        !            76: 
        !            77: #define INITIATOR_COMMAND_REG  1       /* rw */
        !            78: #define ICR_ASSERT_RST         0x80    /* rw Set to assert RST  */
        !            79: #define ICR_ARBITRATION_PROGRESS 0x40  /* ro Indicates arbitration complete */
        !            80: #define ICR_TRI_STATE          0x40    /* wo Set to tri-state drivers */
        !            81: #define ICR_ARBITRATION_LOST   0x20    /* ro Indicates arbitration lost */
        !            82: #define ICR_DIFF_ENABLE                0x20    /* wo Set to enable diff. drivers */
        !            83: #define ICR_ASSERT_ACK         0x10    /* rw ini Set to assert ACK */
        !            84: #define ICR_ASSERT_BSY         0x08    /* rw Set to assert BSY */
        !            85: #define ICR_ASSERT_SEL                 0x04    /* rw Set to assert SEL */
        !            86: #define ICR_ASSERT_ATN         0x02    /* rw Set to assert ATN */
        !            87: #define ICR_ASSERT_DATA                0x01    /* rw SCSI_DATA_REG is asserted */
        !            88: 
        !            89: #ifdef DIFFERENTIAL
        !            90: #define ICR_BASE               ICR_DIFF_ENABLE
        !            91: #else
        !            92: #define ICR_BASE               0
        !            93: #endif
        !            94: 
        !            95: #define MODE_REG               2
        !            96: /*
        !            97:  * Note : BLOCK_DMA code will keep DRQ asserted for the duration of the 
        !            98:  * transfer, causing the chip to hog the bus.  You probably don't want 
        !            99:  * this.
        !           100:  */
        !           101: #define MR_BLOCK_DMA_MODE      0x80    /* rw block mode DMA */
        !           102: #define MR_TARGET              0x40    /* rw target mode */
        !           103: #define MR_ENABLE_PAR_CHECK   0x20     /* rw enable parity checking */
        !           104: #define MR_ENABLE_PAR_INTR     0x10    /* rw enable bad parity interrupt */
        !           105: #define MR_ENABLE_EOP_INTR     0x08    /* rw enable eop interrupt */
        !           106: #define MR_MONITOR_BSY 0x04    /* rw enable int on unexpected bsy fail */
        !           107: #define MR_DMA_MODE            0x02    /* rw DMA / pseudo DMA mode */
        !           108: #define MR_ARBITRATE           0x01    /* rw start arbitration */
        !           109: 
        !           110: #ifdef PARITY
        !           111: #define MR_BASE                        MR_ENABLE_PAR_CHECK
        !           112: #else
        !           113: #define MR_BASE                        0
        !           114: #endif
        !           115: 
        !           116: #define TARGET_COMMAND_REG     3
        !           117: #define TCR_LAST_BYTE_SENT     0x80    /* ro DMA done */
        !           118: #define TCR_ASSERT_REQ         0x08    /* tgt rw assert REQ */
        !           119: #define TCR_ASSERT_MSG         0x04    /* tgt rw assert MSG */
        !           120: #define TCR_ASSERT_CD          0x02    /* tgt rw assert CD */
        !           121: #define TCR_ASSERT_IO          0x01    /* tgt rw assert IO */
        !           122: 
        !           123: #define STATUS_REG             4       /* ro */
        !           124: /*
        !           125:  * Note : a set bit indicates an active signal, driven by us or another 
        !           126:  * device.
        !           127:  */
        !           128: #define SR_RST                 0x80    
        !           129: #define SR_BSY                 0x40
        !           130: #define SR_REQ                 0x20
        !           131: #define SR_MSG                 0x10
        !           132: #define SR_CD                  0x08
        !           133: #define SR_IO                  0x04
        !           134: #define SR_SEL                 0x02
        !           135: #define SR_DBP                 0x01
        !           136: 
        !           137: /*
        !           138:  * Setting a bit in this register will cause an interrupt to be generated when 
        !           139:  * BSY is false and SEL true and this bit is asserted  on the bus.
        !           140:  */
        !           141: #define SELECT_ENABLE_REG      4       /* wo */
        !           142: 
        !           143: #define BUS_AND_STATUS_REG     5       /* ro */
        !           144: #define BASR_END_DMA_TRANSFER  0x80    /* ro set on end of transfer */
        !           145: #define BASR_DRQ               0x40    /* ro mirror of DRQ pin */
        !           146: #define BASR_PARITY_ERROR      0x20    /* ro parity error detected */
        !           147: #define BASR_IRQ               0x10    /* ro mirror of IRQ pin */
        !           148: #define BASR_PHASE_MATCH       0x08    /* ro Set when MSG CD IO match TCR */
        !           149: #define BASR_BUSY_ERROR                0x04    /* ro Unexpected change to inactive state */
        !           150: #define BASR_ATN               0x02    /* ro BUS status */
        !           151: #define BASR_ACK               0x01    /* ro BUS status */
        !           152: 
        !           153: /* Write any value to this register to start a DMA send */
        !           154: #define START_DMA_SEND_REG     5       /* wo */
        !           155: 
        !           156: /* 
        !           157:  * Used in DMA transfer mode, data is latched from the SCSI bus on
        !           158:  * the falling edge of REQ (ini) or ACK (tgt)
        !           159:  */
        !           160: #define INPUT_DATA_REG                 6       /* ro */
        !           161: 
        !           162: /* Write any value to this register to start a DMA receive */
        !           163: #define START_DMA_TARGET_RECEIVE_REG   6       /* wo */
        !           164: 
        !           165: /* Read this register to clear interrupt conditions */
        !           166: #define RESET_PARITY_INTERRUPT_REG     7       /* ro */
        !           167: 
        !           168: /* Write any value to this register to start an ini mode DMA receive */
        !           169: #define START_DMA_INITIATOR_RECEIVE_REG 7      /* wo */
        !           170: 
        !           171: #define C400_CONTROL_STATUS_REG NCR53C400_register_offset-8      /* rw */
        !           172: 
        !           173: #define CSR_RESET              0x80    /* wo  Resets 53c400 */
        !           174: #define CSR_53C80_REG          0x80    /* ro  5380 registers busy */
        !           175: #define CSR_TRANS_DIR          0x40    /* rw  Data transfer direction */
        !           176: #define CSR_SCSI_BUFF_INTR     0x20    /* rw  Enable int on transfer ready */
        !           177: #define CSR_53C80_INTR         0x10    /* rw  Enable 53c80 interrupts */
        !           178: #define CSR_SHARED_INTR        0x08    /* rw  Interrupt sharing */
        !           179: #define CSR_HOST_BUF_NOT_RDY   0x04    /* ro  Is Host buffer ready */
        !           180: #define CSR_SCSI_BUF_RDY       0x02    /* ro  SCSI buffer read */
        !           181: #define CSR_GATED_53C80_IRQ    0x01    /* ro  Last block xferred */
        !           182: 
        !           183: #if 0
        !           184: #define CSR_BASE CSR_SCSI_BUFF_INTR | CSR_53C80_INTR
        !           185: #else
        !           186: #define CSR_BASE CSR_53C80_INTR
        !           187: #endif
        !           188: 
        !           189: /* Number of 128-byte blocks to be transferred */
        !           190: #define C400_BLOCK_COUNTER_REG   NCR53C400_register_offset-7      /* rw */
        !           191: 
        !           192: /* Resume transfer after disconnect */
        !           193: #define C400_RESUME_TRANSFER_REG NCR53C400_register_offset-6      /* wo */
        !           194: 
        !           195: /* Access to host buffer stack */
        !           196: #define C400_HOST_BUFFER         NCR53C400_register_offset-4      /* rw */
        !           197: 
        !           198: 
        !           199: /* Note : PHASE_* macros are based on the values of the STATUS register */
        !           200: #define PHASE_MASK     (SR_MSG | SR_CD | SR_IO)
        !           201: 
        !           202: #define PHASE_DATAOUT          0
        !           203: #define PHASE_DATAIN           SR_IO
        !           204: #define PHASE_CMDOUT           SR_CD
        !           205: #define PHASE_STATIN           (SR_CD | SR_IO)
        !           206: #define PHASE_MSGOUT           (SR_MSG | SR_CD)
        !           207: #define PHASE_MSGIN            (SR_MSG | SR_CD | SR_IO)
        !           208: #define PHASE_UNKNOWN          0xff
        !           209: 
        !           210: /* 
        !           211:  * Convert status register phase to something we can use to set phase in 
        !           212:  * the target register so we can get phase mismatch interrupts on DMA 
        !           213:  * transfers.
        !           214:  */
        !           215:  
        !           216: #define PHASE_SR_TO_TCR(phase) ((phase) >> 2)  
        !           217: 
        !           218: /*
        !           219:  * The internal should_disconnect() function returns these based on the 
        !           220:  * expected length of a disconnect if a device supports disconnect/
        !           221:  * reconnect.
        !           222:  */
        !           223: 
        !           224: #define DISCONNECT_NONE                0
        !           225: #define DISCONNECT_TIME_TO_DATA        1
        !           226: #define DISCONNECT_LONG                2
        !           227: 
        !           228: /* 
        !           229:  * These are "special" values for the tag parameter passed to NCR5380_select.
        !           230:  */
        !           231: 
        !           232: #define TAG_NEXT       -1      /* Use next free tag */
        !           233: #define TAG_NONE       -2      /* 
        !           234:                                 * Establish I_T_L nexus instead of I_T_L_Q
        !           235:                                 * even on SCSI-II devices.
        !           236:                                 */
        !           237: 
        !           238: /*
        !           239:  * These are "special" values for the irq and dma_channel fields of the 
        !           240:  * Scsi_Host structure
        !           241:  */
        !           242: 
        !           243: #define IRQ_NONE       255
        !           244: #define DMA_NONE       255
        !           245: #define IRQ_AUTO       254
        !           246: #define DMA_AUTO       254
        !           247: 
        !           248: #define FLAG_HAS_LAST_BYTE_SENT                1       /* NCR53c81 or better */
        !           249: #define FLAG_CHECK_LAST_BYTE_SENT      2       /* Only test once */
        !           250: #define FLAG_NCR53C400                 4       /* NCR53c400 */
        !           251: #define FLAG_NO_PSEUDO_DMA             8       /* Inhibit DMA */
        !           252: 
        !           253: #ifndef ASM
        !           254: struct NCR5380_hostdata {
        !           255:     NCR5380_implementation_fields;             /* implementation specific */
        !           256:     unsigned char id_mask, id_higher_mask;     /* 1 << id, all bits greater */
        !           257:     unsigned char targets_present;             /* targets we have connected
        !           258:                                                   to, so we can call a select
        !           259:                                                   failure a retryable condition */
        !           260:     volatile unsigned char busy[8];            /* index = target, bit = lun */
        !           261: #if defined(REAL_DMA) || defined(REAL_DMA_POLL)
        !           262:     volatile int dma_len;                      /* requested length of DMA */
        !           263: #endif
        !           264:     volatile unsigned char last_message;       /* last message OUT */
        !           265:     volatile Scsi_Cmnd *connected;             /* currently connected command */
        !           266:     volatile Scsi_Cmnd *issue_queue;           /* waiting to be issued */
        !           267:     volatile Scsi_Cmnd *disconnected_queue;    /* waiting for reconnect */
        !           268:     volatile int restart_select;               /* we have disconnected,
        !           269:                                                   used to restart 
        !           270:                                                   NCR5380_select() */
        !           271:     volatile unsigned aborted:1;               /* flag, says aborted */
        !           272:     int flags;
        !           273: #ifdef USLEEP
        !           274:     unsigned long time_expires;                        /* in jiffies, set prior to sleeping */
        !           275:     struct Scsi_Host *next_timer;
        !           276: #endif
        !           277: };
        !           278: 
        !           279: #ifdef __KERNEL__
        !           280: static struct Scsi_Host *first_instance;               /* linked list of 5380's */
        !           281: 
        !           282: #if defined(AUTOPROBE_IRQ)
        !           283: static int NCR5380_probe_irq (struct Scsi_Host *instance, int possible);
        !           284: #endif
        !           285: static void NCR5380_init (struct Scsi_Host *instance, int flags);
        !           286: static void NCR5380_information_transfer (struct Scsi_Host *instance);
        !           287: static void NCR5380_intr (int irq, struct pt_regs * regs);
        !           288: static void NCR5380_main (void);
        !           289: static void NCR5380_print_options (struct Scsi_Host *instance);
        !           290: static void NCR5380_print_phase (struct Scsi_Host *instance);
        !           291: static void NCR5380_print (struct Scsi_Host *instance);
        !           292: #ifndef NCR5380_abort
        !           293: static
        !           294: #endif
        !           295: int NCR5380_abort (Scsi_Cmnd *cmd);
        !           296: #ifndef NCR5380_reset
        !           297: static
        !           298: #endif
        !           299: int NCR5380_reset (Scsi_Cmnd *cmd);
        !           300: #ifndef NCR5380_queue_command
        !           301: static 
        !           302: #endif
        !           303: int NCR5380_queue_command (Scsi_Cmnd *cmd, void (*done)(Scsi_Cmnd *));
        !           304: 
        !           305: 
        !           306: static void NCR5380_reselect (struct Scsi_Host *instance);
        !           307: static int NCR5380_select (struct Scsi_Host *instance, Scsi_Cmnd *cmd, int tag);
        !           308: #if defined(PSEUDO_DMA) || defined(REAL_DMA) || defined(REAL_DMA_POLL)
        !           309: static int NCR5380_transfer_dma (struct Scsi_Host *instance,
        !           310:        unsigned char *phase, int *count, unsigned char **data);
        !           311: #endif
        !           312: static int NCR5380_transfer_pio (struct Scsi_Host *instance,
        !           313:        unsigned char *phase, int *count, unsigned char **data);
        !           314: 
        !           315: #if (defined(REAL_DMA) || defined(REAL_DMA_POLL)) && defined(i386)
        !           316: static __inline__ int NCR5380_i386_dma_setup (struct Scsi_Host *instance,
        !           317:        unsigned char *ptr, unsigned int count, unsigned char mode) {
        !           318:     unsigned limit;
        !           319: 
        !           320:     if (instance->dma_channel <=3) {
        !           321:        if (count > 65536)
        !           322:            count = 65536;
        !           323:        limit = 65536 - (((unsigned) ptr) & 0xFFFF);
        !           324:     } else {
        !           325:        if (count > 65536 * 2) 
        !           326:            count = 65536 * 2;
        !           327:        limit = 65536* 2 - (((unsigned) ptr) & 0x1FFFF);
        !           328:     }
        !           329: 
        !           330:     if (count > limit) count = limit;
        !           331: 
        !           332:     if ((count & 1) || (((unsigned) ptr) & 1))
        !           333:        panic ("scsi%d : attempted unaligned DMA transfer\n", instance->host_no);
        !           334:     cli();
        !           335:     disable_dma(instance->dma_channel);
        !           336:     clear_dma_ff(instance->dma_channel);
        !           337:     set_dma_addr(instance->dma_channel, (unsigned int) ptr);
        !           338:     set_dma_count(instance->dma_channel, count);
        !           339:     set_dma_mode(instance->dma_channel, mode);
        !           340:     enable_dma(instance->dma_channel);
        !           341:     sti();
        !           342:     return count;
        !           343: }
        !           344: 
        !           345: static __inline__ int NCR5380_i386_dma_write_setup (struct Scsi_Host *instance,
        !           346:     unsigned char *src, unsigned int count) {
        !           347:     return NCR5380_i386_dma_setup (instance, src, count, DMA_MODE_WRITE);
        !           348: }
        !           349: 
        !           350: static __inline__ int NCR5380_i386_dma_read_setup (struct Scsi_Host *instance,
        !           351:     unsigned char *src, unsigned int count) {
        !           352:     return NCR5380_i386_dma_setup (instance, src, count, DMA_MODE_READ);
        !           353: }
        !           354: 
        !           355: static __inline__ int NCR5380_i386_dma_residual (struct Scsi_Host *instance) {
        !           356:     register int tmp;
        !           357:     cli();
        !           358:     clear_dma_ff(instance->dma_channel);
        !           359:     tmp = get_dma_residue(instance->dma_channel);
        !           360:     sti();
        !           361:     return tmp;
        !           362: }
        !           363: #endif /* defined(REAL_DMA) && defined(i386)  */
        !           364: #endif __KERNEL_
        !           365: #endif /* ndef ASM */
        !           366: #endif /* NCR5380_H */

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