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1.1 root 1: /*+M*************************************************************************
2: * Adaptec AIC7xxx register and scratch ram definitions.
3: *
4: * Copyright (c) 1994, 1995, 1996 Justin T. Gibbs.
5: * All rights reserved.
6: *
7: * This program is free software; you can redistribute it and/or modify
8: * it under the terms of the GNU General Public License as published by
9: * the Free Software Foundation; either version 2, or (at your option)
10: * any later version.
11: *
12: * This program is distributed in the hope that it will be useful,
13: * but WITHOUT ANY WARRANTY; without even the implied warranty of
14: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: * GNU General Public License for more details.
16: *
17: * You should have received a copy of the GNU General Public License
18: * along with this program; see the file COPYING. If not, write to
19: * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20: *
21: * $Id: aic7xxx_reg.h,v 1.1.1.1 1997/02/25 21:27:47 thomas Exp $
22: *-M*************************************************************************/
23:
24: /*
25: * This header is shared by the sequencer code and the kernel level driver.
26: *
27: * All page numbers refer to the Adaptec AIC-7770 Data Book availible from
28: * Adaptec's Technical Documents Department 1-800-934-2766
29: */
30:
31: /*
32: * SCSI Sequence Control (p. 3-11).
33: * Each bit, when set starts a specific SCSI sequence on the bus
34: */
35: #define SCSISEQ 0x000
36: #define TEMODEO 0x80
37: #define ENSELO 0x40
38: #define ENSELI 0x20
39: #define ENRSELI 0x10
40: #define ENAUTOATNO 0x08
41: #define ENAUTOATNI 0x04
42: #define ENAUTOATNP 0x02
43: #define SCSIRSTO 0x01
44:
45: /*
46: * SCSI Transfer Control 0 Register (pp. 3-13).
47: * Controls the SCSI module data path.
48: */
49: #define SXFRCTL0 0x001
50: #define DFON 0x80
51: #define DFPEXP 0x40
52: #define ULTRAEN 0x20
53: #define CLRSTCNT 0x10
54: #define SPIOEN 0x08
55: #define SCAMEN 0x04
56: #define CLRCHN 0x02
57: /* UNUSED 0x01 */
58:
59: /*
60: * SCSI Transfer Control 1 Register (pp. 3-14,15).
61: * Controls the SCSI module data path.
62: */
63: #define SXFRCTL1 0x002
64: #define BITBUCKET 0x80
65: #define SWRAPEN 0x40
66: #define ENSPCHK 0x20
67: #define STIMESEL 0x18
68: #define ENSTIMER 0x04
69: #define ACTNEGEN 0x02
70: #define STPWEN 0x01 /* Powered Termination */
71:
72: /*
73: * SCSI Control Signal Read Register (p. 3-15).
74: * Reads the actual state of the SCSI bus pins
75: */
76: #define SCSISIGI 0x003
77: #define CDI 0x80
78: #define IOI 0x40
79: #define MSGI 0x20
80: #define ATNI 0x10
81: #define SELI 0x08
82: #define BSYI 0x04
83: #define REQI 0x02
84: #define ACKI 0x01
85:
86: /*
87: * Possible phases in SCSISIGI
88: */
89: #define PHASE_MASK 0xe0
90: #define P_DATAOUT 0x00
91: #define P_DATAIN 0x40
92: #define P_COMMAND 0x80
93: #define P_MESGOUT 0xa0
94: #define P_STATUS 0xc0
95: #define P_MESGIN 0xe0
96: /*
97: * SCSI Contol Signal Write Register (p. 3-16).
98: * Writing to this register modifies the control signals on the bus. Only
99: * those signals that are allowed in the current mode (Initiator/Target) are
100: * asserted.
101: */
102: #define SCSISIGO 0x003
103: #define CDO 0x80
104: #define IOO 0x40
105: #define MSGO 0x20
106: #define ATNO 0x10
107: #define SELO 0x08
108: #define BSYO 0x04
109: #define REQO 0x02
110: #define ACKO 0x01
111:
112: /*
113: * SCSI Rate Control (p. 3-17).
114: * Contents of this register determine the Synchronous SCSI data transfer
115: * rate and the maximum synchronous Req/Ack offset. An offset of 0 in the
116: * SOFS (3:0) bits disables synchronous data transfers. Any offset value
117: * greater than 0 enables synchronous transfers.
118: */
119: #define SCSIRATE 0x004
120: #define WIDEXFER 0x80 /* Wide transfer control */
121: #define SXFR 0x70 /* Sync transfer rate */
122: #define SOFS 0x0f /* Sync offset */
123:
124: /*
125: * SCSI ID (p. 3-18).
126: * Contains the ID of the board and the current target on the
127: * selected channel.
128: */
129: #define SCSIID 0x005
130: #define TID 0xf0 /* Target ID mask */
131: #define OID 0x0f /* Our ID mask */
132:
133: /*
134: * SCSI Latched Data (p. 3-19).
135: * Read/Write latchs used to transfer data on the SCSI bus during
136: * Automatic or Manual PIO mode. SCSIDATH can be used for the
137: * upper byte of a 16bit wide asyncronouse data phase transfer.
138: */
139: #define SCSIDATL 0x006
140: #define SCSIDATH 0x007
141:
142: /*
143: * SCSI Transfer Count (pp. 3-19,20)
144: * These registers count down the number of bytes transfered
145: * across the SCSI bus. The counter is decremented only once
146: * the data has been safely transfered. SDONE in SSTAT0 is
147: * set when STCNT goes to 0
148: */
149: #define STCNT 0x008
150: #define STCNT0 0x008
151: #define STCNT1 0x009
152: #define STCNT2 0x00a
153:
154: /*
155: * Clear SCSI Interrupt 0 (p. 3-20)
156: * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0.
157: */
158: #define CLRSINT0 0x00b
159: #define CLRSELDO 0x40
160: #define CLRSELDI 0x20
161: #define CLRSELINGO 0x10
162: #define CLRSWRAP 0x08
163: /* UNUSED 0x04 */
164: #define CLRSPIORDY 0x02
165: /* UNUSED 0x01 */
166:
167: /*
168: * SCSI Status 0 (p. 3-21)
169: * Contains one set of SCSI Interrupt codes
170: * These are most likely of interest to the sequencer
171: */
172: #define SSTAT0 0x00b
173: #define TARGET 0x80 /* Board acting as target */
174: #define SELDO 0x40 /* Selection Done */
175: #define SELDI 0x20 /* Board has been selected */
176: #define SELINGO 0x10 /* Selection In Progress */
177: #define SWRAP 0x08 /* 24bit counter wrap */
178: #define SDONE 0x04 /* STCNT = 0x000000 */
179: #define SPIORDY 0x02 /* SCSI PIO Ready */
180: #define DMADONE 0x01 /* DMA transfer completed */
181:
182: /*
183: * Clear SCSI Interrupt 1 (p. 3-23)
184: * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1.
185: */
186: #define CLRSINT1 0x00c
187: #define CLRSELTIMEO 0x80
188: #define CLRATNO 0x40
189: #define CLRSCSIRSTI 0x20
190: /* UNUSED 0x10 */
191: #define CLRBUSFREE 0x08
192: #define CLRSCSIPERR 0x04
193: #define CLRPHASECHG 0x02
194: #define CLRREQINIT 0x01
195:
196: /*
197: * SCSI Status 1 (p. 3-24)
198: */
199: #define SSTAT1 0x00c
200: #define SELTO 0x80
201: #define ATNTARG 0x40
202: #define SCSIRSTI 0x20
203: #define PHASEMIS 0x10
204: #define BUSFREE 0x08
205: #define SCSIPERR 0x04
206: #define PHASECHG 0x02
207: #define REQINIT 0x01
208:
209: /*
210: * SCSI Interrupt Mode 1 (pp. 3-28,29)
211: * Setting any bit will enable the corresponding function
212: * in SIMODE1 to interrupt via the IRQ pin.
213: */
214: #define SIMODE1 0x011
215: #define ENSELTIMO 0x80
216: #define ENATNTARG 0x40
217: #define ENSCSIRST 0x20
218: #define ENPHASEMIS 0x10
219: #define ENBUSFREE 0x08
220: #define ENSCSIPERR 0x04
221: #define ENPHASECHG 0x02
222: #define ENREQINIT 0x01
223:
224: /*
225: * SCSI Data Bus (High) (p. 3-29)
226: * This register reads data on the SCSI Data bus directly.
227: */
228: #define SCSIBUSL 0x012
229: #define SCSIBUSH 0x013
230:
231: /*
232: * SCSI/Host Address (p. 3-30)
233: * These registers hold the host address for the byte about to be
234: * transfered on the SCSI bus. They are counted up in the same
235: * manner as STCNT is counted down. SHADDR should always be used
236: * to determine the address of the last byte transfered since HADDR
237: * can be squewed by write ahead.
238: */
239: #define SHADDR 0x014
240: #define SHADDR0 0x014
241: #define SHADDR1 0x015
242: #define SHADDR2 0x016
243: #define SHADDR3 0x017
244:
245: /*
246: * Selection/Reselection ID (p. 3-31)
247: * Upper four bits are the device id. The ONEBIT is set when the re/selecting
248: * device did not set its own ID.
249: */
250: #define SELID 0x019
251: #define SELID_MASK 0xf0
252: #define ONEBIT 0x08
253: /* UNUSED 0x07 */
254:
255: /*
256: * SCSI Block Control (p. 3-32)
257: * Controls Bus type and channel selection. In a twin channel configuration
258: * addresses 0x00-0x1e are gated to the appropriate channel based on this
259: * register. SELWIDE allows for the coexistence of 8bit and 16bit devices
260: * on a wide bus.
261: */
262: #define SBLKCTL 0x01f
263: #define DIAGLEDEN 0x80 /* Aic78X0 only */
264: #define DIAGLEDON 0x40 /* Aic78X0 only */
265: #define AUTOFLUSHDIS 0x20
266: /* UNUSED 0x10 */
267: #define SELBUS_MASK 0x0a
268: #define SELBUSB 0x08
269: /* UNUSED 0x04 */
270: #define SELWIDE 0x02
271: /* UNUSED 0x01 */
272: #define SELNARROW 0x00
273:
274: /*
275: * Sequencer Control (p. 3-33)
276: * Error detection mode and speed configuration
277: */
278: #define SEQCTL 0x060
279: #define PERRORDIS 0x80
280: #define PAUSEDIS 0x40
281: #define FAILDIS 0x20
282: #define FASTMODE 0x10
283: #define BRKADRINTEN 0x08
284: #define STEP 0x04
285: #define SEQRESET 0x02
286: #define LOADRAM 0x01
287:
288: /*
289: * Sequencer RAM Data (p. 3-34)
290: * Single byte window into the Scratch Ram area starting at the address
291: * specified by SEQADDR0 and SEQADDR1. To write a full word, simply write
292: * four bytes in sucessesion. The SEQADDRs will increment after the most
293: * significant byte is written
294: */
295: #define SEQRAM 0x061
296:
297: /*
298: * Sequencer Address Registers (p. 3-35)
299: * Only the first bit of SEQADDR1 holds addressing information
300: */
301: #define SEQADDR0 0x062
302: #define SEQADDR1 0x063
303: #define SEQADDR1_MASK 0x01
304:
305: /*
306: * Accumulator
307: * We cheat by passing arguments in the Accumulator up to the kernel driver
308: */
309: #define ACCUM 0x064
310:
311: #define SINDEX 0x065
312: #define DINDEX 0x066
313: #define ALLZEROS 0x06a
314: #define NONE 0x06a
315: #define SINDIR 0x06c
316: #define DINDIR 0x06d
317: #define FUNCTION1 0x06e
318:
319: /*
320: * Host Address (p. 3-48)
321: * This register contains the address of the byte about
322: * to be transfered across the host bus.
323: */
324: #define HADDR 0x088
325: #define HADDR0 0x088
326: #define HADDR1 0x089
327: #define HADDR2 0x08a
328: #define HADDR3 0x08b
329:
330: #define HCNT 0x08c
331: #define HCNT0 0x08c
332: #define HCNT1 0x08d
333: #define HCNT2 0x08e
334:
335: /*
336: * SCB Pointer (p. 3-49)
337: * Gate one of the four SCBs into the SCBARRAY window.
338: */
339: #define SCBPTR 0x090
340:
341: /*
342: * Board Control (p. 3-43)
343: */
344: #define BCTL 0x084
345: /* RSVD 0xf0 */
346: #define ACE 0x08 /* Support for external processors */
347: /* RSVD 0x06 */
348: #define ENABLE 0x01
349:
350: /*
351: * On the aic78X0 chips, Board Control is replaced by the DSCommand
352: * register (p. 4-64)
353: */
354: #define DSCOMMAND 0x084
355: #define CACHETHEN 0x80 /* Cache Threshold enable */
356: #define DPARCKEN 0x40 /* Data Parity Check Enable */
357: #define MPARCKEN 0x20 /* Memory Parity Check Enable */
358: #define EXTREQLCK 0x10 /* External Request Lock */
359:
360: /*
361: * Bus On/Off Time (p. 3-44)
362: */
363: #define BUSTIME 0x085
364: #define BOFF 0xf0
365: #define BON 0x0f
366: #define BOFF_60BCLKS 0xf0
367:
368: /*
369: * Bus Speed (p. 3-45)
370: */
371: #define BUSSPD 0x086
372: #define DFTHRSH 0xc0
373: #define STBOFF 0x38
374: #define STBON 0x07
375: #define DFTHRSH_100 0xc0
376:
377: /*
378: * Host Control (p. 3-47) R/W
379: * Overal host control of the device.
380: */
381: #define HCNTRL 0x087
382: /* UNUSED 0x80 */
383: #define POWRDN 0x40
384: /* UNUSED 0x20 */
385: #define SWINT 0x10
386: #define IRQMS 0x08
387: #define PAUSE 0x04
388: #define INTEN 0x02
389: #define CHIPRST 0x01
390:
391: /*
392: * Interrupt Status (p. 3-50)
393: * Status for system interrupts
394: */
395: #define INTSTAT 0x091
396: #define SEQINT_MASK 0xf1 /* SEQINT Status Codes */
397: #define BAD_PHASE 0x01 /* unknown scsi bus phase */
398: #define SEND_REJECT 0x11 /* sending a message reject */
399: #define NO_IDENT 0x21 /* no IDENTIFY after reconnect*/
400: #define NO_MATCH 0x31 /* no cmd match for reconnect */
401: #define SDTR_MSG 0x41 /* SDTR message recieved */
402: #define WDTR_MSG 0x51 /* WDTR message recieved */
403: #define REJECT_MSG 0x61 /* Reject message recieved */
404: #define BAD_STATUS 0x71 /* Bad status from target */
405: #define RESIDUAL 0x81 /* Residual byte count != 0 */
406: #define ABORT_TAG 0x91 /* Sent an ABORT_TAG message */
407: #define AWAITING_MSG 0xa1 /*
408: * Kernel requested to specify
409: * a message to this target
410: * (command was null), so tell
411: * it that it can fill the
412: * message buffer.
413: */
414: #define IMMEDDONE 0xb1 /*
415: * An immediate command has
416: * completed
417: */
418: #define MSG_BUFFER_BUSY 0xc1 /*
419: * Sequencer wants to use the
420: * message buffer, but it
421: * already contains a message
422: */
423: #define MSGIN_PHASEMIS 0xd1 /*
424: * Target changed phase on us
425: * when we were expecting
426: * another msgin byte.
427: */
428: #define PARITY_ERROR 0xe1 /*
429: * Sequencer detected a parity
430: * error.
431: */
432: #define BRKADRINT 0x08
433: #define SCSIINT 0x04
434: #define CMDCMPLT 0x02
435: #define SEQINT 0x01
436: #define INT_PEND (BRKADRINT | SEQINT | SCSIINT | CMDCMPLT)
437:
438: /*
439: * Hard Error (p. 3-53)
440: * Reporting of catastrophic errors. You usually cannot recover from
441: * these without a full board reset.
442: */
443: #define ERROR 0x092
444: /* UNUSED 0xf0 */
445: #define PARERR 0x08
446: #define ILLOPCODE 0x04
447: #define ILLSADDR 0x02
448: #define ILLHADDR 0x01
449:
450: /*
451: * Clear Interrupt Status (p. 3-52)
452: */
453: #define CLRINT 0x092
454: #define CLRBRKADRINT 0x08
455: #define CLRSCSIINT 0x04
456: #define CLRCMDINT 0x02
457: #define CLRSEQINT 0x01
458:
459: #define DFCNTRL 0x093
460: #define WIDEODD 0x40
461: #define SCSIEN 0x20
462: #define SDMAEN 0x10
463: #define SDMAENACK 0x10
464: #define HDMAEN 0x08
465: #define HDMAENACK 0x08
466: #define DIRECTION 0x04
467: #define FIFOFLUSH 0x02
468: #define FIFORESET 0x01
469:
470: #define DFSTATUS 0x094
471: #define HDONE 0x08
472: #define FIFOEMP 0x01
473:
474: #define DFDAT 0x099
475:
476: /*
477: * SCB Auto Increment (p. 3-59)
478: * Byte offset into the SCB Array and an optional bit to allow auto
479: * incrementing of the address during download and upload operations
480: */
481: #define SCBCNT 0x09a
482: #define SCBAUTO 0x80
483: #define SCBCNT_MASK 0x1f
484:
485: /*
486: * Queue In FIFO (p. 3-60)
487: * Input queue for queued SCBs (commands that the seqencer has yet to start)
488: */
489: #define QINFIFO 0x09b
490:
491: /*
492: * Queue In Count (p. 3-60)
493: * Number of queued SCBs
494: */
495: #define QINCNT 0x09c
496:
497: /*
498: * Queue Out FIFO (p. 3-61)
499: * Queue of SCBs that have completed and await the host
500: */
501: #define QOUTFIFO 0x09d
502:
503: /*
504: * Queue Out Count (p. 3-61)
505: * Number of queued SCBs in the Out FIFO
506: */
507: #define QOUTCNT 0x09e
508:
509: /*
510: * SCB Definition (p. 5-4)
511: * The two reserved bytes at SCBARRAY+1[23] are expected to be set to
512: * zero. Bit 3 in SCBARRAY+0 is used as an internal flag to indicate
513: * whether or not to DMA an SCB from host ram. This flag prevents the
514: * "re-fetching" of transactions that are requed because the target is
515: * busy with another command. We also use bits 6 & 7 to indicate whether
516: * or not to initiate SDTR or WDTR repectively when starting this command.
517: */
518: #define SCBARRAY 0x0a0
519: #define SCB_CONTROL 0x0a0
520: #define NEEDWDTR 0x80
521: #define DISCENB 0x40
522: #define TAG_ENB 0x20
523: #define NEEDSDTR 0x10
524: #define DISCONNECTED 0x04
525: #define SCB_TAG_TYPE 0x03
526: #define SCB_TCL 0x0a1
527: #define SCB_TARGET_STATUS 0x0a2
528: #define SCB_SGCOUNT 0x0a3
529: #define SCB_SGPTR 0x0a4
530: #define SCB_SGPTR0 0x0a4
531: #define SCB_SGPTR1 0x0a5
532: #define SCB_SGPTR2 0x0a6
533: #define SCB_SGPTR3 0x0a7
534: #define SCB_RESID_SGCNT 0x0a8
535: #define SCB_RESID_DCNT 0x0a9
536: #define SCB_RESID_DCNT0 0x0a9
537: #define SCB_RESID_DCNT1 0x0aa
538: #define SCB_RESID_DCNT2 0x0ab
539: #define SCB_DATAPTR 0x0ac
540: #define SCB_DATAPTR0 0x0ac
541: #define SCB_DATAPTR1 0x0ad
542: #define SCB_DATAPTR2 0x0ae
543: #define SCB_DATAPTR3 0x0af
544: #define SCB_DATACNT 0x0b0
545: #define SCB_DATACNT0 0x0b0
546: #define SCB_DATACNT1 0x0b1
547: #define SCB_DATACNT2 0x0b2
548: /* UNUSED - QUAD PADDING 0x0b3 */
549: #define SCB_CMDPTR 0x0b4
550: #define SCB_CMDPTR0 0x0b4
551: #define SCB_CMDPTR1 0x0b5
552: #define SCB_CMDPTR2 0x0b6
553: #define SCB_CMDPTR3 0x0b7
554: #define SCB_CMDLEN 0x0b8
555: #define SCB_NEXT_WAITING 0x0b9
556:
557: #ifdef linux
558: #define SG_SIZEOF 0x0c /* sizeof(struct scatterlist) */
559: #else
560: #define SG_SIZEOF 0x08 /* sizeof(struct ahc_dma) */
561: #endif
562:
563: /* --------------------- AHA-2840-only definitions -------------------- */
564:
565: #define SEECTL_2840 0x0c0
566: /* UNUSED 0xf8 */
567: #define CS_2840 0x04
568: #define CK_2840 0x02
569: #define DO_2840 0x01
570:
571: #define STATUS_2840 0x0c1
572: #define EEPROM_TF 0x80
573: #define BIOS_SEL 0x60
574: #define ADSEL 0x1e
575: #define DI_2840 0x01
576:
577: /* --------------------- AIC-7870-only definitions -------------------- */
578:
579: #define DSPCISTATUS 0x086
580:
581: /*
582: * Serial EEPROM Control (p. 4-92 in 7870 Databook)
583: * Controls the reading and writing of an external serial 1-bit
584: * EEPROM Device. In order to access the serial EEPROM, you must
585: * first set the SEEMS bit that generates a request to the memory
586: * port for access to the serial EEPROM device. When the memory
587: * port is not busy servicing another request, it reconfigures
588: * to allow access to the serial EEPROM. When this happens, SEERDY
589: * gets set high to verify that the memory port access has been
590: * granted.
591: *
592: * After successful arbitration for the memory port, the SEECS bit of
593: * the SEECTL register is connected to the chip select. The SEECK,
594: * SEEDO, and SEEDI are connected to the clock, data out, and data in
595: * lines respectively. The SEERDY bit of SEECTL is useful in that it
596: * gives us an 800 nsec timer. After a write to the SEECTL register,
597: * the SEERDY goes high 800 nsec later. The one exception to this is
598: * when we first request access to the memory port. The SEERDY goes
599: * high to signify that access has been granted and, for this case, has
600: * no implied timing.
601: *
602: * See 93cx6.c for detailed information on the protocol necessary to
603: * read the serial EEPROM.
604: */
605: #define SEECTL 0x01e
606: #define EXTARBACK 0x80
607: #define EXTARBREQ 0x40
608: #define SEEMS 0x20
609: #define SEERDY 0x10
610: #define SEECS 0x08
611: #define SEECK 0x04
612: #define SEEDO 0x02
613: #define SEEDI 0x01
614:
615: /* ---------------------- Scratch RAM Offsets ------------------------- */
616: /* These offsets are either to values that are initialized by the board's
617: * BIOS or are specified by the sequencer code.
618: *
619: * The host adapter card (at least the BIOS) uses 20-2f for SCSI
620: * device information, 32-33 and 5a-5f as well. As it turns out, the
621: * BIOS trashes 20-2f, writing the synchronous negotiation results
622: * on top of the BIOS values, so we re-use those for our per-target
623: * scratchspace (actually a value that can be copied directly into
624: * SCSIRATE). The kernel driver will enable synchronous negotiation
625: * for all targets that have a value other than 0 in the lower four
626: * bits of the target scratch space. This should work regardless of
627: * whether the bios has been installed.
628: */
629:
630: /*
631: * 1 byte per target starting at this address for configuration values
632: */
633: #define TARG_SCRATCH 0x020
634:
635: /*
636: * The sequencer will stick the frist byte of any rejected message here so
637: * we can see what is getting thrown away.
638: */
639: #define REJBYTE 0x031
640:
641: /*
642: * Bit vector of targets that have disconnection disabled.
643: */
644: #define DISC_DSB 0x032
645: #define DISC_DSB_A 0x032
646: #define DISC_DSB_B 0x033
647:
648: /*
649: * Length of pending message
650: */
651: #define MSG_LEN 0x034
652:
653: #define MSG0 0x035
654: #define COMP_MSG0 0xcb /* 2's complement of MSG0 */
655: #define MSG1 0x036
656: #define MSG2 0x037
657: #define MSG3 0x038
658: #define MSG4 0x039
659: #define MSG5 0x03a
660:
661: /*
662: * These are offsets into the card's scratch ram. Some of the values are
663: * specified in the AHA2742 technical reference manual and are initialized
664: * by the BIOS at boot time.
665: */
666: #define LASTPHASE 0x049
667: #define ARG_1 0x04a
668: #define RETURN_1 0x04a
669: #define SEND_SENSE 0x80
670: #define SEND_WDTR 0x80
671: #define SEND_SDTR 0x80
672: #define SEND_REJ 0x40
673:
674: #define SIGSTATE 0x04b
675:
676: #define DMAPARAMS 0x04c /* Parameters for DMA Logic */
677:
678: #define SG_COUNT 0x04d
679: #define SG_NEXT 0x04e /* working value of SG pointer */
680: #define SG_NEXT0 0x04e
681: #define SG_NEXT1 0x04f
682: #define SG_NEXT2 0x050
683: #define SG_NEXT3 0x051
684:
685: #define SCBCOUNT 0x052 /*
686: * Number of SCBs supported by
687: * this card.
688: */
689: #define FLAGS 0x053
690: #define SINGLE_BUS 0x00
691: #define TWIN_BUS 0x01
692: #define WIDE_BUS 0x02
693: #define DPHASE 0x04
694: #define MAXOFFSET 0x08
695: #define IDENTIFY_SEEN 0x40
696: #define RESELECTED 0x80
697:
698: #define ACTIVE_A 0x054
699: #define ACTIVE_B 0x055
700: #define SAVED_TCL 0x056 /*
701: * Temporary storage for the
702: * target/channel/lun of a
703: * reconnecting target
704: */
705: #define WAITING_SCBH 0x057 /*
706: * head of list of SCBs awaiting
707: * selection
708: */
709: #define WAITING_SCBT 0x058 /*
710: * tail of list of SCBs awaiting
711: * selection
712: */
713: #define COMP_SCBCOUNT 0x059
714: #define SCB_LIST_NULL 0xff
715:
716: #define SCSICONF 0x05a
717: #define HOSTCONF 0x05d
718:
719: #define HA_274_BIOSCTRL 0x05f
720: #define BIOSMODE 0x30
721: #define BIOSDISABLED 0x30
722:
723: /* Message codes */
724: #define MSG_EXTENDED 0x01
725: #define MSG_SDTR 0x01
726: #define MSG_WDTR 0x03
727: #define MSG_SDPTRS 0x02
728: #define MSG_RDPTRS 0x03
729: #define MSG_DISCONNECT 0x04
730: #define MSG_INITIATOR_DET_ERROR 0x05
731: #define MSG_ABORT 0x06
732: #define MSG_REJECT 0x07
733: #define MSG_NOP 0x08
734: #define MSG_MSG_PARITY_ERROR 0x09
735: #define MSG_BUS_DEVICE_RESET 0x0c
736: #define MSG_SIMPLE_TAG 0x20
737: #define MSG_IDENTIFY 0x80
738:
739: /* WDTR Message values */
740: #define BUS_8_BIT 0x00
741: #define BUS_16_BIT 0x01
742: #define BUS_32_BIT 0x02
743:
744: #define MAX_OFFSET_8BIT 0x0f
745: #define MAX_OFFSET_16BIT 0x08
746:
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