Annotation of Gnu-Mach/i386/i386at/if_3c501.h, revision 1.1.1.1

1.1       root        1: /* 
                      2:  * Mach Operating System
                      3:  * Copyright (c) 1991,1990,1989 Carnegie Mellon University
                      4:  * All Rights Reserved.
                      5:  * 
                      6:  * Permission to use, copy, modify and distribute this software and its
                      7:  * documentation is hereby granted, provided that both the copyright
                      8:  * notice and this permission notice appear in all copies of the
                      9:  * software, derivative works or modified versions, and any portions
                     10:  * thereof, and that both notices appear in supporting documentation.
                     11:  * 
                     12:  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
                     13:  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
                     14:  * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
                     15:  * 
                     16:  * Carnegie Mellon requests users of this software to return to
                     17:  * 
                     18:  *  Software Distribution Coordinator  or  [email protected]
                     19:  *  School of Computer Science
                     20:  *  Carnegie Mellon University
                     21:  *  Pittsburgh PA 15213-3890
                     22:  * 
                     23:  * any improvements or extensions that they make and grant Carnegie Mellon
                     24:  * the rights to redistribute these changes.
                     25:  */
                     26: /*
                     27:  *     File:   if_3c501.h
                     28:  *     Author: Philippe Bernadat
                     29:  *     Date:   1989
                     30:  *     Copyright (c) 1989 OSF Research Institute 
                     31:  *
                     32:  *     3COM Etherlink 3C501 Mach Ethernet drvier
                     33:  */
                     34: /*
                     35:   Copyright 1990 by Open Software Foundation,
                     36: Cambridge, MA.
                     37: 
                     38:                All Rights Reserved
                     39: 
                     40:   Permission to use, copy, modify, and distribute this software and
                     41: its documentation for any purpose and without fee is hereby granted,
                     42: provided that the above copyright notice appears in all copies and
                     43: that both the copyright notice and this permission notice appear in
                     44: supporting documentation, and that the name of OSF or Open Software
                     45: Foundation not be used in advertising or publicity pertaining to
                     46: distribution of the software without specific, written prior
                     47: permission.
                     48: 
                     49:   OSF DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE
                     50: INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS,
                     51: IN NO EVENT SHALL OSF BE LIABLE FOR ANY SPECIAL, INDIRECT, OR
                     52: CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
                     53: LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT,
                     54: NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION
                     55: WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
                     56: */
                     57: 
                     58: /* The various IE command registers */
                     59: 
                     60: #define        EDLC_ADDR(base) (base)          /* EDLC station address, 6 bytes*/
                     61: #define        EDLC_RCV(base)  ((base)+0x6)    /* EDLC receive cmd. & stat.    */
                     62: #define        EDLC_XMT(base)  ((base)+0x7)    /* EDLC transmit cmd. & stat.   */
                     63: #define        IE_GP(base)     ((base)+0x8)    /* General Purpose pointer      */
                     64: #define        IE_RP(base)     ((base)+0xa)    /* Receive buffer pointer       */
                     65: #define        IE_SAPROM(base) ((base)+0xc)    /* station addr prom window     */
                     66: #define        IE_CSR(base)    ((base)+0xe)    /* IE command and status        */
                     67: #define        IE_BFR(base)    ((base)+0xf)    /* 1 byte window on packet buffer*/
                     68: 
                     69: /*  CSR Status Register (read)
                     70:  *
                     71:  *  _______________________________________________________________________ 
                     72:  * |        |        |        |        |        |        |        |        |
                     73:  * | XMTBSY |  RIDE  |   DMA  |  EDMA  |      BUFCTL     |        | RCVBSY |
                     74:  * |________|________|________|________|________|________|________|________|
                     75:  *
                     76:  */
                     77: 
                     78: /*  CSR Command Register (write)
                     79:  * 
                     80:  *  _______________________________________________________________________ 
                     81:  * |        |        |        |        |        |        |        |        |
                     82:  * | RESET  |  RIDE  |   DMA  |        |      BUFCTL     |        |  IRE   |
                     83:  * |________|________|________|________|________|________|________|________|
                     84:  * 
                     85:  */
                     86: 
                     87: #define        IE_XMTBSY       0x80    /* Transmitter busy (ro)                */
                     88: #define        IE_RESET        0x80    /* reset the controller (wo)            */
                     89: #define        IE_RIDE         0x40    /* request interrupt/DMA enable (rw)    */
                     90: #define        IE_DMA          0x20    /* DMA request (rw)                     */
                     91: #define        IE_EDMA         0x10    /* DMA done (ro)                        */
                     92: #define        IE_BUFCTL       0x0c    /* mask for buffer control field (rw)   */
                     93: #define        IE_RCVBSY       0x01    /* receive in progress (ro)             */
                     94: #define        IE_IRE          0x01    /* Interrupt request enable             */
                     95: 
                     96: /* BUFCTL values */
                     97: 
                     98: #define        IE_LOOP         0x0c    /* 2 bit field in bits 2,3, loopback    */
                     99: #define        IE_RCVEDLC      0x08    /* gives buffer to receiver             */
                    100: #define        IE_XMTEDLC      0x04    /* gives buffer to transmit             */
                    101: #define        IE_SYSBFR       0x00    /* gives buffer to processor            */
                    102: 
                    103: /*  XMTCSR Transmit Status Register (read)
                    104:  * 
                    105:  *  _______________________________________________________________________ 
                    106:  * |        |        |        |        |        |        |        |        |
                    107:  * |        |        |        |        |  IDLE  |  16    |   JAM  |  UNDER |
                    108:  * |________|________|________|________|________|________|________|________|
                    109:  * 
                    110:  */
                    111: 
                    112: /*  XMTCSR Transmit Command Register (write) enables interrupts when written
                    113:  * 
                    114:  *  _______________________________________________________________________ 
                    115:  * |        |        |        |        |        |        |        |        |
                    116:  * |        |        |        |        |        |        |        |        |
                    117:  * |________|________|________|________|________|________|________|________|
                    118:  * 
                    119:  */
                    120: 
                    121: #define        EDLC_IDLE       0x08    /* transmit idle                        */
                    122: #define        EDLC_16         0x04    /* packet experienced 16 collisions     */
                    123: #define        EDLC_JAM        0x02    /* packet experienced a collision       */
                    124: #define        EDLC_UNDER      0x01    /* data underflow                       */
                    125: 
                    126: /*  RCVCSR Receive Status Register (read) 
                    127:  * 
                    128:  *  _______________________________________________________________________ 
                    129:  * |        |        |        |        |        |        |        |        |
                    130:  * |  STALE |        |  GOOD  |  ANY   | SHORT  | DRIBBLE|  FCS   |  OVER  |
                    131:  * |________|________|________|________|________|________|________|________|
                    132:  *
                    133:  */
                    134: 
                    135: /*  RCVCSR Receive Command Register (write) enables interrupt when written
                    136:  * 
                    137:  *  _______________________________________________________________________ 
                    138:  * |        |        |        |        |        |        |        |        |
                    139:  * | ADDR MATCH MODE |  GOOD  |  ANY   | SHORT  | DRIBBLE|  FCS   |  OVER  |
                    140:  * |________|________|________|________|________|________|________|________|
                    141:  *
                    142:  */
                    143: 
                    144: #define        EDLC_STALE      0x80    /* receive CSR status previously read   */
                    145: #define        EDLC_GOOD       0x20    /* well formed packets only             */
                    146: #define        EDLC_ANY        0x10    /* any packet, even those with errors   */
                    147: #define        EDLC_SHORT      0x08    /* short frame                          */
                    148: #define        EDLC_DRIBBLE    0x04    /* dribble error                        */
                    149: #define        EDLC_FCS        0x02    /* CRC error                            */
                    150: #define        EDLC_OVER       0x01    /* data overflow                        */
                    151: 
                    152: /* Address Match Mode */
                    153: 
                    154: #define        EDLC_NONE       0x00    /* match mode in bits 5-6, write only   */
                    155: #define        EDLC_ALL        0x40    /* promiscuous receive, write only      */
                    156: #define        EDLC_BROAD      0x80    /* station address plus broadcast       */
                    157: #define        EDLC_MULTI      0xc0    /* station address plus multicast       */
                    158:  
                    159: /* Packet Buffer size */
                    160: 
                    161: #define BFRSIZ         2048
                    162: 
                    163: #define NAT3C501       1
                    164: #define ETHER_ADD_SIZE 6       /* size of a MAC address */
                    165: 
                    166: #ifndef TRUE
                    167: #define TRUE           1
                    168: #endif TRUE
                    169: #define        HZ              100
                    170: 
                    171: #define        DSF_LOCK        1
                    172: #define DSF_RUNNING    2
                    173: 
                    174: #define MOD_ENAL 1
                    175: #define MOD_PROM 2

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