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1.1 root 1: /*
2: * Mach Operating System
3: * Copyright (c) 1991 Carnegie-Mellon University
4: * All Rights Reserved.
5: *
6: * Permission to use, copy, modify and distribute this software and its
7: * documentation is hereby granted, provided that both the copyright
8: * notice and this permission notice appear in all copies of the
9: * software, derivative works or modified versions, and any portions
10: * thereof, and that both notices appear in supporting documentation.
11: *
12: * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
13: * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
14: * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
15: *
16: * Carnegie Mellon requests users of this software to return to
17: *
18: * Software Distribution Coordinator or [email protected]
19: * School of Computer Science
20: * Carnegie Mellon University
21: * Pittsburgh PA 15213-3890
22: *
23: * any improvements or extensions that they make and grant Carnegie Mellon
24: * the rights to redistribute these changes.
25: */
26:
27: /* Vendor unique hardware addr. prefix. 3Com has 2 because they ran
28: out of available addresses on the first one... */
29:
30: #define OLD_3COM_ID 0x02608c
31: #define NEW_3COM_ID 0x0020af
32:
33: /* Gate Array Description */
34:
35: #define PSTR 0x400
36: #define PSPR 0x401
37: #define DQTR 0x402
38: #define BCFR 0x403
39: #define PCFR 0x404
40: #define GACFR 0x405
41: #define CTLR 0x406
42: #define STREG 0x407
43: #define IDCFR 0x408
44: #define DAMSB 0x409
45: #define DALSB 0x40A
46: #define VPTR2 0x40B
47: #define VPTR1 0x40C
48: #define VPTR0 0x40D
49: #define RFMSB 0x40E
50: #define RFLSB 0x40F
51:
52: /* PSTR 400 */
53: /* int */
54: /* PSPR 401 */
55: /* int */
56: /* DQTR 402 */
57: /* dma only */
58: /* BCFR 403 */
59: #define B7_300 0x300
60: #define B6_310 0x310
61: #define B5_330 0x330
62: #define B4_350 0x350
63: #define B3_250 0x250
64: #define B2_280 0x280
65: #define B1_2A0 0x2a0
66: #define B0_2E0 0x2e0
67: /* PCFR 404 */
68:
69: /* GACFR 405 */
70: #define GACFR_NIM 0x80
71: #define GACFR_TCM 0x40
72: #define GACFR_OWS 0x20
73: #define GACFR_TEST 0x10
74: #define GACFR_RSEL 0x08
75: #define GACFR_MBS2 0x04
76: #define GACFR_MBS1 0x02
77: #define GACFR_MBS0 0x01
78: /*
79: * This definition is only for the std 8k window on an 8k board.
80: * It is incorrect for a 32K board. But they do not exists yet
81: * and I don't even know how to tell I am looking at one.
82: */
83: #define GACFR_8K (GACFR_RSEL|0x1)
84: /* CTLR 406 */
85: #define CTLR_START 0x80
86: #define CTLR_DDIR 0x40
87: #define CTLR_DBSEL 0x20
88: #define CTLR_SHARE 0x10
89: #define CTLR_EAHI 0x08
90: #define CTLR_EALO 0x04
91: #define CTLR_XSEL 0x02
92: #define CTLR_RST 0x01
93: #define CTLR_EA 0x0c
94: #define CTLR_STA_ADDR 0x04
95: #define CTLR_THIN 0x02
96: #define CTLR_THICK 0x00
97: /* STREG 407 */
98: /* DMA */
99: /* IDCFR 408 */
100: #define IDCFR_IRQ5 0x80
101: #define IDCFR_IRQ4 0x40
102: #define IDCFR_IRQ3 0x20
103: #define IDCFR_IRQ2 0x10
104: #define IDCFR_DRQ3 0x04
105: #define IDCFR_DRQ2 0x02
106: #define IDCFR_DRQ1 0x01
107: /* DAMSB 409 */
108: /* int & dma */
109: /* DALSB 40A */
110: /* int & dma */
111: /* VPTR2 40B */
112: /* VPTR1 40C */
113: /* VPTR0 40D */
114: /* RFMSB 40E */
115: /* what's a register file */
116: /* RFLSB 40F */
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