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1.1 root 1: /*
2: * Mach Operating System
3: * Copyright (c) 1991,1990,1989 Carnegie Mellon University
4: * All Rights Reserved.
5: *
6: * Permission to use, copy, modify and distribute this software and its
7: * documentation is hereby granted, provided that both the copyright
8: * notice and this permission notice appear in all copies of the
9: * software, derivative works or modified versions, and any portions
10: * thereof, and that both notices appear in supporting documentation.
11: *
12: * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
13: * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
14: * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
15: *
16: * Carnegie Mellon requests users of this software to return to
17: *
18: * Software Distribution Coordinator or [email protected]
19: * School of Computer Science
20: * Carnegie Mellon University
21: * Pittsburgh PA 15213-3890
22: *
23: * any improvements or extensions that they make and grant Carnegie Mellon
24: * the rights to redistribute these changes.
25: */
26: /*
27: * Western Digital Mach Ethernet driver
28: * Copyright (c) 1990 OSF Research Institute
29: */
30: /*
31: Copyright 1990 by Open Software Foundation,
32: Cambridge, MA.
33:
34: All Rights Reserved
35:
36: Permission to use, copy, modify, and distribute this software and
37: its documentation for any purpose and without fee is hereby granted,
38: provided that the above copyright notice appears in all copies and
39: that both the copyright notice and this permission notice appear in
40: supporting documentation, and that the name of OSF or Open Software
41: Foundation not be used in advertising or publicity pertaining to
42: distribution of the software without specific, written prior
43: permission.
44:
45: OSF DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE
46: INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS,
47: IN NO EVENT SHALL OSF BE LIABLE FOR ANY SPECIAL, INDIRECT, OR
48: CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
49: LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT,
50: NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION
51: WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
52: */
53:
54: /***********************************************************/
55: /* Defines for the 583 chip. */
56: /***********************************************************/
57:
58: /*--- 8390 Registers ---*/
59: #define OFF_8390 0x10 /* offset of the 8390 chip */
60:
61: /* Register offsets */
62:
63: #define IFWD_REG_0 0x00
64: #define IFWD_REG_1 0x01
65: #define IFWD_REG_2 0x02
66: #define IFWD_REG_3 0x03
67: #define IFWD_REG_4 0x04
68: #define IFWD_REG_5 0x05
69: #define IFWD_REG_6 0x06
70: #define IFWD_REG_7 0x07
71:
72: /* Register offset definitions for all boards */
73:
74: #define IFWD_LAR_0 0x08
75: #define IFWD_LAR_1 0x09
76: #define IFWD_LAR_2 0x0a
77: #define IFWD_LAR_3 0x0b
78: #define IFWD_LAR_4 0x0c
79: #define IFWD_LAR_5 0x0d
80: #define IFWD_BOARD_ID 0x0e
81: #define IFWD_CHKSUM 0x0f
82:
83: /* revision number mask for BOARD_ID */
84: #define IFWD_BOARD_REV_MASK 0x1e
85:
86: /* REG 1 */
87: #define IFWD_MEMSIZE 0x08
88: #define IFWD_16BIT 0x01
89:
90: /* REG 5 */
91: #define IFWD_REG5_MEM_MASK 0x3f /* B23-B19 of address of the memory */
92: #define IFWD_LA19 0x01 /* B19 of address of the memory */
93: #define IFWD_MEM16ENB 0x80 /* Enable 16 bit memory access from bus */
94: #define IFWD_LAN16ENB 0x40 /* Enable 16 bit memory access from chip*/
95: #define IFWD_INIT_LAAR IFWD_LA19
96: #define IFWD_SOFTINT 0x20 /* Enable interrupt from pc */
97:
98: /* Defs for board rev numbers > 1 */
99: #define IFWD_MEDIA_TYPE 0x01
100: #define IFWD_SOFT_CONFIG 0x20
101: #define IFWD_RAM_SIZE 0x40
102: #define IFWD_BUS_TYPE 0x80
103:
104: /* Register offsets for reading the EEPROM in the 584 chip */
105: #define IFWD_EEPROM_0 0x08
106: #define IFWD_EEPROM_1 0x09
107: #define IFWD_EEPROM_2 0x0A
108: #define IFWD_EEPROM_3 0x0B
109: #define IFWD_EEPROM_4 0x0C
110: #define IFWD_EEPROM_5 0x0D
111: #define IFWD_EEPROM_6 0x0E
112: #define IFWD_EEPROM_7 0x0F
113:
114: /**** defs for manipulating the 584 ****/
115: #define IFWD_OTHER_BIT 0x02
116: #define IFWD_ICR_MASK 0x0C
117: #define IFWD_EAR_MASK 0x0F
118: #define IFWD_ENGR_PAGE 0xA0
119: /* #define IFWD_RLA 0x10 defined in ICR defs */
120: #define IFWD_EA6 0x80
121: #define IFWD_RECALL_DONE_MASK 0x10
122: #define IFWD_EEPROM_MEDIA_MASK 0x07
123: #define IFWD_STARLAN_TYPE 0x00
124: #define IFWD_ETHERNET_TYPE 0x01
125: #define IFWD_TP_TYPE 0x02
126: #define IFWD_EW_TYPE 0x03
127: #define IFWD_EEPROM_IRQ_MASK 0x18
128: #define IFWD_PRIMARY_IRQ 0x00
129: #define IFWD_ALTERNATE_IRQ_1 0x08
130: #define IFWD_ALTERNATE_IRQ_2 0x10
131: #define IFWD_ALTERNATE_IRQ_3 0x18
132: #define IFWD_EEPROM_RAM_SIZE_MASK 0xE0
133: #define IFWD_EEPROM_RAM_SIZE_RES1 0x00
134: #define IFWD_EEPROM_RAM_SIZE_RES2 0x20
135: #define IFWD_EEPROM_RAM_SIZE_8K 0x40
136: #define IFWD_EEPROM_RAM_SIZE_16K 0x60
137: #define IFWD_EEPROM_RAM_SIZE_32K 0x80
138: #define IFWD_EEPROM_RAM_SIZE_64K 0xA0
139: #define IFWD_EEPROM_RAM_SIZE_RES3 0xC0
140: #define IFWD_EEPROM_RAM_SIZE_RES4 0xE0
141: #define IFWD_EEPROM_BUS_TYPE_MASK 0x07
142: #define IFWD_EEPROM_BUS_TYPE_AT 0x00
143: #define IFWD_EEPROM_BUS_TYPE_MCA 0x01
144: #define IFWD_EEPROM_BUS_TYPE_EISA 0x02
145: #define IFWD_EEPROM_BUS_SIZE_MASK 0x18
146: #define IFWD_EEPROM_BUS_SIZE_8BIT 0x00
147: #define IFWD_EEPROM_BUS_SIZE_16BIT 0x08
148: #define IFWD_EEPROM_BUS_SIZE_32BIT 0x10
149: #define IFWD_EEPROM_BUS_SIZE_64BIT 0x18
150:
151: /*****************************************************************************
152: * *
153: * Definitions for board ID. *
154: * *
155: * note: board ID should be ANDed with the STATIC_ID_MASK *
156: * before comparing to a specific board ID *
157: * The high order 16 bits correspond to the Extra Bits which do not *
158: * change the boards ID. *
159: * *
160: * Note: not all are implemented. Rest are here for future enhancements...*
161: * *
162: *****************************************************************************/
163:
164: #define IFWD_STARLAN_MEDIA 0x00000001 /* StarLAN */
165: #define IFWD_ETHERNET_MEDIA 0x00000002 /* Ethernet */
166: #define IFWD_TWISTED_PAIR_MEDIA 0x00000003 /* Twisted Pair */
167: #define IFWD_EW_MEDIA 0x00000004 /* Ethernet and Twisted Pair */
168: #define IFWD_MICROCHANNEL 0x00000008 /* MicroChannel Adapter */
169: #define IFWD_INTERFACE_CHIP 0x00000010 /* Soft Config Adapter */
170: /* #define IFWD_UNUSED 0x00000020 */ /* used to be INTELLIGENT */
171: #define IFWD_BOARD_16BIT 0x00000040 /* 16 bit capability */
172: #define IFWD_RAM_SIZE_UNKNOWN 0x00000000 /* 000 => Unknown RAM Size */
173: #define IFWD_RAM_SIZE_RES_1 0x00010000 /* 001 => Reserved */
174: #define IFWD_RAM_SIZE_8K 0x00020000 /* 010 => 8k RAM */
175: #define IFWD_RAM_SIZE_16K 0x00030000 /* 011 => 16k RAM */
176: #define IFWD_RAM_SIZE_32K 0x00040000 /* 100 => 32k RAM */
177: #define IFWD_RAM_SIZE_64K 0x00050000 /* 101 => 64k RAM */
178: #define IFWD_RAM_SIZE_RES_6 0x00060000 /* 110 => Reserved */
179: #define IFWD_RAM_SIZE_RES_7 0x00070000 /* 111 => Reserved */
180: #define IFWD_SLOT_16BIT 0x00080000 /* 16 bit board - 16 bit slot*/
181: #define IFWD_NIC_690_BIT 0x00100000 /* NIC is 690 */
182: #define IFWD_ALTERNATE_IRQ_BIT 0x00200000 /* Alternate IRQ is used */
183: #define IFWD_INTERFACE_584_CHIP 0x00400000 /* Interface chip is a 584 */
184:
185: #define IFWD_MEDIA_MASK 0x00000007 /* Isolates Media Type */
186: #define IFWD_RAM_SIZE_MASK 0x00070000 /* Isolates RAM Size */
187: #define IFWD_STATIC_ID_MASK 0x0000FFFF /* Isolates Board ID */
188:
189: /* Word definitions for board types */
190: #define WD8003E IFWD_ETHERNET_MEDIA
191: #define WD8003EBT WD8003E /* functionally identical to WD8003E */
192: #define WD8003S IFWD_STARLAN_MEDIA
193: #define WD8003SH WD8003S /* functionally identical to WD8003S */
194: #define WD8003WT IFWD_TWISTED_PAIR_MEDIA
195: #define WD8003W (IFWD_TWISTED_PAIR_MEDIA | IFWD_INTERFACE_CHIP)
196: #define WD8003EB (IFWD_ETHERNET_MEDIA | IFWD_INTERFACE_CHIP)
197: #define WD8003EP WD8003EB /* with IFWD_INTERFACE_584_CHIP bit set */a
198: #define WD8003EW (IFWD_EW_MEDIA | IFWD_INTERFACE_CHIP)
199: #define WD8003ETA (IFWD_ETHERNET_MEDIA | IFWD_MICROCHANNEL)
200: #define WD8003STA (IFWD_STARLAN_MEDIA | IFWD_MICROCHANNEL)
201: #define WD8003EA (IFWD_ETHERNET_MEDIA | IFWD_MICROCHANNEL | \
202: IFWD_INTERFACE_CHIP)
203: #define WD8003SHA (IFWD_STARLAN_MEDIA | IFWD_MICROCHANNEL | \
204: IFWD_INTERFACE_CHIP)
205: #define WD8003WA (IFWD_TWISTED_PAIR_MEDIA | IFWD_MICROCHANNEL | \
206: IFWD_INTERFACE_CHIP)
207: #define WD8013EBT (IFWD_ETHERNET_MEDIA | IFWD_BOARD_16BIT)
208: #define WD8013EB (IFWD_ETHERNET_MEDIA | IFWD_BOARD_16BIT | \
209: IFWD_INTERFACE_CHIP)
210: #define WD8013EP WD8013EB /* with IFWD_INTERFACE_584_CHIP bit set */
211: #define WD8013W (IFWD_TWISTED_PAIR_MEDIA | IFWD_BOARD_16BIT | \
212: IFWD_INTERFACE_CHIP)
213: #define WD8013EW (IFWD_EW_MEDIA | IFWD_BOARD_16BIT | \
214: IFWD_INTERFACE_CHIP)
215:
216:
217: /**** Western digital node bytes ****/
218: #define WD_NODE_ADDR_0 0x00
219: #define WD_NODE_ADDR_1 0x00
220: #define WD_NODE_ADDR_2 0xC0
221:
222: /*--- 83c583 registers ---*/
223: #define IFWD_MSR 0x00 /* memory select register */
224: /* In 584 Board's command register */
225: #define IFWD_ICR 0x01 /* interface configuration register */
226: /* In 584 8013 bus size register */
227: #define IFWD_IAR 0x02 /* io address register */
228: #define IFWD_BIO 0x03 /* bios ROM address register */
229: #define IFWD_IRR 0x04 /* interrupt request register */
230: #define IFWD_GP1 0x05 /* general purpose register 1 */
231: #define IFWD_IOD 0x06 /* io data latch */
232: #define IFWD_GP2 0x07 /* general purpose register 2 */
233: #define IFWD_LAR 0x08 /* LAN address register */
234: #define IFWD_LAR2 0x09 /* */
235: #define IFWD_LAR3 0x0A /* */
236: #define IFWD_LAR4 0x0B /* */
237: #define IFWD_LAR5 0x0C /* */
238: #define IFWD_LAR6 0x0D /* */
239: #define IFWD_LAR7 0x0E /* */
240: #define IFWD_LAR8 0x0F /* LAN address register */
241:
242: /********************* Register Bit Definitions **************************/
243: /* MSR definitions */
244: #define IFWD_RST 0x80 /* 1 => reset */
245: #define IFWD_MENB 0x40 /* 1 => memory enable */
246: #define IFWD_SA18 0x20 /* Memory enable bits */
247: #define IFWD_SA17 0x10 /* telling where shared */
248: #define IFWD_SA16 0x08 /* mem is to start. */
249: #define IFWD_SA15 0x04 /* Assume SA19 = 1 */
250: #define IFWD_SA14 0x02 /* */
251: #define IFWD_SA13 0x01 /* */
252:
253: /* ICR definitions */
254: #define IFWD_STR 0x80 /* Non-volatile EEPROM store */
255: #define IFWD_RCL 0x40 /* Recall I/O Address from EEPROM */
256: #define IFWD_RX7 0x20 /* Recall all but I/O and LAN address*/
257: #define IFWD_RLA 0x10 /* Recall LAN Address */
258: #define IFWD_MSZ 0x08 /* Shared Memory Size */
259: #define IFWD_DMAE 0x04 /* DMA Enable */
260: #define IFWD_IOPE 0x02 /* I/O Port Enable */
261: #define IFWD_WTS 0x01 /* Word Transfer Select */
262:
263: /* IAR definitions */
264: #define IFWD_IA15 0x80 /* I/O Address Bits */
265: /* . */
266: /* . */
267: /* . */
268: #define IFWD_IA5 0x01 /* */
269:
270: /* BIO definitions */
271: #define IFWD_RS1 0x80 /* BIOS size bit 1 */
272: #define IFWD_RS0 0x40 /* BIOS size bit 0 */
273: #define IFWD_BA18 0x20 /* BIOS ROM Memory Address Bits */
274: #define IFWD_BA17 0x10 /* */
275: #define IFWD_BA16 0x08 /* */
276: #define IFWD_BA15 0x04 /* */
277: #define IFWD_BA14 0x02 /* BIOS ROM Memory Address Bits */
278: #define IFWD_WINT 0x01 /* W8003 interrupt */
279:
280: /* IRR definitions */
281: #define IFWD_IEN 0x80 /* Interrupt Enable */
282: #define IFWD_IR1 0x40 /* Interrupt request bit 1 */
283: #define IFWD_IR0 0x20 /* Interrupt request bit 0 */
284: #define IFWD_AMD 0x10 /* Alternate mode */
285: #define IFWD_AINT 0x08 /* Alternate interrupt */
286: #define IFWD_BW1 0x04 /* BIOS Wait State Control bit 1 */
287: #define IFWD_BW0 0x02 /* BIOS Wait State Control bit 0 */
288: #define IFWD_OWS 0x01 /* Zero Wait State Enable */
289:
290: /* GP1 definitions */
291:
292: /* IOD definitions */
293:
294: /* GP2 definitions */
295:
296: /*************************************************************/
297: /* Shared RAM buffer definitions */
298: /*************************************************************/
299:
300: /**** NIC definitions ****/
301: #define NIC_8003_SRAM_SIZE 0x2000 /* size of shared RAM buffer */
302: #define NIC_HEADER_SIZE 4 /* size of receive header */
303: #define NIC_PAGE_SIZE 0x100 /* each page of rcv ring is 256 byte */
304:
305: #define ETHER_ADDR_SIZE 6 /* size of a MAC address */
306:
307: #ifdef MACH
308: #define HZ 100
309: #endif
310:
311: #define DSF_LOCK 1
312: #define DSF_RUNNING 2
313:
314: #define MOD_ENAL 1
315: #define MOD_PROM 2
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