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1.1 root 1: /*
2: * Mach Operating System
3: * Copyright (c) 1991,1990,1989 Carnegie Mellon University
4: * All Rights Reserved.
5: *
6: * Permission to use, copy, modify and distribute this software and its
7: * documentation is hereby granted, provided that both the copyright
8: * notice and this permission notice appear in all copies of the
9: * software, derivative works or modified versions, and any portions
10: * thereof, and that both notices appear in supporting documentation.
11: *
12: * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
13: * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
14: * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
15: *
16: * Carnegie Mellon requests users of this software to return to
17: *
18: * Software Distribution Coordinator or [email protected]
19: * School of Computer Science
20: * Carnegie Mellon University
21: * Pittsburgh PA 15213-3890
22: *
23: * any improvements or extensions that they make and grant Carnegie Mellon
24: * the rights to redistribute these changes.
25: */
26: /*
27: Copyright 1988, 1989 by Intel Corporation, Santa Clara, California.
28:
29: All Rights Reserved
30:
31: Permission to use, copy, modify, and distribute this software and
32: its documentation for any purpose and without fee is hereby
33: granted, provided that the above copyright notice appears in all
34: copies and that both the copyright notice and this permission notice
35: appear in supporting documentation, and that the name of Intel
36: not be used in advertising or publicity pertaining to distribution
37: of the software without specific, written prior permission.
38:
39: INTEL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE
40: INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS,
41: IN NO EVENT SHALL INTEL BE LIABLE FOR ANY SPECIAL, INDIRECT, OR
42: CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
43: LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT,
44: NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION
45: WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
46: */
47:
48: #define RTC_ADDR 0x70 /* I/O port address for register select */
49: #define RTC_DATA 0x71 /* I/O port address for data read/write */
50:
51: /*
52: * Register A definitions
53: */
54: #define RTC_A 0x0a /* register A address */
55: #define RTC_UIP 0x80 /* Update in progress bit */
56: #define RTC_DIV0 0x00 /* Time base of 4.194304 MHz */
57: #define RTC_DIV1 0x10 /* Time base of 1.048576 MHz */
58: #define RTC_DIV2 0x20 /* Time base of 32.768 KHz */
59: #define RTC_RATE6 0x06 /* interrupt rate of 976.562 */
60:
61: /*
62: * Register B definitions
63: */
64: #define RTC_B 0x0b /* register B address */
65: #define RTC_SET 0x80 /* stop updates for time set */
66: #define RTC_PIE 0x40 /* Periodic interrupt enable */
67: #define RTC_AIE 0x20 /* Alarm interrupt enable */
68: #define RTC_UIE 0x10 /* Update ended interrupt enable */
69: #define RTC_SQWE 0x08 /* Square wave enable */
70: #define RTC_DM 0x04 /* Date mode, 1 = binary, 0 = BCD */
71: #define RTC_HM 0x02 /* hour mode, 1 = 24 hour, 0 = 12 hour */
72: #define RTC_DSE 0x01 /* Daylight savings enable */
73:
74: /*
75: * Register C definitions
76: */
77: #define RTC_C 0x0c /* register C address */
78: #define RTC_IRQF 0x80 /* IRQ flag */
79: #define RTC_PF 0x40 /* PF flag bit */
80: #define RTC_AF 0x20 /* AF flag bit */
81: #define RTC_UF 0x10 /* UF flag bit */
82:
83: /*
84: * Register D definitions
85: */
86: #define RTC_D 0x0d /* register D address */
87: #define RTC_VRT 0x80 /* Valid RAM and time bit */
88:
89: #define RTC_NREG 0x0e /* number of RTC registers */
90: #define RTC_NREGP 0x0a /* number of RTC registers to set time */
91:
92: #define RTCRTIME _IOR('c', 0x01, struct rtc_st) /* Read time from RTC */
93: #define RTCSTIME _IOW('c', 0x02, struct rtc_st) /* Set time into RTC */
94:
95: struct rtc_st {
96: char rtc_sec;
97: char rtc_asec;
98: char rtc_min;
99: char rtc_amin;
100: char rtc_hr;
101: char rtc_ahr;
102: char rtc_dow;
103: char rtc_dom;
104: char rtc_mon;
105: char rtc_yr;
106: char rtc_statusa;
107: char rtc_statusb;
108: char rtc_statusc;
109: char rtc_statusd;
110: };
111:
112: /*
113: * this macro reads contents of real time clock to specified buffer
114: */
115: #define load_rtc(regs) \
116: {\
117: register int i; \
118: \
119: for (i = 0; i < RTC_NREG; i++) { \
120: outb(RTC_ADDR, i); \
121: regs[i] = inb(RTC_DATA); \
122: } \
123: }
124:
125: /*
126: * this macro writes contents of specified buffer to real time clock
127: */
128: #define save_rtc(regs) \
129: { \
130: register int i; \
131: for (i = 0; i < RTC_NREGP; i++) { \
132: outb(RTC_ADDR, i); \
133: outb(RTC_DATA, regs[i]);\
134: } \
135: }
136:
137:
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