--- Gnu-Mach/i386/intel/pmap.c 2020/09/02 04:36:59 1.1 +++ Gnu-Mach/i386/intel/pmap.c 2020/09/02 04:44:40 1.1.1.2 @@ -2,24 +2,24 @@ * Mach Operating System * Copyright (c) 1991,1990,1989,1988 Carnegie Mellon University * All Rights Reserved. - * + * * Permission to use, copy, modify and distribute this software and its * documentation is hereby granted, provided that both the copyright * notice and this permission notice appear in all copies of the * software, derivative works or modified versions, and any portions * thereof, and that both notices appear in supporting documentation. - * + * * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. - * + * * Carnegie Mellon requests users of this software to return to - * + * * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU * School of Computer Science * Carnegie Mellon University * Pittsburgh PA 15213-3890 - * + * * any improvements or extensions that they make and grant Carnegie Mellon * the rights to redistribute these changes. */ @@ -83,12 +83,12 @@ #ifdef ORC #define OLIVETTICACHE 1 -#endif ORC +#endif /* ORC */ #ifndef OLIVETTICACHE #define WRITE_PTE(pte_p, pte_entry) *(pte_p) = (pte_entry); #define WRITE_PTE_FAST(pte_p, pte_entry) *(pte_p) = (pte_entry); -#else OLIVETTICACHE +#else /* OLIVETTICACHE */ #error might not work anymore /* This gross kludgery is needed for Olivetti XP7 & XP9 boxes to get @@ -125,7 +125,7 @@ pt_entry_t *pte_p, pte_entry; #define WRITE_PTE_FAST(pte_p, pte_entry)*pte_p = pte_entry; -#endif OLIVETTICACHE +#endif /* OLIVETTICACHE */ /* * Private data structures. @@ -191,7 +191,7 @@ boolean_t pmap_initialized = FALSE; */ extern vm_offset_t phys_first_addr, phys_last_addr; -/* +/* * Range of kernel virtual addresses available for kernel memory mapping. * Does not include the virtual addresses used to map physical memory 1-1. * Initialized by pmap_bootstrap. @@ -349,7 +349,7 @@ lock_data_t pmap_system_lock; } \ } -#else NCPUS > 1 +#else /* NCPUS > 1 */ #define SPLVM(spl) #define SPLX(spl) @@ -370,7 +370,7 @@ lock_data_t pmap_system_lock; } \ } -#endif NCPUS > 1 +#endif /* NCPUS > 1 */ #define MAX_TBIS_SIZE 32 /* > this -> TBIA */ /* XXX */ @@ -380,11 +380,11 @@ lock_data_t pmap_system_lock; flush(); \ flush_tlb(); \ } -#else i860 +#else /* i860 */ #define INVALIDATE_TLB(s, e) { \ flush_tlb(); \ } -#endif i860 +#endif /* i860 */ #if NCPUS > 1 @@ -415,7 +415,7 @@ typedef struct pmap_update_list *pmap_up struct pmap_update_list cpu_update_list[NCPUS]; -#endif NCPUS > 1 +#endif /* NCPUS > 1 */ /* * Other useful macros. @@ -450,7 +450,7 @@ pt_entry_t *kernel_page_dir; void pmap_remove_range(); /* forward */ #if NCPUS > 1 void signal_cpus(); /* forward */ -#endif NCPUS > 1 +#endif /* NCPUS > 1 */ #if i860 /* @@ -520,7 +520,7 @@ void ptep_check(ptep) panic("pte count"); } } -#endif DEBUG_PTE_PAGE +#endif /* DEBUG_PTE_PAGE */ /* * Map memory at initialization. The physical addresses being @@ -547,7 +547,7 @@ vm_offset_t pmap_map(virt, start, end, p } /* - * Back-door routine for mapping kernel VM at initialization. + * Back-door routine for mapping kernel VM at initialization. * Useful for mapping memory outside the range * [phys_first_addr, phys_last_addr) (i.e., devices). * Otherwise like pmap_map. @@ -614,7 +614,7 @@ void pmap_bootstrap() #if NCPUS > 1 lock_init(&pmap_system_lock, FALSE); /* NOT a sleep lock */ -#endif NCPUS > 1 +#endif /* NCPUS > 1 */ simple_lock_init(&kernel_pmap->lock); @@ -674,11 +674,11 @@ void pmap_bootstrap() { WRITE_PTE_FAST(pte, 0); } - else + else { - extern char start[], etext[]; + extern char _start[], etext[]; - if ((va >= (vm_offset_t)start) + if ((va >= (vm_offset_t)_start) && (va + INTEL_PGBYTES <= (vm_offset_t)etext)) { WRITE_PTE_FAST(pte, pa_to_pte(va) @@ -852,7 +852,7 @@ void pmap_init() simple_lock_init(&up->lock); up->count = 0; } -#endif NCPUS > 1 +#endif /* NCPUS > 1 */ /* * Indicate that the PMAP module is now fully initialized. @@ -915,7 +915,7 @@ pmap_page_table_page_alloc() /* * Allocate a VM page for the level 2 page table entries. */ - while ((m = vm_page_grab()) == VM_PAGE_NULL) + while ((m = vm_page_grab(FALSE)) == VM_PAGE_NULL) VM_PAGE_WAIT((void (*)()) 0); /* @@ -1126,7 +1126,7 @@ void pmap_remove_range(pmap, va, spte, e #if DEBUG_PTE_PAGE if (pmap != kernel_pmap) ptep_check(get_pte_page(spte)); -#endif DEBUG_PTE_PAGE +#endif /* DEBUG_PTE_PAGE */ num_removed = 0; num_unwired = 0; @@ -1657,7 +1657,7 @@ Retry: /* * May be changing its wired attribute or protection */ - + if (wired && !(*pte & INTEL_PTE_WIRED)) pmap->stats.wired_count++; else if (!wired && (*pte & INTEL_PTE_WIRED)) @@ -1730,8 +1730,8 @@ Retry: e = e->next; } } -#endif DEBUG - +#endif /* DEBUG */ + /* * Add new pv_entry after header. */ @@ -1888,9 +1888,9 @@ void pmap_copy(dst_pmap, src_pmap, dst_a { #ifdef lint dst_pmap++; src_pmap++; dst_addr++; len++; src_addr++; -#endif lint +#endif /* lint */ } -#endif 0 +#endif /* 0 */ /* * Routine: pmap_collect @@ -2014,7 +2014,7 @@ void pmap_activate(my_pmap, th, my_cpu) { PMAP_ACTIVATE(my_pmap, th, my_cpu); } -#endif 0 +#endif /* 0 */ /* * Routine: pmap_deactivate @@ -2031,10 +2031,10 @@ void pmap_deactivate(pmap, th, which_cpu { #ifdef lint pmap++; th++; which_cpu++; -#endif lint +#endif /* lint */ PMAP_DEACTIVATE(pmap, th, which_cpu); } -#endif 0 +#endif /* 0 */ /* * Routine: pmap_kernel @@ -2046,7 +2046,7 @@ pmap_t pmap_kernel() { return (kernel_pmap); } -#endif 0 +#endif /* 0 */ /* * pmap_zero_page zeros the specified (machine independent) page. @@ -2065,7 +2065,7 @@ pmap_zero_page(phys) while (i--) zero_phys(phys++); } -#endif 0 +#endif /* 0 */ /* * pmap_copy_page copies the specified (machine independent) page. @@ -2087,7 +2087,7 @@ pmap_copy_page(src, dst) dst += INTEL_PGBYTES; } } -#endif 0 +#endif /* 0 */ /* * Routine: pmap_pageable @@ -2111,7 +2111,7 @@ pmap_pageable(pmap, start, end, pageable { #ifdef lint pmap++; start++; end++; pageable++; -#endif lint +#endif /* lint */ } /* @@ -2344,7 +2344,7 @@ boolean_t pmap_is_referenced(phys) #if NCPUS > 1 /* * TLB Coherence Code (TLB "shootdown" code) -* +* * Threads that belong to the same task share the same address space and * hence share a pmap. However, they may run on distinct cpus and thus * have distinct TLBs that cache page table entries. In order to guarantee @@ -2357,7 +2357,7 @@ boolean_t pmap_is_referenced(phys) * flush its own TLB; a processor that needs to invalidate another TLB * needs to interrupt the processor that owns that TLB to signal the * update. -* +* * Whenever a pmap is updated, the lock on that pmap is locked, and all * cpus using the pmap are signaled to invalidate. All threads that need * to activate a pmap must wait for the lock to clear to await any updates @@ -2366,7 +2366,7 @@ boolean_t pmap_is_referenced(phys) * throughout the TLB code is that all kernel code that runs at or higher * than splvm blocks out update interrupts, and that such code does not * touch pageable pages. -* +* * A shootdown interrupt serves another function besides signaling a * processor to invalidate. The interrupt routine (pmap_update_interrupt) * waits for the both the pmap lock (and the kernel pmap lock) to clear, @@ -2379,17 +2379,17 @@ boolean_t pmap_is_referenced(phys) * Spinning on the VALUES of the locks is sufficient (rather than * having to acquire the locks) because any updates that occur subsequent * to finding the lock unlocked will be signaled via another interrupt. -* (This assumes the interrupt is cleared before the low level interrupt code -* calls pmap_update_interrupt()). -* +* (This assumes the interrupt is cleared before the low level interrupt code +* calls pmap_update_interrupt()). +* * The signaling processor must wait for any implicit updates in progress * to terminate before continuing with its update. Thus it must wait for an * acknowledgement of the interrupt from each processor for which such * references could be made. For maintaining this information, a set -* cpus_active is used. A cpu is in this set if and only if it can +* cpus_active is used. A cpu is in this set if and only if it can * use a pmap. When pmap_update_interrupt() is entered, a cpu is removed from * this set; when all such cpus are removed, it is safe to update. -* +* * Before attempting to acquire the update lock on a pmap, a cpu (A) must * be at least at the priority of the interprocessor interrupt * (splip<=splvm). Otherwise, A could grab a lock and be interrupted by a @@ -2525,10 +2525,10 @@ void pmap_update_interrupt() i_bit_set(my_cpu, &cpus_active); } while (cpu_update_needed[my_cpu]); - + splx(s); } -#else NCPUS > 1 +#else /* NCPUS > 1 */ /* * Dummy routine to satisfy external reference. */ @@ -2536,7 +2536,7 @@ void pmap_update_interrupt() { /* should never be called. */ } -#endif NCPUS > 1 +#endif /* NCPUS > 1 */ #if i860 /* akp */ void set_dirbase(dirbase) @@ -2546,7 +2546,7 @@ void set_dirbase(dirbase) /*flush_tlb();*/ flush_and_ctxsw(dirbase); } -#endif i860 +#endif /* i860 */ #ifdef i386 /* Unmap page 0 to trap NULL references. */