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Annotation of Gnu-Mach/i386/pc/irq.h, revision 1.1.1.1

1.1       root        1: /* 
                      2:  * Copyright (c) 1995 The University of Utah and
                      3:  * the Computer Systems Laboratory at the University of Utah (CSL).
                      4:  * All rights reserved.
                      5:  *
                      6:  * Permission to use, copy, modify and distribute this software is hereby
                      7:  * granted provided that (1) source code retains these copyright, permission,
                      8:  * and disclaimer notices, and (2) redistributions including binaries
                      9:  * reproduce the notices in supporting documentation, and (3) all advertising
                     10:  * materials mentioning features or use of this software display the following
                     11:  * acknowledgement: ``This product includes software developed by the
                     12:  * Computer Systems Laboratory at the University of Utah.''
                     13:  *
                     14:  * THE UNIVERSITY OF UTAH AND CSL ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS
                     15:  * IS" CONDITION.  THE UNIVERSITY OF UTAH AND CSL DISCLAIM ANY LIABILITY OF
                     16:  * ANY KIND FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
                     17:  *
                     18:  * CSL requests users of this software to return to [email protected] any
                     19:  * improvements that they make and grant CSL redistribution rights.
                     20:  *
                     21:  *      Author: Bryan Ford, University of Utah CSL
                     22:  */
                     23: #ifndef _I386_PC_IRQ_H_
                     24: #define _I386_PC_IRQ_H_
                     25: 
                     26: /* On normal PCs, there are always 16 IRQ lines.  */
                     27: #define IRQ_COUNT 16
                     28: 
                     29: /* Start of hardware interrupt vectors in the IDT.  */
                     30: #define IDT_IRQ_BASE 0x20
                     31: 
                     32: /* Variables storing the master and slave PIC interrupt vector base.  */
                     33: extern int irq_master_base, irq_slave_base;
                     34: 
                     35: /* Routine called just after entering protected mode for the first time,
                     36:    to set up the IRQ interrupt vectors in the protected-mode IDT.
                     37:    It should initialize IDT entries irq_master_base through irq_master_base+7,
                     38:    and irq_slave_base through irq_slave_base+7.  */
                     39: extern void idt_irq_init(void);
                     40: 
                     41: /* Fill an IRQ gate in a CPU's IDT.
                     42:    Always uses an interrupt gate; just set `access' to the privilege level.  */
                     43: #define fill_irq_gate(cpu, irq_num, entry, selector, access)                   \
                     44:        fill_idt_gate(cpu, (irq_num) < 8                                        \
                     45:                           ? irq_master_base+(irq_num)                          \
                     46:                           : irq_slave_base+(irq_num)-8,                        \
                     47:                  entry, selector, ACC_INTR_GATE | (access))
                     48: 
                     49: #endif _I386_PC_IRQ_H_

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