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1.1 root 1: /*
2: * Mach Operating System
3: * Copyright (c) 1991,1990,1989 Carnegie Mellon University
4: * All Rights Reserved.
5: *
6: * Permission to use, copy, modify and distribute this software and its
7: * documentation is hereby granted, provided that both the copyright
8: * notice and this permission notice appear in all copies of the
9: * software, derivative works or modified versions, and any portions
10: * thereof, and that both notices appear in supporting documentation.
11: *
12: * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
13: * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
14: * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
15: *
16: * Carnegie Mellon requests users of this software to return to
17: *
18: * Software Distribution Coordinator or [email protected]
19: * School of Computer Science
20: * Carnegie Mellon University
21: * Pittsburgh PA 15213-3890
22: *
23: * any improvements or extensions that they make and grant Carnegie Mellon
24: * the rights to redistribute these changes.
25: */
26: /*
27: Copyright (c) 1988,1989 Prime Computer, Inc. Natick, MA 01760
28: All Rights Reserved.
29:
30: Permission to use, copy, modify, and distribute this
31: software and its documentation for any purpose and
32: without fee is hereby granted, provided that the above
33: copyright notice appears in all copies and that both the
34: copyright notice and this permission notice appear in
35: supporting documentation, and that the name of Prime
36: Computer, Inc. not be used in advertising or publicity
37: pertaining to distribution of the software without
38: specific, written prior permission.
39:
40: THIS SOFTWARE IS PROVIDED "AS IS", AND PRIME COMPUTER,
41: INC. DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS
42: SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
43: MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN
44: NO EVENT SHALL PRIME COMPUTER, INC. BE LIABLE FOR ANY
45: SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY
46: DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
47: PROFITS, WHETHER IN ACTION OF CONTRACT, NEGLIGENCE, OR
48: OTHER TORTIOUS ACTION, ARISING OUR OF OR IN CONNECTION
49: WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
50: */
51:
52: #ifndef _I386_PIC_H_
53: #define _I386_PIC_H_
54:
55: #include "irq.h"
56:
57: #define NINTR 0x10
58: #define NPICS 0x02
59:
60: /*
61: ** The following are definitions used to locate the PICs in the system
62: */
63:
64: #define ADDR_PIC_BASE 0x20
65: #define OFF_ICW 0x00
66: #define OFF_OCW 0x01
67: #define SIZE_PIC 0x80
68:
69: #define MASTER_ICW (ADDR_PIC_BASE + OFF_ICW)
70: #define MASTER_OCW (ADDR_PIC_BASE + OFF_OCW)
71: #define SLAVES_ICW (ADDR_PIC_BASE + OFF_ICW + SIZE_PIC)
72: #define SLAVES_OCW (ADDR_PIC_BASE + OFF_OCW + SIZE_PIC)
73:
74: /*
75: ** The following banks of definitions ICW1, ICW2, ICW3, and ICW4 are used
76: ** to define the fields of the various ICWs for initialisation of the PICs
77: */
78:
79: /*
80: ** ICW1
81: */
82:
83: #define ICW_TEMPLATE 0x10
84:
85: #define LEVL_TRIGGER 0x08
86: #define EDGE_TRIGGER 0x00
87: #define ADDR_INTRVL4 0x04
88: #define ADDR_INTRVL8 0x00
89: #define SINGLE__MODE 0x02
90: #define CASCADE_MODE 0x00
91: #define ICW4__NEEDED 0x01
92: #define NO_ICW4_NEED 0x00
93:
94: /*
95: ** ICW2
96: */
97:
98: #define PICM_VECTBASE IDT_IRQ_BASE
99: #define PICS_VECTBASE (PICM_VECTBASE + 0x08)
100:
101: /*
102: ** ICW3
103: */
104:
105: #define SLAVE_ON_IR0 0x01
106: #define SLAVE_ON_IR1 0x02
107: #define SLAVE_ON_IR2 0x04
108: #define SLAVE_ON_IR3 0x08
109: #define SLAVE_ON_IR4 0x10
110: #define SLAVE_ON_IR5 0x20
111: #define SLAVE_ON_IR6 0x40
112: #define SLAVE_ON_IR7 0x80
113:
114: #define I_AM_SLAVE_0 0x00
115: #define I_AM_SLAVE_1 0x01
116: #define I_AM_SLAVE_2 0x02
117: #define I_AM_SLAVE_3 0x03
118: #define I_AM_SLAVE_4 0x04
119: #define I_AM_SLAVE_5 0x05
120: #define I_AM_SLAVE_6 0x06
121: #define I_AM_SLAVE_7 0x07
122:
123: /*
124: ** ICW4
125: */
126:
127: #define SNF_MODE_ENA 0x10
128: #define SNF_MODE_DIS 0x00
129: #define BUFFERD_MODE 0x08
130: #define NONBUFD_MODE 0x00
131: #define AUTO_EOI_MOD 0x02
132: #define NRML_EOI_MOD 0x00
133: #define I8086_EMM_MOD 0x01
134: #define SET_MCS_MODE 0x00
135:
136: /*
137: ** OCW1
138: */
139:
140: #define PICM_MASK 0xFF
141: #define PICS_MASK 0xFF
142:
143: /*
144: ** OCW2
145: */
146:
147: #define NON_SPEC_EOI 0x20
148: #define SPECIFIC_EOI 0x30
149: #define ROT_NON_SPEC 0x50
150: #define SET_ROT_AEOI 0x40
151: #define RSET_ROTAEOI 0x00
152: #define ROT_SPEC_EOI 0x70
153: #define SET_PRIORITY 0x60
154: #define NO_OPERATION 0x20
155:
156: #define SEND_EOI_IR0 0x00
157: #define SEND_EOI_IR1 0x01
158: #define SEND_EOI_IR2 0x02
159: #define SEND_EOI_IR3 0x03
160: #define SEND_EOI_IR4 0x04
161: #define SEND_EOI_IR5 0x05
162: #define SEND_EOI_IR6 0x06
163: #define SEND_EOI_IR7 0x07
164:
165: /*
166: ** OCW3
167: */
168:
169: #define OCW_TEMPLATE 0x08
170: #define SPECIAL_MASK 0x40
171: #define MASK_MDE_SET 0x20
172: #define MASK_MDE_RST 0x00
173: #define POLL_COMMAND 0x04
174: #define NO_POLL_CMND 0x00
175: #define READ_NEXT_RD 0x02
176: #define READ_IR_ONRD 0x00
177: #define READ_IS_ONRD 0x01
178:
179:
180: /*
181: ** Standard PIC initialization values for PCs.
182: */
183: #define PICM_ICW1 (ICW_TEMPLATE | EDGE_TRIGGER | ADDR_INTRVL8 \
184: | CASCADE_MODE | ICW4__NEEDED)
185: #define PICM_ICW3 (SLAVE_ON_IR2)
186: #define PICM_ICW4 (SNF_MODE_DIS | NONBUFD_MODE | NRML_EOI_MOD \
187: | I8086_EMM_MOD)
188:
189: #define PICS_ICW1 (ICW_TEMPLATE | EDGE_TRIGGER | ADDR_INTRVL8 \
190: | CASCADE_MODE | ICW4__NEEDED)
191: #define PICS_ICW3 (I_AM_SLAVE_2)
192: #define PICS_ICW4 (SNF_MODE_DIS | NONBUFD_MODE | NRML_EOI_MOD \
193: | I8086_EMM_MOD)
194:
195: /* Some systems need a little bit of delay
196: while fiddling with PIC registers. */
197: #ifndef ASSEMBLER
198: #define PIC_DELAY() asm volatile("jmp 1f; 1: jmp 1f; 1:")
199: #else
200: #define PIC_DELAY jmp 9f; 9: jmp 9f; 9:
201: #endif
202:
203:
204: #endif _I386_PIC_H_
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