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1.1 root 1: /*
2: * Copyright (c) 1995-1994 The University of Utah and
3: * the Computer Systems Laboratory at the University of Utah (CSL).
4: * All rights reserved.
5: *
6: * Permission to use, copy, modify and distribute this software is hereby
7: * granted provided that (1) source code retains these copyright, permission,
8: * and disclaimer notices, and (2) redistributions including binaries
9: * reproduce the notices in supporting documentation, and (3) all advertising
10: * materials mentioning features or use of this software display the following
11: * acknowledgement: ``This product includes software developed by the
12: * Computer Systems Laboratory at the University of Utah.''
13: *
14: * THE UNIVERSITY OF UTAH AND CSL ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS
15: * IS" CONDITION. THE UNIVERSITY OF UTAH AND CSL DISCLAIM ANY LIABILITY OF
16: * ANY KIND FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
17: *
18: * CSL requests users of this software to return to [email protected] any
19: * improvements that they make and grant CSL redistribution rights.
20: *
21: * Author: Bryan Ford, University of Utah CSL
22: */
23:
24: #include <mach/machine/seg.h>
25: #include <mach/machine/proc_reg.h>
26:
27: #include "vm_param.h"
28: #include "cpu.h"
29:
30: struct idt_init_entry
31: {
32: unsigned entrypoint;
33: unsigned short vector;
34: unsigned short type;
35: };
36: extern struct idt_init_entry idt_inittab[];
37:
38: void cpu_idt_init(struct cpu *cpu)
39: {
40: struct idt_init_entry *iie = idt_inittab;
41:
42: /* Initialize the trap/interrupt vectors from the idt_inittab. */
43: while (iie->entrypoint)
44: {
45: fill_idt_gate(cpu, iie->vector, iie->entrypoint,
46: KERNEL_CS, iie->type);
47: iie++;
48: }
49: }
50:
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