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1.1 root 1: /*
2: * Copyright (C) 2013 Free Software Foundation
3: *
4: * This program is free software ; you can redistribute it and/or modify
5: * it under the terms of the GNU General Public License as published by
6: * the Free Software Foundation ; either version 2 of the License, or
7: * (at your option) any later version.
8: *
9: * This program is distributed in the hope that it will be useful,
10: * but WITHOUT ANY WARRANTY ; without even the implied warranty of
11: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12: * GNU General Public License for more details.
13: *
14: * You should have received a copy of the GNU General Public License
15: * along with the program ; if not, write to the Free Software
16: * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17: */
18:
19: #include <ahci.h>
20: #include <kern/assert.h>
21: #include <linux/kernel.h>
22: #include <linux/types.h>
23: #include <linux/pci.h>
24: #include <linux/fs.h>
25: #include <linux/bios32.h>
26: #include <linux/major.h>
27: #include <linux/hdreg.h>
28: #include <linux/genhd.h>
29: #include <asm/io.h>
30:
31: #define MAJOR_NR SCSI_DISK_MAJOR
32: #include <linux/blk.h>
33:
34: /* Standard AHCI BAR for mmio */
35: #define AHCI_PCI_BAR 5
36:
37: /* minor: 2 bits for device number, 6 bits for partition number. */
38:
1.1.1.2 root 39: #define MAX_PORTS 8
40: #define PARTN_BITS 5
1.1 root 41: #define PARTN_MASK ((1<<PARTN_BITS)-1)
42:
43: /* We need to use one DMA scatter element per physical page.
44: * ll_rw_block creates at most 8 buffer heads */
45: /* See MAX_BUF */
46: #define PRDTL_SIZE 8
47:
48: #define WAIT_MAX (1*HZ) /* Wait at most 1s for requests completion */
49:
50: /* AHCI standard structures */
51:
52: struct ahci_prdt {
53: u32 dba; /* Data base address */
54: u32 dbau; /* upper 32bit */
55: u32 rsv0; /* Reserved */
56:
57: u32 dbc; /* Byte count bits 0-21,
58: * bit31 interrupt on completion. */
59: };
60:
61: struct ahci_cmd_tbl {
62: u8 cfis[64];
63: u8 acmd[16];
64: u8 rsv[48];
65:
66: struct ahci_prdt prdtl[PRDTL_SIZE];
67: };
68:
69: struct ahci_command {
70: u32 opts; /* Command options */
71:
72: u32 prdbc; /* Physical Region Descriptor byte count */
73:
74: u32 ctba; /* Command Table Descriptor Base Address */
75: u32 ctbau; /* upper 32bit */
76:
77: u32 rsv1[4]; /* Reserved */
78: };
79:
80: struct ahci_fis_dma {
81: u8 fis_type;
82: u8 flags;
83: u8 rsved[2];
84: u64 id;
85: u32 rsvd;
86: u32 offset;
87: u32 count;
88: u32 resvd;
89: };
90:
91: struct ahci_fis_pio {
92: u8 fis_type;
93: u8 flags;
94: u8 status;
95: u8 error;
96:
97: u8 lba0;
98: u8 lba1;
99: u8 lba2;
100: u8 device;
101:
102: u8 lba3;
103: u8 lba4;
104: u8 lba5;
105: u8 rsv2;
106:
107: u8 countl;
108: u8 counth;
109: u8 rsv3;
110: u8 e_status;
111:
112: u16 tc; /* Transfer Count */
113: u8 rsv4[2];
114: };
115:
116: struct ahci_fis_d2h {
117: u8 fis_type;
118: u8 flags;
119: u8 status;
120: u8 error;
121:
122: u8 lba0;
123: u8 lba1;
124: u8 lba2;
125: u8 device;
126:
127: u8 lba3;
128: u8 lba4;
129: u8 lba5;
130: u8 rsv2;
131:
132: u8 countl;
133: u8 counth;
134: u8 rsv3[2];
135:
136: u8 rsv4[4];
137: };
138:
139: struct ahci_fis_dev {
140: u8 rsvd[8];
141: };
142:
143: struct ahci_fis_h2d {
144: u8 fis_type;
145: u8 flags;
146: u8 command;
147: u8 featurel;
148:
149: u8 lba0;
150: u8 lba1;
151: u8 lba2;
152: u8 device;
153:
154: u8 lba3;
155: u8 lba4;
156: u8 lba5;
157: u8 featureh;
158:
159: u8 countl;
160: u8 counth;
161: u8 icc;
162: u8 control;
163:
164: u8 rsv1[4];
165: };
166:
167: struct ahci_fis_data {
168: u8 fis_type;
169: u8 flags;
170: u8 rsv1[2];
171: u32 data1[];
172: };
173:
174: struct ahci_fis {
175: struct ahci_fis_dma dma_fis;
176: u8 pad0[4];
177:
178: struct ahci_fis_pio pio_fis;
179: u8 pad1[12];
180:
181: struct ahci_fis_d2h d2h_fis;
182: u8 pad2[4];
183:
184: struct ahci_fis_dev dev_fis;
185:
186: u8 ufis[64];
187:
188: u8 rsv[0x100 - 0xa0];
189: };
190:
191: struct ahci_port {
192: u32 clb; /* Command List Base address */
193: u32 clbu; /* upper 32bit */
194: u32 fb; /* FIS Base */
195: u32 fbu; /* upper 32bit */
196: u32 is; /* Interrupt Status */
197: u32 ie; /* Interrupt Enable */
198: u32 cmd; /* Command and Status */
199: u32 rsv0; /* Reserved */
200: u32 tfd; /* Task File Data */
201: u32 sig; /* Signature */
202: u32 ssts; /* SATA Status */
203: u32 sctl; /* SATA Control */
204: u32 serr; /* SATA Error */
205: u32 sact; /* SATA Active */
206: u32 ci; /* Command Issue */
207: u32 sntf; /* SATA Notification */
208: u32 fbs; /* FIS-based switch control */
209: u8 rsv1[0x70 - 0x44]; /* Reserved */
210: u8 vendor[0x80 - 0x70]; /* Vendor-specific */
211: };
212:
213: struct ahci_host {
214: u32 cap; /* Host capabilities */
215: u32 ghc; /* Global Host Control */
216: u32 is; /* Interrupt Status */
217: u32 pi; /* Port Implemented */
218: u32 v; /* Version */
219: u32 ccc_ctl; /* Command Completion Coalescing control */
220: u32 ccc_pts; /* Command Completion Coalescing ports */
221: u32 em_loc; /* Enclosure Management location */
222: u32 em_ctrl; /* Enclosure Management control */
223: u32 cap2; /* Host capabilities extended */
224: u32 bohc; /* BIOS/OS Handoff Control and status */
225: u8 rsv[0xa0 - 0x2c]; /* Reserved */
226: u8 vendor[0x100 - 0xa0]; /* Vendor-specific */
227: struct ahci_port ports[]; /* Up to 32 ports */
228: };
229:
230: /* Our own data */
231:
232: static struct port {
233: /* memory-mapped regions */
234: const volatile struct ahci_host *ahci_host;
235: const volatile struct ahci_port *ahci_port;
236:
237: /* host-memory buffers */
238: struct ahci_command *command;
239: struct ahci_fis *fis;
240: struct ahci_cmd_tbl *prdtl;
241:
1.1.1.2 root 242: struct hd_driveid id;
243: unsigned is_cd;
1.1 root 244: unsigned long long capacity; /* Nr of sectors */
245: u32 status; /* interrupt status */
246: unsigned cls; /* Command list maximum size.
247: We currently only use 1. */
248: struct wait_queue *q; /* IRQ wait queue */
249: struct hd_struct *part; /* drive partition table */
250: unsigned lba48; /* Whether LBA48 is supported */
251: unsigned identify; /* Whether we are just identifying
252: at boot */
253: struct gendisk *gd;
254: } ports[MAX_PORTS];
255:
256:
257: /* do_request() gets called by the block layer to push a request to the disk.
258: We just push one, and when an interrupt tells it's over, we call do_request()
259: ourself again to push the next request, etc. */
260:
261: /* Request completed, either successfully or with an error */
262: static void ahci_end_request(int uptodate)
263: {
264: struct request *rq = CURRENT;
265: struct buffer_head *bh;
266:
267: rq->errors = 0;
268: if (!uptodate) {
1.1.1.2 root 269: if (!rq->quiet)
270: printk("end_request: I/O error, dev %s, sector %lu\n",
271: kdevname(rq->rq_dev), rq->sector);
1.1 root 272: }
273:
274: for (bh = rq->bh; bh; )
275: {
276: struct buffer_head *next = bh->b_reqnext;
277: bh->b_reqnext = NULL;
278: mark_buffer_uptodate (bh, uptodate);
279: unlock_buffer (bh);
280: bh = next;
281: }
282:
283: CURRENT = rq->next;
284: if (rq->sem != NULL)
285: up(rq->sem);
286: rq->rq_status = RQ_INACTIVE;
287: wake_up(&wait_for_request);
288: }
289:
290: /* Push the request to the controler port */
1.1.1.2 root 291: static void ahci_do_port_request(struct port *port, unsigned long long sector, struct request *rq)
1.1 root 292: {
293: struct ahci_command *command = port->command;
294: struct ahci_cmd_tbl *prdtl = port->prdtl;
295: struct ahci_fis_h2d *fis_h2d;
296: unsigned slot = 0;
297: struct buffer_head *bh;
298: unsigned i;
299:
300: rq->rq_status = RQ_SCSI_BUSY;
301:
302: /* Shouldn't ever happen: the block glue is limited at 8 blocks */
303: assert(rq->nr_sectors < 0x10000);
304:
305: fis_h2d = (void*) &prdtl[slot].cfis;
306: fis_h2d->fis_type = FIS_TYPE_REG_H2D;
307: fis_h2d->flags = 128;
308: if (port->lba48)
309: if (rq->cmd == READ)
310: fis_h2d->command = WIN_READDMA_EXT;
311: else
312: fis_h2d->command = WIN_WRITEDMA_EXT;
313: else
314: if (rq->cmd == READ)
315: fis_h2d->command = WIN_READDMA;
316: else
317: fis_h2d->command = WIN_WRITEDMA;
318:
319: fis_h2d->device = 1<<6; /* LBA */
320:
321: fis_h2d->lba0 = sector;
322: fis_h2d->lba1 = sector >> 8;
323: fis_h2d->lba2 = sector >> 16;
324:
325: fis_h2d->lba3 = sector >> 24;
1.1.1.2 root 326: fis_h2d->lba4 = sector >> 32;
327: fis_h2d->lba5 = sector >> 40;
1.1 root 328:
329: fis_h2d->countl = rq->nr_sectors;
330: fis_h2d->counth = rq->nr_sectors >> 8;
331:
332: command[slot].opts = sizeof(*fis_h2d) / sizeof(u32);
333:
334: if (rq->cmd == WRITE)
335: command[slot].opts |= AHCI_CMD_WRITE;
336:
337: for (i = 0, bh = rq->bh; bh; i++, bh = bh->b_reqnext)
338: {
339: assert(i < PRDTL_SIZE);
340: assert((((unsigned long) bh->b_data) & ~PAGE_MASK) ==
341: (((unsigned long) bh->b_data + bh->b_size - 1) & ~PAGE_MASK));
342: prdtl[slot].prdtl[i].dbau = 0;
343: prdtl[slot].prdtl[i].dba = vmtophys(bh->b_data);
344: prdtl[slot].prdtl[i].dbc = bh->b_size - 1;
345: }
346:
347: command[slot].opts |= i << 16;
348:
349: /* Make sure main memory buffers are up to date */
350: mb();
351:
352: /* Issue command */
353: writel(1 << slot, &port->ahci_port->ci);
354:
355: /* TODO: IRQ timeout handler */
356: }
357:
358: /* Called by block core to push a request */
359: /* TODO: ideally, would have one request queue per port */
360: /* TODO: ideally, would use tags to process several requests at a time */
361: static void ahci_do_request() /* invoked with cli() */
362: {
363: struct request *rq;
364: unsigned minor, unit;
1.1.1.2 root 365: unsigned long long block, blockend;
1.1 root 366: struct port *port;
367:
368: rq = CURRENT;
369: if (!rq)
370: return;
371:
372: if (rq->rq_status != RQ_ACTIVE)
373: /* Current one is already ongoing, let the interrupt handler
374: * push the new one when the current one is finished. */
375: return;
376:
377: if (MAJOR(rq->rq_dev) != MAJOR_NR) {
378: printk("bad ahci major %u\n", MAJOR(rq->rq_dev));
379: goto kill_rq;
380: }
381:
382: minor = MINOR(rq->rq_dev);
383: unit = minor >> PARTN_BITS;
384: if (unit > MAX_PORTS) {
385: printk("bad ahci unit %u\n", unit);
386: goto kill_rq;
387: }
388:
389: port = &ports[unit];
390:
391: /* Compute start sector */
392: block = rq->sector;
393: block += port->part[minor & PARTN_MASK].start_sect;
394:
395: /* And check end */
396: blockend = block + rq->nr_sectors;
397: if (blockend < block) {
1.1.1.2 root 398: if (!rq->quiet)
399: printk("bad blockend %lu vs %lu\n", (unsigned long) blockend, (unsigned long) block);
1.1 root 400: goto kill_rq;
401: }
402: if (blockend > port->capacity) {
1.1.1.2 root 403: if (!rq->quiet)
404: {
405: printk("offset for %u was %lu\n", minor, port->part[minor & PARTN_MASK].start_sect);
406: printk("bad access: block %lu, count= %lu\n", (unsigned long) blockend, (unsigned long) port->capacity);
407: }
1.1 root 408: goto kill_rq;
409: }
410:
411: /* Push this to the port */
412: ahci_do_port_request(port, block, rq);
413: return;
414:
415: kill_rq:
416: ahci_end_request(0);
417: }
418:
419: /* The given port got an interrupt, terminate the current request if any */
420: static void ahci_port_interrupt(struct port *port, u32 status)
421: {
422: unsigned slot = 0;
423:
424: if (readl(&port->ahci_port->ci) & (1 << slot)) {
425: /* Command still pending */
426: return;
427: }
428:
429: if (port->identify) {
430: port->status = status;
431: wake_up(&port->q);
432: return;
433: }
434:
435: if (!CURRENT || CURRENT->rq_status != RQ_SCSI_BUSY) {
436: /* No request currently running */
437: return;
438: }
439:
440: if (status & (PORT_IRQ_TF_ERR | PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR | PORT_IRQ_IF_ERR | PORT_IRQ_IF_NONFATAL)) {
441: printk("ahci error %x %x\n", status, readl(&port->ahci_port->tfd));
442: ahci_end_request(0);
443: return;
444: }
445:
446: ahci_end_request(1);
447: }
448:
449: /* Start of IRQ handler. Iterate over all ports for this host */
450: static void ahci_interrupt (int irq, void *host, struct pt_regs *regs)
451: {
452: struct port *port;
453: struct ahci_host *ahci_host = host;
454: u32 irq_mask;
455: u32 status;
456:
457: irq_mask = readl(&ahci_host->is);
458:
459: if (!irq_mask)
460: return;
461:
462: for (port = &ports[0]; port < &ports[MAX_PORTS]; port++) {
463: if (port->ahci_host == ahci_host && (irq_mask & (1 << (port->ahci_port - ahci_host->ports)))) {
464: status = readl(&port->ahci_port->is);
465: /* Clear interrupt before possibly triggering others */
466: writel(status, &port->ahci_port->is);
467: ahci_port_interrupt (port, status);
468: }
469: }
470:
471: if (CURRENT)
472: /* Still some requests, queue another one */
473: ahci_do_request();
474:
475: /* Clear host after clearing ports */
476: writel(irq_mask, &ahci_host->is);
477:
478: /* unlock */
479: }
480:
481: static int ahci_ioctl (struct inode *inode, struct file *file,
482: unsigned int cmd, unsigned long arg)
483: {
484: int major, unit;
485:
486: if (!inode || !inode->i_rdev)
487: return -EINVAL;
488:
489: major = MAJOR(inode->i_rdev);
490: if (major != MAJOR_NR)
491: return -ENOTTY;
492:
493: unit = DEVICE_NR(inode->i_rdev);
494: if (unit >= MAX_PORTS)
495: return -EINVAL;
496:
497: switch (cmd) {
498: case BLKRRPART:
499: if (!suser()) return -EACCES;
500: if (!ports[unit].gd)
501: return -EINVAL;
502: resetup_one_dev(ports[unit].gd, unit);
503: return 0;
504: default:
505: return -EPERM;
506: }
507: }
508:
509: static int ahci_open (struct inode *inode, struct file *file)
510: {
511: int target;
512:
513: if (MAJOR(inode->i_rdev) != MAJOR_NR)
514: return -ENXIO;
515:
516: target = MINOR(inode->i_rdev) >> PARTN_BITS;
517: if (target >= MAX_PORTS)
518: return -ENXIO;
519:
520: if (!ports[target].ahci_port)
521: return -ENXIO;
522:
523: return 0;
524: }
525:
526: static void ahci_release (struct inode *inode, struct file *file)
527: {
528: }
529:
530: static int ahci_fsync (struct inode *inode, struct file *file)
531: {
532: printk("fsync\n");
533: return -ENOSYS;
534: }
535:
536: static struct file_operations ahci_fops = {
537: .lseek = NULL,
538: .read = block_read,
539: .write = block_write,
540: .readdir = NULL,
541: .select = NULL,
542: .ioctl = ahci_ioctl,
543: .mmap = NULL,
544: .open = ahci_open,
545: .release = ahci_release,
546: .fsync = ahci_fsync,
547: .fasync = NULL,
548: .check_media_change = NULL,
549: .revalidate = NULL,
550: };
551:
552: /* Disk timed out while processing identify, interrupt ahci_probe_port */
553: static void identify_timeout(unsigned long data)
554: {
555: struct port *port = (void*) data;
556:
557: wake_up(&port->q);
558: }
559:
560: static struct timer_list identify_timer = { .function = identify_timeout };
561:
1.1.1.2 root 562: static int ahci_identify(const volatile struct ahci_host *ahci_host, const volatile struct ahci_port *ahci_port, struct port *port, unsigned cmd)
1.1 root 563: {
564: struct hd_driveid id;
565: struct ahci_fis_h2d *fis_h2d;
1.1.1.2 root 566: struct ahci_command *command = port->command;
567: struct ahci_cmd_tbl *prdtl = port->prdtl;
568: unsigned long flags;
1.1 root 569: unsigned slot;
570: unsigned long first_part;
571: unsigned long long timeout;
1.1.1.2 root 572: int ret = 0;
1.1 root 573:
574: /* Identify device */
575: /* TODO: make this a request */
576: slot = 0;
577:
578: fis_h2d = (void*) &prdtl[slot].cfis;
579: fis_h2d->fis_type = FIS_TYPE_REG_H2D;
580: fis_h2d->flags = 128;
1.1.1.2 root 581: fis_h2d->command = cmd;
1.1 root 582: fis_h2d->device = 0;
583:
584: /* Fetch the 512 identify data */
585: memset(&id, 0, sizeof(id));
586:
587: command[slot].opts = sizeof(*fis_h2d) / sizeof(u32);
588:
589: first_part = PAGE_ALIGN((unsigned long) &id) - (unsigned long) &id;
590:
591: if (first_part && first_part < sizeof(id)) {
592: /* split over two pages */
593:
594: command[slot].opts |= (2 << 16);
595:
596: prdtl[slot].prdtl[0].dbau = 0;
597: prdtl[slot].prdtl[0].dba = vmtophys((void*) &id);
598: prdtl[slot].prdtl[0].dbc = first_part - 1;
599: prdtl[slot].prdtl[1].dbau = 0;
600: prdtl[slot].prdtl[1].dba = vmtophys((void*) &id + first_part);
601: prdtl[slot].prdtl[1].dbc = sizeof(id) - first_part - 1;
602: }
603: else
604: {
605: command[slot].opts |= (1 << 16);
606:
607: prdtl[slot].prdtl[0].dbau = 0;
608: prdtl[slot].prdtl[0].dba = vmtophys((void*) &id);
609: prdtl[slot].prdtl[0].dbc = sizeof(id) - 1;
610: }
611:
612: timeout = jiffies + WAIT_MAX;
613: while (readl(&ahci_port->tfd) & (BUSY_STAT | DRQ_STAT))
614: if (jiffies > timeout) {
615: printk("sd%u: timeout waiting for ready\n", port-ports);
616: port->ahci_host = NULL;
617: port->ahci_port = NULL;
1.1.1.2 root 618: return 3;
1.1 root 619: }
620:
621: save_flags(flags);
622: cli();
623:
624: port->identify = 1;
625: port->status = 0;
626:
627: /* Issue command */
628: mb();
629: writel(1 << slot, &ahci_port->ci);
630:
631: timeout = jiffies + WAIT_MAX;
632: identify_timer.expires = timeout;
633: identify_timer.data = (unsigned long) port;
634: add_timer(&identify_timer);
635: while (!port->status) {
636: if (jiffies >= timeout) {
637: printk("sd%u: timeout waiting for ready\n", port-ports);
638: port->ahci_host = NULL;
639: port->ahci_port = NULL;
640: del_timer(&identify_timer);
1.1.1.3 ! root 641: restore_flags(flags);
1.1.1.2 root 642: return 3;
1.1 root 643: }
644: sleep_on(&port->q);
645: }
646: del_timer(&identify_timer);
647: restore_flags(flags);
648:
1.1.1.2 root 649: if ((port->status & PORT_IRQ_TF_ERR) || readl(&ahci_port->is) & PORT_IRQ_TF_ERR)
1.1 root 650: {
1.1.1.2 root 651: /* Identify error */
1.1 root 652: port->capacity = 0;
653: port->lba48 = 0;
1.1.1.2 root 654: ret = 2;
1.1 root 655: } else {
1.1.1.2 root 656: memcpy(&port->id, &id, sizeof(id));
657: port->is_cd = 0;
658:
1.1 root 659: ide_fixstring(id.model, sizeof(id.model), 1);
660: ide_fixstring(id.fw_rev, sizeof(id.fw_rev), 1);
661: ide_fixstring(id.serial_no, sizeof(id.serial_no), 1);
1.1.1.2 root 662: if (cmd == WIN_PIDENTIFY)
663: {
664: unsigned char type = (id.config >> 8) & 0x1f;
665:
666: printk("sd%u: %s, ATAPI ", port - ports, id.model);
667: if (type == 5)
668: {
669: printk("unsupported CDROM drive\n");
670: port->is_cd = 1;
671: port->lba48 = 0;
672: port->capacity = 0;
673: }
674: else
675: {
676: printk("unsupported type %d\n", type);
677: port->lba48 = 0;
678: port->capacity = 0;
679: return 2;
680: }
681: return 0;
682: }
683:
1.1 root 684: if (id.command_set_2 & (1U<<10))
685: {
686: port->lba48 = 1;
687: port->capacity = id.lba_capacity_2;
688: if (port->capacity >= (1ULL << 32))
689: {
690: port->capacity = (1ULL << 32) - 1;
691: printk("Warning: truncating disk size to 2TiB\n");
692: }
693: }
694: else
695: {
696: port->lba48 = 0;
697: port->capacity = id.lba_capacity;
698: if (port->capacity > (1ULL << 24))
699: {
700: port->capacity = (1ULL << 24);
701: printk("Warning: truncating disk size to 128GiB\n");
702: }
703: }
704: if (port->capacity/2048 >= 10240)
705: printk("sd%u: %s, %uGB w/%dkB Cache\n", port - ports, id.model, (unsigned) (port->capacity/(2048*1024)), id.buf_size/2);
706: else
707: printk("sd%u: %s, %uMB w/%dkB Cache\n", port - ports, id.model, (unsigned) (port->capacity/2048), id.buf_size/2);
708: }
709: port->identify = 0;
1.1.1.2 root 710:
711: return ret;
712: }
713:
714: /* Probe one AHCI port */
715: static void ahci_probe_port(const volatile struct ahci_host *ahci_host, const volatile struct ahci_port *ahci_port)
716: {
717: struct port *port;
718: void *mem;
719: unsigned cls = ((readl(&ahci_host->cap) >> 8) & 0x1f) + 1;
720: struct ahci_command *command;
721: struct ahci_fis *fis;
722: struct ahci_cmd_tbl *prdtl;
723: vm_size_t size =
724: cls * sizeof(*command)
725: + sizeof(*fis)
726: + cls * sizeof(*prdtl);
727: unsigned i;
728: unsigned long long timeout;
729:
730: for (i = 0; i < MAX_PORTS; i++) {
731: if (!ports[i].ahci_port)
732: break;
733: }
734: if (i == MAX_PORTS)
735: return;
736: port = &ports[i];
737:
738: /* Has to be 1K-aligned */
739: mem = vmalloc (size);
740: if (!mem)
741: return;
742: assert (!(((unsigned long) mem) & (1024-1)));
743: memset (mem, 0, size);
744:
745: port->ahci_host = ahci_host;
746: port->ahci_port = ahci_port;
747: port->cls = cls;
748:
749: port->command = command = mem;
750: port->fis = fis = (void*) command + cls * sizeof(*command);
751: port->prdtl = prdtl = (void*) fis + sizeof(*fis);
752:
753: /* Stop commands */
754: writel(readl(&ahci_port->cmd) & ~PORT_CMD_START, &ahci_port->cmd);
755: timeout = jiffies + WAIT_MAX;
756: while (readl(&ahci_port->cmd) & PORT_CMD_LIST_ON)
757: if (jiffies > timeout) {
758: printk("sd%u: timeout waiting for list completion\n", port-ports);
759: port->ahci_host = NULL;
760: port->ahci_port = NULL;
761: return;
762: }
763:
764: writel(readl(&ahci_port->cmd) & ~PORT_CMD_FIS_RX, &ahci_port->cmd);
765: timeout = jiffies + WAIT_MAX;
766: while (readl(&ahci_port->cmd) & PORT_CMD_FIS_ON)
767: if (jiffies > timeout) {
768: printk("sd%u: timeout waiting for FIS completion\n", port-ports);
769: port->ahci_host = NULL;
770: port->ahci_port = NULL;
771: return;
772: }
773:
774: /* We don't support 64bit */
775: /* Point controller to our buffers */
776: writel(0, &ahci_port->clbu);
777: writel(vmtophys((void*) command), &ahci_port->clb);
778: writel(0, &ahci_port->fbu);
779: writel(vmtophys((void*) fis), &ahci_port->fb);
780:
781: /* Clear any previous interrupts */
782: writel(readl(&ahci_port->is), &ahci_port->is);
783: writel(1 << (ahci_port - ahci_host->ports), &ahci_host->is);
784:
785: /* And activate them */
786: writel(DEF_PORT_IRQ, &ahci_port->ie);
787: writel(readl(&ahci_host->ghc) | HOST_IRQ_EN, &ahci_host->ghc);
788:
789: for (i = 0; i < cls; i++)
790: {
791: command[i].ctbau = 0;
792: command[i].ctba = vmtophys((void*) &prdtl[i]);
793: }
794:
795: /* Start commands */
796: timeout = jiffies + WAIT_MAX;
797: while (readl(&ahci_port->cmd) & PORT_CMD_LIST_ON)
798: if (jiffies > timeout) {
799: printk("sd%u: timeout waiting for list completion\n", port-ports);
800: port->ahci_host = NULL;
801: port->ahci_port = NULL;
802: return;
803: }
804:
805: writel(readl(&ahci_port->cmd) | PORT_CMD_FIS_RX | PORT_CMD_START, &ahci_port->cmd);
806:
807: if (ahci_identify(ahci_host, ahci_port, port, WIN_IDENTIFY) >= 2)
808: /* Try ATAPI */
809: ahci_identify(ahci_host, ahci_port, port, WIN_PIDENTIFY);
1.1 root 810: }
811:
812: /* Probe one AHCI PCI device */
813: static void ahci_probe_dev(unsigned char bus, unsigned char device)
814: {
815: unsigned char hdrtype;
816: unsigned char dev, fun;
817: const volatile struct ahci_host *ahci_host;
818: const volatile struct ahci_port *ahci_port;
819: unsigned nports, n, i;
820: unsigned port_map;
821: unsigned bar;
822: unsigned char irq;
823:
824: dev = PCI_SLOT(device);
825: fun = PCI_FUNC(device);
826:
827: /* Get configuration */
828: if (pcibios_read_config_byte(bus, device, PCI_HEADER_TYPE, &hdrtype) != PCIBIOS_SUCCESSFUL) {
829: printk("ahci: %02u:%02u.%u: Can not read configuration", bus, dev, fun);
830: return;
831: }
832:
833: if (hdrtype != 0) {
834: printk("ahci: %02u:%02u.%u: Unknown hdrtype %d\n", bus, dev, fun, hdrtype);
835: return;
836: }
837:
838: if (pcibios_read_config_dword(bus, device, PCI_BASE_ADDRESS_5, &bar) != PCIBIOS_SUCCESSFUL) {
839: printk("ahci: %02u:%02u.%u: Can not read BAR 5", bus, dev, fun);
840: return;
841: }
842: if (bar & 0x01) {
843: printk("ahci: %02u:%02u.%u: BAR 5 is I/O?!", bus, dev, fun);
844: return;
845: }
846: bar &= ~0x0f;
847:
848: if (pcibios_read_config_byte(bus, device, PCI_INTERRUPT_LINE, &irq) != PCIBIOS_SUCCESSFUL) {
849: printk("ahci: %02u:%02u.%u: Can not read IRQ", bus, dev, fun);
850: return;
851: }
852:
853: printk("AHCI SATA %02u:%02u.%u BAR 0x%x IRQ %u\n", bus, dev, fun, bar, irq);
854:
855: /* Map mmio */
856: ahci_host = vremap(bar, 0x2000);
857:
858: /* Request IRQ */
859: if (request_irq(irq, &ahci_interrupt, SA_SHIRQ, "ahci", (void*) ahci_host)) {
860: printk("ahci: %02u:%02u.%u: Can not get irq %u\n", bus, dev, fun, irq);
861: return;
862: }
863:
864: nports = (readl(&ahci_host->cap) & 0x1f) + 1;
865: port_map = readl(&ahci_host->pi);
866:
867: for (n = 0, i = 0; i < AHCI_MAX_PORTS; i++)
868: if (port_map & (1U << i))
869: n++;
870:
871: if (nports != n) {
1.1.1.2 root 872: printk("ahci: %02u:%02u.%u: Odd number of ports %u, assuming %u is correct\n", bus, dev, fun, n, nports);
1.1 root 873: port_map = 0;
874: }
875: if (!port_map) {
876: port_map = (1U << nports) - 1;
877: }
878:
879: for (i = 0; i < AHCI_MAX_PORTS; i++) {
880: u32 ssts;
1.1.1.3 ! root 881: u8 spd, ipm;
1.1 root 882:
883: if (!(port_map & (1U << i)))
884: continue;
885:
886: ahci_port = &ahci_host->ports[i];
887:
888: ssts = readl(&ahci_port->ssts);
1.1.1.3 ! root 889: spd = ssts & 0xf;
! 890: switch (spd)
! 891: {
! 892: case 0x0:
! 893: /* Device not present */
! 894: continue;
! 895: case 0x1:
! 896: printk("ahci: %02u:%02u.%u: Port %u communication not established. TODO: power on device\n", bus, dev, fun, i);
! 897: continue;
! 898: case 0x3:
! 899: /* Present and communication established */
! 900: break;
! 901: case 0x4:
! 902: printk("ahci: %02u:%02u.%u: Phy offline?!\n", bus, dev, fun, i);
! 903: continue;
! 904: default:
! 905: printk("ahci: %02u:%02u.%u: Unknown port %u SPD %x\n", bus, dev, fun, i, spd);
! 906: continue;
! 907: }
! 908:
! 909: ipm = (ssts >> 8) & 0xf;
! 910: switch (ipm)
! 911: {
! 912: case 0x0:
! 913: /* Device not present */
! 914: continue;
! 915: case 0x1:
! 916: /* Active */
! 917: break;
! 918: case 0x2:
! 919: printk("ahci: %02u:%02u.%u: Port %u in Partial power management. TODO: power on device\n", bus, dev, fun, i);
! 920: continue;
! 921: case 0x6:
! 922: printk("ahci: %02u:%02u.%u: Port %u in Slumber power management. TODO: power on device\n", bus, dev, fun, i);
! 923: continue;
! 924: default:
! 925: printk("ahci: %02u:%02u.%u: Unknown port %u IPM %x\n", bus, dev, fun, i, ipm);
! 926: continue;
! 927: }
1.1 root 928:
929: /* OK! Probe this port */
930: ahci_probe_port(ahci_host, ahci_port);
931: }
932: }
933:
934: /* genhd callback to set size of disks */
935: static void ahci_geninit(struct gendisk *gd)
936: {
937: unsigned unit;
938: struct port *port;
939:
940: for (unit = 0; unit < gd->nr_real; unit++) {
941: port = &ports[unit];
942: port->part[0].nr_sects = port->capacity;
1.1.1.2 root 943: if (!port->part[0].nr_sects)
944: port->part[0].nr_sects = -1;
1.1 root 945: }
946: }
947:
948: /* Probe all AHCI PCI devices */
949: void ahci_probe_pci(void)
950: {
951: unsigned char bus, device;
952: unsigned short index;
953: int ret;
954: unsigned nports, unit, nminors;
955: struct port *port;
956: struct gendisk *gd, **gdp;
957: int *bs;
958:
959: for (index = 0;
960: (ret = pcibios_find_class(PCI_CLASS_STORAGE_SATA_AHCI, index, &bus, &device)) == PCIBIOS_SUCCESSFUL;
961: index++)
962: {
963: /* Note: this prevents from also having a SCSI controler.
964: * It shouldn't harm too much until we have proper hardware
965: * enumeration.
966: */
967: if (register_blkdev(MAJOR_NR, "sd", &ahci_fops) < 0)
968: printk("could not register ahci\n");
969: ahci_probe_dev(bus, device);
970: }
971:
972: for (nports = 0, port = &ports[0]; port < &ports[MAX_PORTS]; port++)
973: if (port->ahci_port)
974: nports++;
975:
976: nminors = nports * (1<<PARTN_BITS);
977:
978: gd = kmalloc(sizeof(*gd), GFP_KERNEL);
979: gd->sizes = kmalloc(nminors * sizeof(*gd->sizes), GFP_KERNEL);
980: gd->part = kmalloc(nminors * sizeof(*gd->part), GFP_KERNEL);
981: bs = kmalloc(nminors * sizeof(*bs), GFP_KERNEL);
982:
983: blksize_size[MAJOR_NR] = bs;
984: for (unit = 0; unit < nminors; unit++)
985: /* We prefer to transfer whole pages */
986: *bs++ = PAGE_SIZE;
987:
988: memset(gd->part, 0, nminors * sizeof(*gd->part));
989:
990: for (unit = 0; unit < nports; unit++) {
991: ports[unit].gd = gd;
992: ports[unit].part = &gd->part[unit << PARTN_BITS];
993: }
994:
995: gd->major = MAJOR_NR;
996: gd->major_name = "sd";
997: gd->minor_shift = PARTN_BITS;
998: gd->max_p = 1<<PARTN_BITS;
999: gd->max_nr = nports;
1000: gd->nr_real = nports;
1001: gd->init = ahci_geninit;
1002: gd->next = NULL;
1003:
1004: for (gdp = &gendisk_head; *gdp; gdp = &((*gdp)->next))
1005: ;
1006: *gdp = gd;
1007:
1008: blk_dev[MAJOR_NR].request_fn = ahci_do_request;
1009: }
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