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Annotation of Gnu-Mach/linux/dev/include/ahci.h, revision 1.1

1.1     ! root        1: #ifndef _GNUMACH_AHCI_H
        !             2: #define _GNUMACH_AHCI_H
        !             3: extern void ahci_probe_pci(void);
        !             4: 
        !             5: /* From linux 3.9's drivers/ata/ahci.h */
        !             6: 
        !             7: /*
        !             8:  *  ahci.h - Common AHCI SATA definitions and declarations
        !             9:  *
        !            10:  *  Maintained by:  Jeff Garzik <[email protected]>
        !            11:  *                 Please ALWAYS copy [email protected]
        !            12:  *                 on emails.
        !            13:  *
        !            14:  *  Copyright 2004-2005 Red Hat, Inc.
        !            15:  *
        !            16:  *
        !            17:  *  This program is free software; you can redistribute it and/or modify
        !            18:  *  it under the terms of the GNU General Public License as published by
        !            19:  *  the Free Software Foundation; either version 2, or (at your option)
        !            20:  *  any later version.
        !            21:  *
        !            22:  *  This program is distributed in the hope that it will be useful,
        !            23:  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
        !            24:  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
        !            25:  *  GNU General Public License for more details.
        !            26:  *
        !            27:  *  You should have received a copy of the GNU General Public License
        !            28:  *  along with this program; see the file COPYING.  If not, write to
        !            29:  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
        !            30:  *
        !            31:  *
        !            32:  * libata documentation is available via 'make {ps|pdf}docs',
        !            33:  * as Documentation/DocBook/libata.*
        !            34:  *
        !            35:  * AHCI hardware documentation:
        !            36:  * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
        !            37:  * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
        !            38:  *
        !            39:  */
        !            40: 
        !            41: enum {
        !            42:        AHCI_MAX_PORTS          = 32,
        !            43:        AHCI_MAX_SG             = 168, /* hardware max is 64K */
        !            44:        AHCI_DMA_BOUNDARY       = 0xffffffff,
        !            45:        AHCI_MAX_CMDS           = 32,
        !            46:        AHCI_CMD_SZ             = 32,
        !            47:        AHCI_CMD_SLOT_SZ        = AHCI_MAX_CMDS * AHCI_CMD_SZ,
        !            48:        AHCI_RX_FIS_SZ          = 256,
        !            49:        AHCI_CMD_TBL_CDB        = 0x40,
        !            50:        AHCI_CMD_TBL_HDR_SZ     = 0x80,
        !            51:        AHCI_CMD_TBL_SZ         = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
        !            52:        AHCI_CMD_TBL_AR_SZ      = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
        !            53:        AHCI_PORT_PRIV_DMA_SZ   = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
        !            54:                                  AHCI_RX_FIS_SZ,
        !            55:        AHCI_PORT_PRIV_FBS_DMA_SZ       = AHCI_CMD_SLOT_SZ +
        !            56:                                          AHCI_CMD_TBL_AR_SZ +
        !            57:                                          (AHCI_RX_FIS_SZ * 16),
        !            58:        AHCI_IRQ_ON_SG          = (1 << 31),
        !            59:        AHCI_CMD_ATAPI          = (1 << 5),
        !            60:        AHCI_CMD_WRITE          = (1 << 6),
        !            61:        AHCI_CMD_PREFETCH       = (1 << 7),
        !            62:        AHCI_CMD_RESET          = (1 << 8),
        !            63:        AHCI_CMD_CLR_BUSY       = (1 << 10),
        !            64: 
        !            65:        RX_FIS_PIO_SETUP        = 0x20, /* offset of PIO Setup FIS data */
        !            66:        RX_FIS_D2H_REG          = 0x40, /* offset of D2H Register FIS data */
        !            67:        RX_FIS_SDB              = 0x58, /* offset of SDB FIS data */
        !            68:        RX_FIS_UNK              = 0x60, /* offset of Unknown FIS data */
        !            69: 
        !            70:        /* global controller registers */
        !            71:        HOST_CAP                = 0x00, /* host capabilities */
        !            72:        HOST_CTL                = 0x04, /* global host control */
        !            73:        HOST_IRQ_STAT           = 0x08, /* interrupt status */
        !            74:        HOST_PORTS_IMPL         = 0x0c, /* bitmap of implemented ports */
        !            75:        HOST_VERSION            = 0x10, /* AHCI spec. version compliancy */
        !            76:        HOST_EM_LOC             = 0x1c, /* Enclosure Management location */
        !            77:        HOST_EM_CTL             = 0x20, /* Enclosure Management Control */
        !            78:        HOST_CAP2               = 0x24, /* host capabilities, extended */
        !            79: 
        !            80:        /* HOST_CTL bits */
        !            81:        HOST_RESET              = (1 << 0),  /* reset controller; self-clear */
        !            82:        HOST_IRQ_EN             = (1 << 1),  /* global IRQ enable */
        !            83:        HOST_AHCI_EN            = (1 << 31), /* AHCI enabled */
        !            84: 
        !            85:        /* HOST_CAP bits */
        !            86:        HOST_CAP_SXS            = (1 << 5),  /* Supports External SATA */
        !            87:        HOST_CAP_EMS            = (1 << 6),  /* Enclosure Management support */
        !            88:        HOST_CAP_CCC            = (1 << 7),  /* Command Completion Coalescing */
        !            89:        HOST_CAP_PART           = (1 << 13), /* Partial state capable */
        !            90:        HOST_CAP_SSC            = (1 << 14), /* Slumber state capable */
        !            91:        HOST_CAP_PIO_MULTI      = (1 << 15), /* PIO multiple DRQ support */
        !            92:        HOST_CAP_FBS            = (1 << 16), /* FIS-based switching support */
        !            93:        HOST_CAP_PMP            = (1 << 17), /* Port Multiplier support */
        !            94:        HOST_CAP_ONLY           = (1 << 18), /* Supports AHCI mode only */
        !            95:        HOST_CAP_CLO            = (1 << 24), /* Command List Override support */
        !            96:        HOST_CAP_LED            = (1 << 25), /* Supports activity LED */
        !            97:        HOST_CAP_ALPM           = (1 << 26), /* Aggressive Link PM support */
        !            98:        HOST_CAP_SSS            = (1 << 27), /* Staggered Spin-up */
        !            99:        HOST_CAP_MPS            = (1 << 28), /* Mechanical presence switch */
        !           100:        HOST_CAP_SNTF           = (1 << 29), /* SNotification register */
        !           101:        HOST_CAP_NCQ            = (1 << 30), /* Native Command Queueing */
        !           102:        HOST_CAP_64             = (1 << 31), /* PCI DAC (64-bit DMA) support */
        !           103: 
        !           104:        /* HOST_CAP2 bits */
        !           105:        HOST_CAP2_BOH           = (1 << 0),  /* BIOS/OS handoff supported */
        !           106:        HOST_CAP2_NVMHCI        = (1 << 1),  /* NVMHCI supported */
        !           107:        HOST_CAP2_APST          = (1 << 2),  /* Automatic partial to slumber */
        !           108:        HOST_CAP2_SDS           = (1 << 3),  /* Support device sleep */
        !           109:        HOST_CAP2_SADM          = (1 << 4),  /* Support aggressive DevSlp */
        !           110:        HOST_CAP2_DESO          = (1 << 5),  /* DevSlp from slumber only */
        !           111: 
        !           112:        /* registers for each SATA port */
        !           113:        PORT_LST_ADDR           = 0x00, /* command list DMA addr */
        !           114:        PORT_LST_ADDR_HI        = 0x04, /* command list DMA addr hi */
        !           115:        PORT_FIS_ADDR           = 0x08, /* FIS rx buf addr */
        !           116:        PORT_FIS_ADDR_HI        = 0x0c, /* FIS rx buf addr hi */
        !           117:        PORT_IRQ_STAT           = 0x10, /* interrupt status */
        !           118:        PORT_IRQ_MASK           = 0x14, /* interrupt enable/disable mask */
        !           119:        PORT_CMD                = 0x18, /* port command */
        !           120:        PORT_TFDATA             = 0x20, /* taskfile data */
        !           121:        PORT_SIG                = 0x24, /* device TF signature */
        !           122:        PORT_CMD_ISSUE          = 0x38, /* command issue */
        !           123:        PORT_SCR_STAT           = 0x28, /* SATA phy register: SStatus */
        !           124:        PORT_SCR_CTL            = 0x2c, /* SATA phy register: SControl */
        !           125:        PORT_SCR_ERR            = 0x30, /* SATA phy register: SError */
        !           126:        PORT_SCR_ACT            = 0x34, /* SATA phy register: SActive */
        !           127:        PORT_SCR_NTF            = 0x3c, /* SATA phy register: SNotification */
        !           128:        PORT_FBS                = 0x40, /* FIS-based Switching */
        !           129:        PORT_DEVSLP             = 0x44, /* device sleep */
        !           130: 
        !           131:        /* PORT_IRQ_{STAT,MASK} bits */
        !           132:        PORT_IRQ_COLD_PRES      = (1 << 31), /* cold presence detect */
        !           133:        PORT_IRQ_TF_ERR         = (1 << 30), /* task file error */
        !           134:        PORT_IRQ_HBUS_ERR       = (1 << 29), /* host bus fatal error */
        !           135:        PORT_IRQ_HBUS_DATA_ERR  = (1 << 28), /* host bus data error */
        !           136:        PORT_IRQ_IF_ERR         = (1 << 27), /* interface fatal error */
        !           137:        PORT_IRQ_IF_NONFATAL    = (1 << 26), /* interface non-fatal error */
        !           138:        PORT_IRQ_OVERFLOW       = (1 << 24), /* xfer exhausted available S/G */
        !           139:        PORT_IRQ_BAD_PMP        = (1 << 23), /* incorrect port multiplier */
        !           140: 
        !           141:        PORT_IRQ_PHYRDY         = (1 << 22), /* PhyRdy changed */
        !           142:        PORT_IRQ_DEV_ILCK       = (1 << 7), /* device interlock */
        !           143:        PORT_IRQ_CONNECT        = (1 << 6), /* port connect change status */
        !           144:        PORT_IRQ_SG_DONE        = (1 << 5), /* descriptor processed */
        !           145:        PORT_IRQ_UNK_FIS        = (1 << 4), /* unknown FIS rx'd */
        !           146:        PORT_IRQ_SDB_FIS        = (1 << 3), /* Set Device Bits FIS rx'd */
        !           147:        PORT_IRQ_DMAS_FIS       = (1 << 2), /* DMA Setup FIS rx'd */
        !           148:        PORT_IRQ_PIOS_FIS       = (1 << 1), /* PIO Setup FIS rx'd */
        !           149:        PORT_IRQ_D2H_REG_FIS    = (1 << 0), /* D2H Register FIS rx'd */
        !           150: 
        !           151:        PORT_IRQ_FREEZE         = PORT_IRQ_HBUS_ERR |
        !           152:                                  PORT_IRQ_IF_ERR |
        !           153:                                  PORT_IRQ_CONNECT |
        !           154:                                  PORT_IRQ_PHYRDY |
        !           155:                                  PORT_IRQ_UNK_FIS |
        !           156:                                  PORT_IRQ_BAD_PMP,
        !           157:        PORT_IRQ_ERROR          = PORT_IRQ_FREEZE |
        !           158:                                  PORT_IRQ_TF_ERR |
        !           159:                                  PORT_IRQ_HBUS_DATA_ERR,
        !           160:        DEF_PORT_IRQ            = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
        !           161:                                  PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
        !           162:                                  PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
        !           163: 
        !           164:        /* PORT_CMD bits */
        !           165:        PORT_CMD_ASP            = (1 << 27), /* Aggressive Slumber/Partial */
        !           166:        PORT_CMD_ALPE           = (1 << 26), /* Aggressive Link PM enable */
        !           167:        PORT_CMD_ATAPI          = (1 << 24), /* Device is ATAPI */
        !           168:        PORT_CMD_FBSCP          = (1 << 22), /* FBS Capable Port */
        !           169:        PORT_CMD_PMP            = (1 << 17), /* PMP attached */
        !           170:        PORT_CMD_LIST_ON        = (1 << 15), /* cmd list DMA engine running */
        !           171:        PORT_CMD_FIS_ON         = (1 << 14), /* FIS DMA engine running */
        !           172:        PORT_CMD_FIS_RX         = (1 << 4), /* Enable FIS receive DMA engine */
        !           173:        PORT_CMD_CLO            = (1 << 3), /* Command list override */
        !           174:        PORT_CMD_POWER_ON       = (1 << 2), /* Power up device */
        !           175:        PORT_CMD_SPIN_UP        = (1 << 1), /* Spin up device */
        !           176:        PORT_CMD_START          = (1 << 0), /* Enable port DMA engine */
        !           177: 
        !           178:        PORT_CMD_ICC_MASK       = (0xf << 28), /* i/f ICC state mask */
        !           179:        PORT_CMD_ICC_ACTIVE     = (0x1 << 28), /* Put i/f in active state */
        !           180:        PORT_CMD_ICC_PARTIAL    = (0x2 << 28), /* Put i/f in partial state */
        !           181:        PORT_CMD_ICC_SLUMBER    = (0x6 << 28), /* Put i/f in slumber state */
        !           182: 
        !           183:        /* PORT_FBS bits */
        !           184:        PORT_FBS_DWE_OFFSET     = 16, /* FBS device with error offset */
        !           185:        PORT_FBS_ADO_OFFSET     = 12, /* FBS active dev optimization offset */
        !           186:        PORT_FBS_DEV_OFFSET     = 8,  /* FBS device to issue offset */
        !           187:        PORT_FBS_DEV_MASK       = (0xf << PORT_FBS_DEV_OFFSET),  /* FBS.DEV */
        !           188:        PORT_FBS_SDE            = (1 << 2), /* FBS single device error */
        !           189:        PORT_FBS_DEC            = (1 << 1), /* FBS device error clear */
        !           190:        PORT_FBS_EN             = (1 << 0), /* Enable FBS */
        !           191: 
        !           192:        /* PORT_DEVSLP bits */
        !           193:        PORT_DEVSLP_DM_OFFSET   = 25,             /* DITO multiplier offset */
        !           194:        PORT_DEVSLP_DM_MASK     = (0xf << 25),    /* DITO multiplier mask */
        !           195:        PORT_DEVSLP_DITO_OFFSET = 15,             /* DITO offset */
        !           196:        PORT_DEVSLP_MDAT_OFFSET = 10,             /* Minimum assertion time */
        !           197:        PORT_DEVSLP_DETO_OFFSET = 2,              /* DevSlp exit timeout */
        !           198:        PORT_DEVSLP_DSP         = (1 << 1),       /* DevSlp present */
        !           199:        PORT_DEVSLP_ADSE        = (1 << 0),       /* Aggressive DevSlp enable */
        !           200: 
        !           201:        /* hpriv->flags bits */
        !           202: 
        !           203: #define AHCI_HFLAGS(flags)             .private_data   = (void *)(flags)
        !           204: 
        !           205:        AHCI_HFLAG_NO_NCQ               = (1 << 0),
        !           206:        AHCI_HFLAG_IGN_IRQ_IF_ERR       = (1 << 1), /* ignore IRQ_IF_ERR */
        !           207:        AHCI_HFLAG_IGN_SERR_INTERNAL    = (1 << 2), /* ignore SERR_INTERNAL */
        !           208:        AHCI_HFLAG_32BIT_ONLY           = (1 << 3), /* force 32bit */
        !           209:        AHCI_HFLAG_MV_PATA              = (1 << 4), /* PATA port */
        !           210:        AHCI_HFLAG_NO_MSI               = (1 << 5), /* no PCI MSI */
        !           211:        AHCI_HFLAG_NO_PMP               = (1 << 6), /* no PMP */
        !           212:        AHCI_HFLAG_SECT255              = (1 << 8), /* max 255 sectors */
        !           213:        AHCI_HFLAG_YES_NCQ              = (1 << 9), /* force NCQ cap on */
        !           214:        AHCI_HFLAG_NO_SUSPEND           = (1 << 10), /* don't suspend */
        !           215:        AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11), /* treat SRST timeout as
        !           216:                                                        link offline */
        !           217:        AHCI_HFLAG_NO_SNTF              = (1 << 12), /* no sntf */
        !           218:        AHCI_HFLAG_NO_FPDMA_AA          = (1 << 13), /* no FPDMA AA */
        !           219:        AHCI_HFLAG_YES_FBS              = (1 << 14), /* force FBS cap on */
        !           220:        AHCI_HFLAG_DELAY_ENGINE         = (1 << 15), /* do not start engine on
        !           221:                                                        port start (wait until
        !           222:                                                        error-handling stage) */
        !           223:        AHCI_HFLAG_MULTI_MSI            = (1 << 16), /* multiple PCI MSIs */
        !           224: 
        !           225:        /* ap->flags bits */
        !           226: 
        !           227:        /*
        !           228:        AHCI_FLAG_COMMON                = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
        !           229:                                          ATA_FLAG_ACPI_SATA | ATA_FLAG_AN,
        !           230:                                          */
        !           231: 
        !           232:        ICH_MAP                         = 0x90, /* ICH MAP register */
        !           233: 
        !           234:        /* em constants */
        !           235:        EM_MAX_SLOTS                    = 8,
        !           236:        EM_MAX_RETRY                    = 5,
        !           237: 
        !           238:        /* em_ctl bits */
        !           239:        EM_CTL_RST              = (1 << 9), /* Reset */
        !           240:        EM_CTL_TM               = (1 << 8), /* Transmit Message */
        !           241:        EM_CTL_MR               = (1 << 0), /* Message Received */
        !           242:        EM_CTL_ALHD             = (1 << 26), /* Activity LED */
        !           243:        EM_CTL_XMT              = (1 << 25), /* Transmit Only */
        !           244:        EM_CTL_SMB              = (1 << 24), /* Single Message Buffer */
        !           245:        EM_CTL_SGPIO            = (1 << 19), /* SGPIO messages supported */
        !           246:        EM_CTL_SES              = (1 << 18), /* SES-2 messages supported */
        !           247:        EM_CTL_SAFTE            = (1 << 17), /* SAF-TE messages supported */
        !           248:        EM_CTL_LED              = (1 << 16), /* LED messages supported */
        !           249: 
        !           250:        /* em message type */
        !           251:        EM_MSG_TYPE_LED         = (1 << 0), /* LED */
        !           252:        EM_MSG_TYPE_SAFTE       = (1 << 1), /* SAF-TE */
        !           253:        EM_MSG_TYPE_SES2        = (1 << 2), /* SES-2 */
        !           254:        EM_MSG_TYPE_SGPIO       = (1 << 3), /* SGPIO */
        !           255: 
        !           256:        FIS_TYPE_REG_H2D        = 0x27,
        !           257:        FIS_TYPE_REG_D2H        = 0x34,
        !           258:        FIS_TYPE_DMA_ACT        = 0x39,
        !           259:        FIS_TYPE_DMA_SETUP      = 0x41,
        !           260:        FIS_TYPE_DATA           = 0x46,
        !           261:        FIS_TYPE_BIST           = 0x58,
        !           262:        FIS_TYPE_PIO_SETUP      = 0x5F,
        !           263:        FIS_TYPE_DEV_BITS       = 0xA1,
        !           264: };
        !           265: 
        !           266: /* End from linux 3.9 */
        !           267: 
        !           268: #endif /* _GNUMACH_AHCI_H */

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