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1.1 root 1: /* Generic NS8390 register definitions. */
2: /* This file is part of Donald Becker's 8390 drivers, and is distributed
3: under the same license. Auto-loading of 8390.o only in v2.2 - Paul G.
4: Some of these names and comments originated from the Crynwr
5: packet drivers, which are distributed under the GPL. */
6:
7: #ifndef _8390_h
8: #define _8390_h
9:
10: #include <linux/config.h>
11: #include <linux/if_ether.h>
12: #include <linux/ioport.h>
13: #include <linux/skbuff.h>
14:
15: #define TX_2X_PAGES 12
16: #define TX_1X_PAGES 6
17:
18: #define TX_PAGES TX_2X_PAGES
19:
20: #define ETHER_ADDR_LEN 6
21:
22: /* The 8390 specific per-packet-header format. */
23: struct e8390_pkt_hdr {
24: unsigned char status; /* status */
25: unsigned char next; /* pointer to next packet. */
26: unsigned short count; /* header + packet length in bytes */
27: };
28:
29: #ifdef notdef
30: extern int ei_debug;
31: #else
32: #define ei_debug 1
33: #endif
34:
35: #ifndef HAVE_AUTOIRQ
36: /* From auto_irq.c */
37: extern void autoirq_setup(int waittime);
38: extern unsigned long autoirq_report(int waittime);
39: #endif
40:
41: /* Most of these entries should be in 'struct net_device' (or most of the
42: things in there should be here!) */
43: /* You have one of these per-board */
44: struct ei_device {
45: const char *name;
46: void (*reset_8390)(struct net_device *);
47: void (*get_8390_hdr)(struct net_device *, struct e8390_pkt_hdr *, int);
48: void (*block_output)(struct net_device *, int, const unsigned char *, int);
49: void (*block_input)(struct net_device *, int, struct sk_buff *, int);
50: unsigned char mcfilter[8];
51: unsigned open:1;
52: unsigned word16:1; /* We have the 16-bit (vs 8-bit) version of the card. */
53: unsigned txing:1; /* Transmit Active */
54: unsigned irqlock:1; /* 8390's intrs disabled when '1'. */
55: unsigned dmaing:1; /* Remote DMA Active */
56: unsigned char tx_start_page, rx_start_page, stop_page;
57: unsigned char current_page; /* Read pointer in buffer */
58: unsigned char interface_num; /* Net port (AUI, 10bT.) to use. */
59: unsigned char txqueue; /* Tx Packet buffer queue length. */
60: short tx1, tx2; /* Packet lengths for ping-pong tx. */
61: short lasttx; /* Alpha version consistency check. */
62: unsigned char saved_irq; /* Original dev->irq value. */
63: struct net_device_stats stat; /* The new statistics table. */
64: spinlock_t page_lock; /* Page register locks */
65: unsigned long priv; /* Private field to store bus IDs etc. */
66: };
67:
68: /* The maximum number of 8390 interrupt service routines called per IRQ. */
69: #define MAX_SERVICE 12
70:
71: /* The maximum time waited (in jiffies) before assuming a Tx failed. (20ms) */
72: #define TX_TIMEOUT (20*HZ/100)
73:
74: #define ei_status (*(struct ei_device *)(dev->priv))
75:
76: /* Some generic ethernet register configurations. */
77: #define E8390_TX_IRQ_MASK 0xa /* For register EN0_ISR */
78: #define E8390_RX_IRQ_MASK 0x5
79: #define E8390_RXCONFIG 0x4 /* EN0_RXCR: broadcasts, no multicast,errors */
80: #define E8390_RXOFF 0x20 /* EN0_RXCR: Accept no packets */
81: #define E8390_TXCONFIG 0x00 /* EN0_TXCR: Normal transmit mode */
82: #define E8390_TXOFF 0x02 /* EN0_TXCR: Transmitter off */
83:
84: /* Register accessed at EN_CMD, the 8390 base addr. */
85: #define E8390_STOP 0x01 /* Stop and reset the chip */
86: #define E8390_START 0x02 /* Start the chip, clear reset */
87: #define E8390_TRANS 0x04 /* Transmit a frame */
88: #define E8390_RREAD 0x08 /* Remote read */
89: #define E8390_RWRITE 0x10 /* Remote write */
90: #define E8390_NODMA 0x20 /* Remote DMA */
91: #define E8390_PAGE0 0x00 /* Select page chip registers */
92: #define E8390_PAGE1 0x40 /* using the two high-order bits */
93: #define E8390_PAGE2 0x80 /* Page 3 is invalid. */
94:
95: #define E8390_CMD 0x00 /* The command register (for all pages) */
96: /* Page 0 register offsets. */
97: #define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */
98: #define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */
99: #define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */
100: #define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */
101: #define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */
102: #define EN0_TSR 0x04 /* Transmit status reg RD */
103: #define EN0_TPSR 0x04 /* Transmit starting page WR */
104: #define EN0_NCR 0x05 /* Number of collision reg RD */
105: #define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */
106: #define EN0_FIFO 0x06 /* FIFO RD */
107: #define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */
108: #define EN0_ISR 0x07 /* Interrupt status reg RD WR */
109: #define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */
110: #define EN0_RSARLO 0x08 /* Remote start address reg 0 */
111: #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */
112: #define EN0_RSARHI 0x09 /* Remote start address reg 1 */
113: #define EN0_RCNTLO 0x0a /* Remote byte count reg WR */
114: #define EN0_RCNTHI 0x0b /* Remote byte count reg WR */
115: #define EN0_RSR 0x0c /* rx status reg RD */
116: #define EN0_RXCR 0x0c /* RX configuration reg WR */
117: #define EN0_TXCR 0x0d /* TX configuration reg WR */
118: #define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */
119: #define EN0_DCFG 0x0e /* Data configuration reg WR */
120: #define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */
121: #define EN0_IMR 0x0f /* Interrupt mask reg WR */
122: #define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */
123:
124: /* Bits in EN0_ISR - Interrupt status register */
125: #define ENISR_RX 0x01 /* Receiver, no error */
126: #define ENISR_TX 0x02 /* Transmitter, no error */
127: #define ENISR_RX_ERR 0x04 /* Receiver, with error */
128: #define ENISR_TX_ERR 0x08 /* Transmitter, with error */
129: #define ENISR_OVER 0x10 /* Receiver overwrote the ring */
130: #define ENISR_COUNTERS 0x20 /* Counters need emptying */
131: #define ENISR_RDC 0x40 /* remote dma complete */
132: #define ENISR_RESET 0x80 /* Reset completed */
133: #define ENISR_ALL 0x3f /* Interrupts we will enable */
134:
135: /* Bits in EN0_DCFG - Data config register */
136: #define ENDCFG_WTS 0x01 /* word transfer mode selection */
137:
138: /* Page 1 register offsets. */
139: #define EN1_PHYS 0x01 /* This board's physical enet addr RD WR */
140: #define EN1_PHYS_SHIFT(i) (i+1) /* Get and set mac address */
141: #define EN1_CURPAG 0x07 /* Current memory page RD WR */
142: #define EN1_MULT 0x08 /* Multicast filter mask array (8 bytes) RD WR */
143: #define EN1_MULT_SHIFT(i) (8+i) /* Get and set multicast filter */
144:
145: /* Bits in received packet status byte and EN0_RSR*/
146: #define ENRSR_RXOK 0x01 /* Received a good packet */
147: #define ENRSR_CRC 0x02 /* CRC error */
148: #define ENRSR_FAE 0x04 /* frame alignment error */
149: #define ENRSR_FO 0x08 /* FIFO overrun */
150: #define ENRSR_MPA 0x10 /* missed pkt */
151: #define ENRSR_PHY 0x20 /* physical/multicast address */
152: #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
153: #define ENRSR_DEF 0x80 /* deferring */
154:
155: /* Transmitted packet status, EN0_TSR. */
156: #define ENTSR_PTX 0x01 /* Packet transmitted without error */
157: #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
158: #define ENTSR_COL 0x04 /* The transmit collided at least once. */
159: #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
160: #define ENTSR_CRS 0x10 /* The carrier sense was lost. */
161: #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
162: #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
163: #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
164:
165: #endif /* _8390_h */
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