|
|
1.1 ! root 1: /* ! 2: * cirrus.h 1.11 2003/09/09 07:05:40 ! 3: * ! 4: * The contents of this file are subject to the Mozilla Public License ! 5: * Version 1.1 (the "License"); you may not use this file except in ! 6: * compliance with the License. You may obtain a copy of the License ! 7: * at http://www.mozilla.org/MPL/ ! 8: * ! 9: * Software distributed under the License is distributed on an "AS IS" ! 10: * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See ! 11: * the License for the specific language governing rights and ! 12: * limitations under the License. ! 13: * ! 14: * The initial developer of the original code is David A. Hinds ! 15: * <[email protected]>. Portions created by David A. Hinds ! 16: * are Copyright (C) 1999 David A. Hinds. All Rights Reserved. ! 17: * ! 18: * Alternatively, the contents of this file may be used under the ! 19: * terms of the GNU General Public License version 2 (the "GPL"), in ! 20: * which case the provisions of the GPL are applicable instead of the ! 21: * above. If you wish to allow the use of your version of this file ! 22: * only under the terms of the GPL and not to allow others to use ! 23: * your version of this file under the MPL, indicate your decision by ! 24: * deleting the provisions above and replace them with the notice and ! 25: * other provisions required by the GPL. If you do not delete the ! 26: * provisions above, a recipient may use your version of this file ! 27: * under either the MPL or the GPL. ! 28: */ ! 29: ! 30: #ifndef _LINUX_CIRRUS_H ! 31: #define _LINUX_CIRRUS_H ! 32: ! 33: #ifndef PCI_VENDOR_ID_CIRRUS ! 34: #define PCI_VENDOR_ID_CIRRUS 0x1013 ! 35: #endif ! 36: #ifndef PCI_DEVICE_ID_CIRRUS_6729 ! 37: #define PCI_DEVICE_ID_CIRRUS_6729 0x1100 ! 38: #endif ! 39: #ifndef PCI_DEVICE_ID_CIRRUS_6832 ! 40: #define PCI_DEVICE_ID_CIRRUS_6832 0x1110 ! 41: #endif ! 42: ! 43: #define PD67_MISC_CTL_1 0x16 /* Misc control 1 */ ! 44: #define PD67_FIFO_CTL 0x17 /* FIFO control */ ! 45: #define PD67_MISC_CTL_2 0x1E /* Misc control 2 */ ! 46: #define PD67_CHIP_INFO 0x1f /* Chip information */ ! 47: #define PD67_ATA_CTL 0x026 /* 6730: ATA control */ ! 48: #define PD67_EXT_INDEX 0x2e /* Extension index */ ! 49: #define PD67_EXT_DATA 0x2f /* Extension data */ ! 50: ! 51: #define pd67_ext_get(s, r) \ ! 52: (i365_set(s, PD67_EXT_INDEX, r), i365_get(s, PD67_EXT_DATA)) ! 53: #define pd67_ext_set(s, r, v) \ ! 54: (i365_set(s, PD67_EXT_INDEX, r), i365_set(s, PD67_EXT_DATA, v)) ! 55: ! 56: /* PD6722 extension registers -- indexed in PD67_EXT_INDEX */ ! 57: #define PD67_DATA_MASK0 0x01 /* Data mask 0 */ ! 58: #define PD67_DATA_MASK1 0x02 /* Data mask 1 */ ! 59: #define PD67_DMA_CTL 0x03 /* DMA control */ ! 60: ! 61: /* PD6730 extension registers -- indexed in PD67_EXT_INDEX */ ! 62: #define PD67_EXT_CTL_1 0x03 /* Extension control 1 */ ! 63: #define PD67_MEM_PAGE(n) ((n)+5) /* PCI window bits 31:24 */ ! 64: #define PD67_EXTERN_DATA 0x0a ! 65: #define PD67_EXT_CTL_2 0x0b ! 66: #define PD67_MISC_CTL_3 0x25 ! 67: #define PD67_SMB_PWR_CTL 0x26 ! 68: ! 69: /* I/O window address offset */ ! 70: #define PD67_IO_OFF(w) (0x36+((w)<<1)) ! 71: ! 72: /* Timing register sets */ ! 73: #define PD67_TIME_SETUP(n) (0x3a + 3*(n)) ! 74: #define PD67_TIME_CMD(n) (0x3b + 3*(n)) ! 75: #define PD67_TIME_RECOV(n) (0x3c + 3*(n)) ! 76: ! 77: /* Flags for PD67_MISC_CTL_1 */ ! 78: #define PD67_MC1_5V_DET 0x01 /* 5v detect */ ! 79: #define PD67_MC1_MEDIA_ENA 0x01 /* 6730: Multimedia enable */ ! 80: #define PD67_MC1_VCC_3V 0x02 /* 3.3v Vcc */ ! 81: #define PD67_MC1_PULSE_MGMT 0x04 ! 82: #define PD67_MC1_PULSE_IRQ 0x08 ! 83: #define PD67_MC1_SPKR_ENA 0x10 ! 84: #define PD67_MC1_INPACK_ENA 0x80 ! 85: ! 86: /* Flags for PD67_FIFO_CTL */ ! 87: #define PD67_FIFO_EMPTY 0x80 ! 88: ! 89: /* Flags for PD67_MISC_CTL_2 */ ! 90: #define PD67_MC2_FREQ_BYPASS 0x01 ! 91: #define PD67_MC2_DYNAMIC_MODE 0x02 ! 92: #define PD67_MC2_SUSPEND 0x04 ! 93: #define PD67_MC2_5V_CORE 0x08 ! 94: #define PD67_MC2_LED_ENA 0x10 /* IRQ 12 is LED enable */ ! 95: #define PD67_MC2_FAST_PCI 0x10 /* 6729: PCI bus > 25 MHz */ ! 96: #define PD67_MC2_3STATE_BIT7 0x20 /* Floppy change bit */ ! 97: #define PD67_MC2_DMA_MODE 0x40 ! 98: #define PD67_MC2_IRQ15_RI 0x80 /* IRQ 15 is ring enable */ ! 99: ! 100: /* Flags for PD67_CHIP_INFO */ ! 101: #define PD67_INFO_SLOTS 0x20 /* 0 = 1 slot, 1 = 2 slots */ ! 102: #define PD67_INFO_CHIP_ID 0xc0 ! 103: #define PD67_INFO_REV 0x1c ! 104: ! 105: /* Fields in PD67_TIME_* registers */ ! 106: #define PD67_TIME_SCALE 0xc0 ! 107: #define PD67_TIME_SCALE_1 0x00 ! 108: #define PD67_TIME_SCALE_16 0x40 ! 109: #define PD67_TIME_SCALE_256 0x80 ! 110: #define PD67_TIME_SCALE_4096 0xc0 ! 111: #define PD67_TIME_MULT 0x3f ! 112: ! 113: /* Fields in PD67_DMA_CTL */ ! 114: #define PD67_DMA_MODE 0xc0 ! 115: #define PD67_DMA_OFF 0x00 ! 116: #define PD67_DMA_DREQ_INPACK 0x40 ! 117: #define PD67_DMA_DREQ_WP 0x80 ! 118: #define PD67_DMA_DREQ_BVD2 0xc0 ! 119: #define PD67_DMA_PULLUP 0x20 /* Disable socket pullups? */ ! 120: ! 121: /* Fields in PD67_EXT_CTL_1 */ ! 122: #define PD67_EC1_VCC_PWR_LOCK 0x01 ! 123: #define PD67_EC1_AUTO_PWR_CLEAR 0x02 ! 124: #define PD67_EC1_LED_ENA 0x04 ! 125: #define PD67_EC1_INV_CARD_IRQ 0x08 ! 126: #define PD67_EC1_INV_MGMT_IRQ 0x10 ! 127: #define PD67_EC1_PULLUP_CTL 0x20 ! 128: ! 129: /* Fields in PD67_EXTERN_DATA */ ! 130: #define PD67_EXD_VS1(s) (0x01 << ((s)<<1)) ! 131: #define PD67_EXD_VS2(s) (0x02 << ((s)<<1)) ! 132: ! 133: /* Fields in PD67_EXT_CTL_2 */ ! 134: #define PD67_EC2_GPSTB_TOTEM 0x04 ! 135: #define PD67_EC2_GPSTB_IOR 0x08 ! 136: #define PD67_EC2_GPSTB_IOW 0x10 ! 137: #define PD67_EC2_GPSTB_HIGH 0x20 ! 138: ! 139: /* Fields in PD67_MISC_CTL_3 */ ! 140: #define PD67_MC3_IRQ_MASK 0x03 ! 141: #define PD67_MC3_IRQ_PCPCI 0x00 ! 142: #define PD67_MC3_IRQ_EXTERN 0x01 ! 143: #define PD67_MC3_IRQ_PCIWAY 0x02 ! 144: #define PD67_MC3_IRQ_PCI 0x03 ! 145: #define PD67_MC3_PWR_MASK 0x0c ! 146: #define PD67_MC3_PWR_SERIAL 0x00 ! 147: #define PD67_MC3_PWR_TI2202 0x08 ! 148: #define PD67_MC3_PWR_SMB 0x0c ! 149: ! 150: /* Register definitions for Cirrus PD6832 PCI-to-CardBus bridge */ ! 151: ! 152: /* PD6832 extension registers -- indexed in PD67_EXT_INDEX */ ! 153: #define PD68_PCI_SPACE 0x22 ! 154: #define PD68_PCCARD_SPACE 0x23 ! 155: #define PD68_WINDOW_TYPE 0x24 ! 156: #define PD68_EXT_CSC 0x2e ! 157: #define PD68_MISC_CTL_4 0x2f ! 158: #define PD68_MISC_CTL_5 0x30 ! 159: #define PD68_MISC_CTL_6 0x31 ! 160: ! 161: /* Extra flags in PD67_MISC_CTL_3 */ ! 162: #define PD68_MC3_HW_SUSP 0x10 ! 163: #define PD68_MC3_MM_EXPAND 0x40 ! 164: #define PD68_MC3_MM_ARM 0x80 ! 165: ! 166: /* Bridge Control Register */ ! 167: #define PD6832_BCR_MGMT_IRQ_ENA 0x0800 ! 168: ! 169: /* Socket Number Register */ ! 170: #define PD6832_SOCKET_NUMBER 0x004c /* 8 bit */ ! 171: ! 172: /* Data structure for tracking vendor-specific state */ ! 173: typedef struct cirrus_state_t { ! 174: u_char misc1; /* PD67_MISC_CTL_1 */ ! 175: u_char misc2; /* PD67_MISC_CTL_2 */ ! 176: u_char ectl1; /* PD67_EXT_CTL_1 */ ! 177: u_char timer[6]; /* PD67_TIME_* */ ! 178: } cirrus_state_t; ! 179: ! 180: #define CIRRUS_PCIC_ID \ ! 181: IS_PD6729, IS_PD6730, IS_PD6832 ! 182: ! 183: #define CIRRUS_PCIC_INFO \ ! 184: { "Cirrus PD6729", IS_CIRRUS|IS_PCI, ID(CIRRUS, 6729) }, \ ! 185: { "Cirrus PD6730", IS_CIRRUS|IS_PCI, PCI_VENDOR_ID_CIRRUS, -1 }, \ ! 186: { "Cirrus PD6832", IS_CIRRUS|IS_CARDBUS, ID(CIRRUS, 6832) } ! 187: ! 188: #endif /* _LINUX_CIRRUS_H */
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.