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1.1 root 1: /*
2: * o2micro.h 1.20 2002/03/03 14:16:57
3: *
4: * The contents of this file are subject to the Mozilla Public License
5: * Version 1.1 (the "License"); you may not use this file except in
6: * compliance with the License. You may obtain a copy of the License
7: * at http://www.mozilla.org/MPL/
8: *
9: * Software distributed under the License is distributed on an "AS IS"
10: * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
11: * the License for the specific language governing rights and
12: * limitations under the License.
13: *
14: * The initial developer of the original code is David A. Hinds
15: * <[email protected]>. Portions created by David A. Hinds
16: * are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
17: *
18: * Alternatively, the contents of this file may be used under the
19: * terms of the GNU General Public License version 2 (the "GPL"), in
20: * which case the provisions of the GPL are applicable instead of the
21: * above. If you wish to allow the use of your version of this file
22: * only under the terms of the GPL and not to allow others to use
23: * your version of this file under the MPL, indicate your decision by
24: * deleting the provisions above and replace them with the notice and
25: * other provisions required by the GPL. If you do not delete the
26: * provisions above, a recipient may use your version of this file
27: * under either the MPL or the GPL.
28: */
29:
30: #ifndef _LINUX_O2MICRO_H
31: #define _LINUX_O2MICRO_H
32:
33: #ifndef PCI_VENDOR_ID_O2
34: #define PCI_VENDOR_ID_O2 0x1217
35: #endif
36: #ifndef PCI_DEVICE_ID_O2_6729
37: #define PCI_DEVICE_ID_O2_6729 0x6729
38: #endif
39: #ifndef PCI_DEVICE_ID_O2_6730
40: #define PCI_DEVICE_ID_O2_6730 0x673a
41: #endif
42: #ifndef PCI_DEVICE_ID_O2_6832
43: #define PCI_DEVICE_ID_O2_6832 0x6832
44: #endif
45: #ifndef PCI_DEVICE_ID_O2_6836
46: #define PCI_DEVICE_ID_O2_6836 0x6836
47: #endif
48: #ifndef PCI_DEVICE_ID_O2_6812
49: #define PCI_DEVICE_ID_O2_6812 0x6872
50: #endif
51: #ifndef PCI_DEVICE_ID_O2_6922
52: #define PCI_DEVICE_ID_O2_6922 0x6825
53: #endif
54: #ifndef PCI_DEVICE_ID_O2_6933
55: #define PCI_DEVICE_ID_O2_6933 0x6933
56: #endif
57: #ifndef PCI_DEVICE_ID_O2_6912
58: #define PCI_DEVICE_ID_O2_6912 0x6972
59: #endif
60:
61: /* Additional PCI configuration registers */
62:
63: #define O2_MUX_CONTROL 0x90 /* 32 bit */
64: #define O2_MUX_RING_OUT 0x0000000f
65: #define O2_MUX_SKTB_ACTV 0x000000f0
66: #define O2_MUX_SCTA_ACTV_ENA 0x00000100
67: #define O2_MUX_SCTB_ACTV_ENA 0x00000200
68: #define O2_MUX_SER_IRQ_ROUTE 0x0000e000
69: #define O2_MUX_SER_PCI 0x00010000
70:
71: #define O2_MUX_SKTA_TURBO 0x000c0000 /* for 6833, 6860 */
72: #define O2_MUX_SKTB_TURBO 0x00300000
73: #define O2_MUX_AUX_VCC_3V 0x00400000
74: #define O2_MUX_PCI_VCC_5V 0x00800000
75: #define O2_MUX_PME_MUX 0x0f000000
76:
77: /* Additional ExCA registers */
78:
79: #define O2_MODE_A 0x38
80: #define O2_MODE_A_2 0x26 /* for 6833B, 6860C */
81: #define O2_MODE_A_CD_PULSE 0x04
82: #define O2_MODE_A_SUSP_EDGE 0x08
83: #define O2_MODE_A_HOST_SUSP 0x10
84: #define O2_MODE_A_PWR_MASK 0x60
85: #define O2_MODE_A_QUIET 0x80
86:
87: #define O2_MODE_B 0x39
88: #define O2_MODE_B_2 0x2e /* for 6833B, 6860C */
89: #define O2_MODE_B_IDENT 0x03
90: #define O2_MODE_B_ID_BSTEP 0x00
91: #define O2_MODE_B_ID_CSTEP 0x01
92: #define O2_MODE_B_ID_O2 0x02
93: #define O2_MODE_B_VS1 0x04
94: #define O2_MODE_B_VS2 0x08
95: #define O2_MODE_B_IRQ15_RI 0x80
96:
97: #define O2_MODE_C 0x3a
98: #define O2_MODE_C_DREQ_MASK 0x03
99: #define O2_MODE_C_DREQ_INPACK 0x01
100: #define O2_MODE_C_DREQ_WP 0x02
101: #define O2_MODE_C_DREQ_BVD2 0x03
102: #define O2_MODE_C_ZVIDEO 0x08
103: #define O2_MODE_C_IREQ_SEL 0x30
104: #define O2_MODE_C_MGMT_SEL 0xc0
105:
106: #define O2_MODE_D 0x3b
107: #define O2_MODE_D_IRQ_MODE 0x03
108: #define O2_MODE_D_IRQ_PCPCI 0x00
109: #define O2_MODE_D_IRQ_PCIWAY 0x02
110: #define O2_MODE_D_IRQ_PCI 0x03
111: #define O2_MODE_D_PCI_CLKRUN 0x04
112: #define O2_MODE_D_CB_CLKRUN 0x08
113: #define O2_MODE_D_SKT_ACTV 0x20
114: #define O2_MODE_D_PCI_FIFO 0x40 /* for OZ6729, OZ6730 */
115: #define O2_MODE_D_W97_IRQ 0x40
116: #define O2_MODE_D_ISA_IRQ 0x80
117:
118: #define O2_MHPG_DMA 0x3c
119: #define O2_MHPG_CHANNEL 0x07
120: #define O2_MHPG_CINT_ENA 0x08
121: #define O2_MHPG_CSC_ENA 0x10
122:
123: #define O2_FIFO_ENA 0x3d
124: #define O2_FIFO_ZVIDEO_3 0x08
125: #define O2_FIFO_PCI_FIFO 0x10
126: #define O2_FIFO_POSTWR 0x40
127: #define O2_FIFO_BUFFER 0x80
128:
129: #define O2_MODE_E 0x3e
130: #define O2_MODE_E_MHPG_DMA 0x01
131: #define O2_MODE_E_SPKR_OUT 0x02
132: #define O2_MODE_E_LED_OUT 0x08
133: #define O2_MODE_E_SKTA_ACTV 0x10
134:
135: /* Data structure for tracking vendor-specific state */
136: typedef struct o2micro_state_t {
137: u_char mode_a; /* O2_MODE_A */
138: u_char mode_b; /* O2_MODE_B */
139: u_char mode_c; /* O2_MODE_C */
140: u_char mode_d; /* O2_MODE_D */
141: u_char mhpg; /* O2_MHPG_DMA */
142: u_char fifo; /* O2_FIFO_ENA */
143: u_char mode_e; /* O2_MODE_E */
144: } o2micro_state_t;
145:
146: #define O2MICRO_PCIC_ID \
147: IS_OZ6729, IS_OZ6730, IS_OZ6832, IS_OZ6836, IS_OZ6812, \
148: IS_OZ6922, IS_OZ6933, IS_OZ6912
149:
150: #define O2MICRO_PCIC_INFO \
151: { "O2Micro OZ6729", IS_O2MICRO|IS_PCI|IS_VG_PWR, ID(O2, 6729) }, \
152: { "O2Micro OZ6730", IS_O2MICRO|IS_PCI|IS_VG_PWR, ID(O2, 6730) }, \
153: { "O2Micro OZ6832/33", IS_O2MICRO|IS_CARDBUS, ID(O2, 6832) }, \
154: { "O2Micro OZ6836/60", IS_O2MICRO|IS_CARDBUS, ID(O2, 6836) }, \
155: { "O2Micro OZ6812", IS_O2MICRO|IS_CARDBUS, ID(O2, 6812) }, \
156: { "O2Micro OZ6922", IS_O2MICRO|IS_CARDBUS, ID(O2, 6922) }, \
157: { "O2Micro OZ6933", IS_O2MICRO|IS_CARDBUS, ID(O2, 6933) }, \
158: { "O2Micro OZ6912", IS_O2MICRO|IS_CARDBUS, ID(O2, 6912) }
159:
160: #endif /* _LINUX_O2MICRO_H */
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