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1.1 root 1: /*
2: * ti113x.h 1.32 2003/02/13 06:28:09
3: *
4: * The contents of this file are subject to the Mozilla Public License
5: * Version 1.1 (the "License"); you may not use this file except in
6: * compliance with the License. You may obtain a copy of the License
7: * at http://www.mozilla.org/MPL/
8: *
9: * Software distributed under the License is distributed on an "AS IS"
10: * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
11: * the License for the specific language governing rights and
12: * limitations under the License.
13: *
14: * The initial developer of the original code is David A. Hinds
15: * <[email protected]>. Portions created by David A. Hinds
16: * are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
17: *
18: * Alternatively, the contents of this file may be used under the
19: * terms of the GNU General Public License version 2 (the "GPL"), in
20: * which case the provisions of the GPL are applicable instead of the
21: * above. If you wish to allow the use of your version of this file
22: * only under the terms of the GPL and not to allow others to use
23: * your version of this file under the MPL, indicate your decision by
24: * deleting the provisions above and replace them with the notice and
25: * other provisions required by the GPL. If you do not delete the
26: * provisions above, a recipient may use your version of this file
27: * under either the MPL or the GPL.
28: */
29:
30: #ifndef _LINUX_TI113X_H
31: #define _LINUX_TI113X_H
32:
33: #ifndef PCI_VENDOR_ID_TI
34: #define PCI_VENDOR_ID_TI 0x104c
35: #endif
36:
37: #ifndef PCI_DEVICE_ID_TI_1130
38: #define PCI_DEVICE_ID_TI_1130 0xac12
39: #endif
40: #ifndef PCI_DEVICE_ID_TI_1031
41: #define PCI_DEVICE_ID_TI_1031 0xac13
42: #endif
43: #ifndef PCI_DEVICE_ID_TI_1131
44: #define PCI_DEVICE_ID_TI_1131 0xac15
45: #endif
46: #ifndef PCI_DEVICE_ID_TI_1210
47: #define PCI_DEVICE_ID_TI_1210 0xac1a
48: #endif
49: #ifndef PCI_DEVICE_ID_TI_1211
50: #define PCI_DEVICE_ID_TI_1211 0xac1e
51: #endif
52: #ifndef PCI_DEVICE_ID_TI_1220
53: #define PCI_DEVICE_ID_TI_1220 0xac17
54: #endif
55: #ifndef PCI_DEVICE_ID_TI_1221
56: #define PCI_DEVICE_ID_TI_1221 0xac19
57: #endif
58: #ifndef PCI_DEVICE_ID_TI_1250A
59: #define PCI_DEVICE_ID_TI_1250A 0xac16
60: #endif
61: #ifndef PCI_DEVICE_ID_TI_1225
62: #define PCI_DEVICE_ID_TI_1225 0xac1c
63: #endif
64: #ifndef PCI_DEVICE_ID_TI_1251A
65: #define PCI_DEVICE_ID_TI_1251A 0xac1d
66: #endif
67: #ifndef PCI_DEVICE_ID_TI_1251B
68: #define PCI_DEVICE_ID_TI_1251B 0xac1f
69: #endif
70: #ifndef PCI_DEVICE_ID_TI_1410
71: #define PCI_DEVICE_ID_TI_1410 0xac50
72: #endif
73: #ifndef PCI_DEVICE_ID_TI_1420
74: #define PCI_DEVICE_ID_TI_1420 0xac51
75: #endif
76: #ifndef PCI_DEVICE_ID_TI_1450
77: #define PCI_DEVICE_ID_TI_1450 0xac1b
78: #endif
79: #ifndef PCI_DEVICE_ID_TI_1451
80: #define PCI_DEVICE_ID_TI_1451 0xac52
81: #endif
82: #ifndef PCI_DEVICE_ID_TI_1510
83: #define PCI_DEVICE_ID_TI_1510 0xac56
84: #endif
85: #ifndef PCI_DEVICE_ID_TI_1520
86: #define PCI_DEVICE_ID_TI_1520 0xac55
87: #endif
88: #ifndef PCI_DEVICE_ID_TI_1620
89: #define PCI_DEVICE_ID_TI_1620 0xac54
90: #endif
91: #ifndef PCI_DEVICE_ID_TI_4410
92: #define PCI_DEVICE_ID_TI_4410 0xac41
93: #endif
94: #ifndef PCI_DEVICE_ID_TI_4450
95: #define PCI_DEVICE_ID_TI_4450 0xac40
96: #endif
97: #ifndef PCI_DEVICE_ID_TI_4451
98: #define PCI_DEVICE_ID_TI_4451 0xac42
99: #endif
100: #ifndef PCI_DEVICE_ID_TI_4510
101: #define PCI_DEVICE_ID_TI_4510 0xac44
102: #endif
103: #ifndef PCI_DEVICE_ID_TI_4520
104: #define PCI_DEVICE_ID_TI_4520 0xac46
105: #endif
106: #ifndef PCI_DEVICE_ID_TI_7410
107: #define PCI_DEVICE_ID_TI_7410 0xac49
108: #endif
109: #ifndef PCI_DEVICE_ID_TI_7510
110: #define PCI_DEVICE_ID_TI_7510 0xac47
111: #endif
112: #ifndef PCI_DEVICE_ID_TI_7610
113: #define PCI_DEVICE_ID_TI_7610 0xac48
114: #endif
115:
116: /* Register definitions for TI 113X PCI-to-CardBus bridges */
117:
118: /* System Control Register */
119: #define TI113X_SYSTEM_CONTROL 0x80 /* 32 bit */
120: #define TI113X_SCR_SMIROUTE 0x04000000
121: #define TI113X_SCR_SMISTATUS 0x02000000
122: #define TI113X_SCR_SMIENB 0x01000000
123: #define TI113X_SCR_VCCPROT 0x00200000
124: #define TI113X_SCR_REDUCEZV 0x00100000
125: #define TI113X_SCR_CDREQEN 0x00080000
126: #define TI113X_SCR_CDMACHAN 0x00070000
127: #define TI113X_SCR_SOCACTIVE 0x00002000
128: #define TI113X_SCR_PWRSTREAM 0x00000800
129: #define TI113X_SCR_DELAYUP 0x00000400
130: #define TI113X_SCR_DELAYDOWN 0x00000200
131: #define TI113X_SCR_INTERROGATE 0x00000100
132: #define TI113X_SCR_CLKRUN_SEL 0x00000080
133: #define TI113X_SCR_PWRSAVINGS 0x00000040
134: #define TI113X_SCR_SUBSYSRW 0x00000020
135: #define TI113X_SCR_CB_DPAR 0x00000010
136: #define TI113X_SCR_CDMA_EN 0x00000008
137: #define TI113X_SCR_ASYNC_IRQ 0x00000004
138: #define TI113X_SCR_KEEPCLK 0x00000002
139: #define TI113X_SCR_CLKRUN_ENA 0x00000001
140:
141: #define TI122X_SCR_SER_STEP 0xc0000000
142: #define TI122X_SCR_INTRTIE 0x20000000
143: #define TI122X_SCR_P2CCLK 0x08000000
144: #define TI122X_SCR_CBRSVD 0x00400000
145: #define TI122X_SCR_MRBURSTDN 0x00008000
146: #define TI122X_SCR_MRBURSTUP 0x00004000
147: #define TI122X_SCR_RIMUX 0x00000001
148:
149: /* Multimedia Control Register */
150: #define TI1250_MULTIMEDIA_CTL 0x84 /* 8 bit */
151: #define TI1250_MMC_ZVOUTEN 0x80
152: #define TI1250_MMC_PORTSEL 0x40
153: #define TI1250_MMC_ZVEN1 0x02
154: #define TI1250_MMC_ZVEN0 0x01
155:
156: #define TI1250_GENERAL_STATUS 0x85 /* 8 bit */
157: #define TI1250_GPIO0_CONTROL 0x88 /* 8 bit */
158: #define TI1250_GPIO1_CONTROL 0x89 /* 8 bit */
159: #define TI1250_GPIO2_CONTROL 0x8a /* 8 bit */
160: #define TI1250_GPIO3_CONTROL 0x8b /* 8 bit */
161: #define TI12XX_IRQMUX 0x8c /* 32 bit */
162:
163: /* Retry Status Register */
164: #define TI113X_RETRY_STATUS 0x90 /* 8 bit */
165: #define TI113X_RSR_PCIRETRY 0x80
166: #define TI113X_RSR_CBRETRY 0x40
167: #define TI113X_RSR_TEXP_CBB 0x20
168: #define TI113X_RSR_MEXP_CBB 0x10
169: #define TI113X_RSR_TEXP_CBA 0x08
170: #define TI113X_RSR_MEXP_CBA 0x04
171: #define TI113X_RSR_TEXP_PCI 0x02
172: #define TI113X_RSR_MEXP_PCI 0x01
173:
174: /* Card Control Register */
175: #define TI113X_CARD_CONTROL 0x91 /* 8 bit */
176: #define TI113X_CCR_RIENB 0x80
177: #define TI113X_CCR_ZVENABLE 0x40
178: #define TI113X_CCR_PCI_IRQ_ENA 0x20
179: #define TI113X_CCR_PCI_IREQ 0x10
180: #define TI113X_CCR_PCI_CSC 0x08
181: #define TI113X_CCR_SPKROUTEN 0x02
182: #define TI113X_CCR_IFG 0x01
183:
184: #define TI1220_CCR_PORT_SEL 0x20
185: #define TI122X_CCR_AUD2MUX 0x04
186:
187: /* Device Control Register */
188: #define TI113X_DEVICE_CONTROL 0x92 /* 8 bit */
189: #define TI113X_DCR_5V_FORCE 0x40
190: #define TI113X_DCR_3V_FORCE 0x20
191: #define TI113X_DCR_IMODE_MASK 0x06
192: #define TI113X_DCR_IMODE_ISA 0x02
193: #define TI113X_DCR_IMODE_SERIAL 0x04
194:
195: #define TI12XX_DCR_IMODE_PCI_ONLY 0x00
196: #define TI12XX_DCR_IMODE_ALL_SERIAL 0x06
197:
198: /* Buffer Control Register */
199: #define TI113X_BUFFER_CONTROL 0x93 /* 8 bit */
200: #define TI113X_BCR_CB_READ_DEPTH 0x08
201: #define TI113X_BCR_CB_WRITE_DEPTH 0x04
202: #define TI113X_BCR_PCI_READ_DEPTH 0x02
203: #define TI113X_BCR_PCI_WRITE_DEPTH 0x01
204:
205: /* Diagnostic Register */
206: #define TI1250_DIAGNOSTIC 0x93 /* 8 bit */
207: #define TI1250_DIAG_TRUE_VALUE 0x80
208: #define TI1250_DIAG_PCI_IREQ 0x40
209: #define TI1250_DIAG_PCI_CSC 0x20
210: #define TI1250_DIAG_ASYNC_CSC 0x01
211:
212: /* DMA Registers */
213: #define TI113X_DMA_0 0x94 /* 32 bit */
214: #define TI113X_DMA_1 0x98 /* 32 bit */
215:
216: /* ExCA IO offset registers */
217: #define TI113X_IO_OFFSET(map) (0x36+((map)<<1))
218:
219: /* Data structure for tracking vendor-specific state */
220: typedef struct ti113x_state_t {
221: u32 sysctl; /* TI113X_SYSTEM_CONTROL */
222: u8 cardctl; /* TI113X_CARD_CONTROL */
223: u8 devctl; /* TI113X_DEVICE_CONTROL */
224: u8 diag; /* TI1250_DIAGNOSTIC */
225: u32 irqmux; /* TI12XX_IRQMUX */
226: } ti113x_state_t;
227:
228: #define TI_PCIC_ID \
229: IS_TI1130, IS_TI1131, IS_TI1031, IS_TI1210, IS_TI1211, \
230: IS_TI1220, IS_TI1221, IS_TI1225, IS_TI1250A, IS_TI1251A, \
231: IS_TI1251B, IS_TI1410, IS_TI1420, IS_TI1450, IS_TI1451, \
232: IS_TI1510, IS_TI1520, IS_TI1620, IS_TI4410, IS_TI4450, \
233: IS_TI4451, IS_TI4510, IS_TI4520, IS_TI7410, IS_TI7510, \
234: IS_TI7610
235:
236: #define TI_PCIC_INFO \
237: { "TI 1130", IS_TI|IS_CARDBUS, ID(TI, 1130) }, \
238: { "TI 1131", IS_TI|IS_CARDBUS, ID(TI, 1131) }, \
239: { "TI 1031", IS_TI|IS_CARDBUS, ID(TI, 1031) }, \
240: { "TI 1210", IS_TI|IS_CARDBUS, ID(TI, 1210) }, \
241: { "TI 1211", IS_TI|IS_CARDBUS, ID(TI, 1211) }, \
242: { "TI 1220", IS_TI|IS_CARDBUS, ID(TI, 1220) }, \
243: { "TI 1221", IS_TI|IS_CARDBUS, ID(TI, 1221) }, \
244: { "TI 1225", IS_TI|IS_CARDBUS, ID(TI, 1225) }, \
245: { "TI 1250A", IS_TI|IS_CARDBUS, ID(TI, 1250A) }, \
246: { "TI 1251A", IS_TI|IS_CARDBUS, ID(TI, 1251A) }, \
247: { "TI 1251B", IS_TI|IS_CARDBUS, ID(TI, 1251B) }, \
248: { "TI 1410", IS_TI|IS_CARDBUS, ID(TI, 1410) }, \
249: { "TI 1420", IS_TI|IS_CARDBUS, ID(TI, 1420) }, \
250: { "TI 1450", IS_TI|IS_CARDBUS, ID(TI, 1450) }, \
251: { "TI 1451", IS_TI|IS_CARDBUS, ID(TI, 1451) }, \
252: { "TI 1510", IS_TI|IS_CARDBUS, ID(TI, 1510) }, \
253: { "TI 1520", IS_TI|IS_CARDBUS, ID(TI, 1520) }, \
254: { "TI 1620", IS_TI|IS_CARDBUS, ID(TI, 1620) }, \
255: { "TI 4410", IS_TI|IS_CARDBUS, ID(TI, 4410) }, \
256: { "TI 4450", IS_TI|IS_CARDBUS, ID(TI, 4450) }, \
257: { "TI 4451", IS_TI|IS_CARDBUS, ID(TI, 4451) }, \
258: { "TI 4510", IS_TI|IS_CARDBUS, ID(TI, 4510) }, \
259: { "TI 4520", IS_TI|IS_CARDBUS, ID(TI, 4520) }, \
260: { "TI 7410", IS_TI|IS_CARDBUS, ID(TI, 7410) }, \
261: { "TI 7510", IS_TI|IS_CARDBUS, ID(TI, 7510) }, \
262: { "TI 7610", IS_TI|IS_CARDBUS, ID(TI, 7610) }
263:
264: #endif /* _LINUX_TI113X_H */
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