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1.1 root 1: /*
2: * yenta.h 1.20 2001/08/24 12:15:34
3: *
4: * The contents of this file are subject to the Mozilla Public License
5: * Version 1.1 (the "License"); you may not use this file except in
6: * compliance with the License. You may obtain a copy of the License
7: * at http://www.mozilla.org/MPL/
8: *
9: * Software distributed under the License is distributed on an "AS IS"
10: * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
11: * the License for the specific language governing rights and
12: * limitations under the License.
13: *
14: * The initial developer of the original code is David A. Hinds
15: * <[email protected]>. Portions created by David A. Hinds
16: * are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
17: *
18: * Alternatively, the contents of this file may be used under the
19: * terms of the GNU General Public License version 2 (the "GPL"), in
20: * which case the provisions of the GPL are applicable instead of the
21: * above. If you wish to allow the use of your version of this file
22: * only under the terms of the GPL and not to allow others to use
23: * your version of this file under the MPL, indicate your decision by
24: * deleting the provisions above and replace them with the notice and
25: * other provisions required by the GPL. If you do not delete the
26: * provisions above, a recipient may use your version of this file
27: * under either the MPL or the GPL.
28: */
29:
30: #ifndef _LINUX_YENTA_H
31: #define _LINUX_YENTA_H
32:
33: /* PCI Configuration Registers */
34:
35: #define PCI_STATUS_CAPLIST 0x10
36: #define PCI_CB_CAPABILITY_POINTER 0x14 /* 8 bit */
37: #define PCI_CAPABILITY_ID 0x00 /* 8 bit */
38: #define PCI_CAPABILITY_PM 0x01
39: #define PCI_NEXT_CAPABILITY 0x01 /* 8 bit */
40: #define PCI_PM_CAPABILITIES 0x02 /* 16 bit */
41: #define PCI_PMCAP_PME_D3COLD 0x8000
42: #define PCI_PMCAP_PME_D3HOT 0x4000
43: #define PCI_PMCAP_PME_D2 0x2000
44: #define PCI_PMCAP_PME_D1 0x1000
45: #define PCI_PMCAP_PME_D0 0x0800
46: #define PCI_PMCAP_D2_CAP 0x0400
47: #define PCI_PMCAP_D1_CAP 0x0200
48: #define PCI_PMCAP_DYN_DATA 0x0100
49: #define PCI_PMCAP_DSI 0x0020
50: #define PCI_PMCAP_AUX_PWR 0x0010
51: #define PCI_PMCAP_PMECLK 0x0008
52: #define PCI_PMCAP_VERSION_MASK 0x0007
53: #define PCI_PM_CONTROL_STATUS 0x04 /* 16 bit */
54: #define PCI_PMCS_PME_STATUS 0x8000
55: #define PCI_PMCS_DATASCALE_MASK 0x6000
56: #define PCI_PMCS_DATASCALE_SHIFT 13
57: #define PCI_PMCS_DATASEL_MASK 0x1e00
58: #define PCI_PMCS_DATASEL_SHIFT 9
59: #define PCI_PMCS_PME_ENABLE 0x0100
60: #define PCI_PMCS_PWR_STATE_MASK 0x0003
61: #define PCI_PMCS_PWR_STATE_D0 0x0000
62: #define PCI_PMCS_PWR_STATE_D1 0x0001
63: #define PCI_PMCS_PWR_STATE_D2 0x0002
64: #define PCI_PMCS_PWR_STATE_D3 0x0003
65: #define PCI_PM_BRIDGE_EXT 0x06 /* 8 bit */
66: #define PCI_PM_DATA 0x07 /* 8 bit */
67:
68: #define CB_PRIMARY_BUS 0x18 /* 8 bit */
69: #define CB_CARDBUS_BUS 0x19 /* 8 bit */
70: #define CB_SUBORD_BUS 0x1a /* 8 bit */
71: #define CB_LATENCY_TIMER 0x1b /* 8 bit */
72:
73: #define CB_MEM_BASE(m) (0x1c + 8*(m))
74: #define CB_MEM_LIMIT(m) (0x20 + 8*(m))
75: #define CB_IO_BASE(m) (0x2c + 8*(m))
76: #define CB_IO_LIMIT(m) (0x30 + 8*(m))
77:
78: #define CB_BRIDGE_CONTROL 0x3e /* 16 bit */
79: #define CB_BCR_PARITY_ENA 0x0001
80: #define CB_BCR_SERR_ENA 0x0002
81: #define CB_BCR_ISA_ENA 0x0004
82: #define CB_BCR_VGA_ENA 0x0008
83: #define CB_BCR_MABORT 0x0020
84: #define CB_BCR_CB_RESET 0x0040
85: #define CB_BCR_ISA_IRQ 0x0080
86: #define CB_BCR_PREFETCH(m) (0x0100 << (m))
87: #define CB_BCR_WRITE_POST 0x0400
88:
89: #define CB_LEGACY_MODE_BASE 0x44
90:
91: /* Memory mapped registers */
92:
93: #define CB_SOCKET_EVENT 0x0000
94: #define CB_SE_CSTSCHG 0x00000001
95: #define CB_SE_CCD 0x00000006
96: #define CB_SE_CCD1 0x00000002
97: #define CB_SE_CCD2 0x00000004
98: #define CB_SE_PWRCYCLE 0x00000008
99:
100: #define CB_SOCKET_MASK 0x0004
101: #define CB_SM_CSTSCHG 0x00000001
102: #define CB_SM_CCD 0x00000006
103: #define CB_SM_PWRCYCLE 0x00000008
104:
105: #define CB_SOCKET_STATE 0x0008
106: #define CB_SS_CSTSCHG 0x00000001
107: #define CB_SS_CCD 0x00000006
108: #define CB_SS_CCD1 0x00000002
109: #define CB_SS_CCD2 0x00000004
110: #define CB_SS_PWRCYCLE 0x00000008
111: #define CB_SS_16BIT 0x00000010
112: #define CB_SS_32BIT 0x00000020
113: #define CB_SS_CINT 0x00000040
114: #define CB_SS_BADCARD 0x00000080
115: #define CB_SS_DATALOST 0x00000100
116: #define CB_SS_BADVCC 0x00000200
117: #define CB_SS_5VCARD 0x00000400
118: #define CB_SS_3VCARD 0x00000800
119: #define CB_SS_XVCARD 0x00001000
120: #define CB_SS_YVCARD 0x00002000
121: #define CB_SS_VSENSE 0x00003c86
122: #define CB_SS_5VSOCKET 0x10000000
123: #define CB_SS_3VSOCKET 0x20000000
124: #define CB_SS_XVSOCKET 0x40000000
125: #define CB_SS_YVSOCKET 0x80000000
126:
127: #define CB_SOCKET_FORCE 0x000c
128: #define CB_SF_CVSTEST 0x00004000
129:
130: #define CB_SOCKET_CONTROL 0x0010
131: #define CB_SC_VPP_MASK 0x00000007
132: #define CB_SC_VPP_OFF 0x00000000
133: #define CB_SC_VPP_12V 0x00000001
134: #define CB_SC_VPP_5V 0x00000002
135: #define CB_SC_VPP_3V 0x00000003
136: #define CB_SC_VPP_XV 0x00000004
137: #define CB_SC_VPP_YV 0x00000005
138: #define CB_SC_VCC_MASK 0x00000070
139: #define CB_SC_VCC_OFF 0x00000000
140: #define CB_SC_VCC_5V 0x00000020
141: #define CB_SC_VCC_3V 0x00000030
142: #define CB_SC_VCC_XV 0x00000040
143: #define CB_SC_VCC_YV 0x00000050
144: #define CB_SC_CCLK_STOP 0x00000080
145:
146: #define CB_SOCKET_POWER 0x0020
147: #define CB_SP_CLK_CTRL 0x00000001
148: #define CB_SP_CLK_CTRL_ENA 0x00010000
149: #define CB_SP_CLK_MODE 0x01000000
150: #define CB_SP_ACCESS 0x02000000
151:
152: /* Address bits 31..24 for memory windows for 16-bit cards,
153: accessable only by memory mapping the 16-bit register set */
154: #define CB_MEM_PAGE(map) (0x40 + (map))
155:
156: #endif /* _LINUX_YENTA_H */
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