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1.1 root 1: /*
2: * linux/drivers/block/triton.c Version 1.13 Aug 12, 1996
3: *
4: * Copyright (c) 1995-1996 Mark Lord
5: * May be copied or modified under the terms of the GNU General Public License
6: */
7:
8: /*
9: * This module provides support for the Bus Master IDE DMA function
10: * of the Intel PCI Triton I/II chipsets (i82371FB or i82371SB).
11: *
12: * Pretty much the same code will work for the OPTi "Viper" chipset.
13: * Look for DMA support for this in linux kernel 2.1.xx, when it appears.
14: *
15: * DMA is currently supported only for hard disk drives (not cdroms).
16: *
17: * Support for cdroms will likely be added at a later date,
18: * after broader experience has been obtained with hard disks.
19: *
20: * Up to four drives may be enabled for DMA, and the Triton chipset will
21: * (hopefully) arbitrate the PCI bus among them. Note that the i82371 chip
22: * provides a single "line buffer" for the BM IDE function, so performance of
23: * multiple (two) drives doing DMA simultaneously will suffer somewhat,
24: * as they contest for that resource bottleneck. This is handled transparently
25: * inside the i82371 chip.
26: *
27: * By default, DMA support is prepared for use, but is currently enabled only
28: * for drives which support multi-word DMA mode2 (mword2), or which are
29: * recognized as "good" (see table below). Drives with only mode0 or mode1
30: * (single or multi) DMA should also work with this chipset/driver (eg. MC2112A)
31: * but are not enabled by default. Use "hdparm -i" to view modes supported
32: * by a given drive.
33: *
34: * The hdparm-2.4 (or later) utility can be used for manually enabling/disabling
35: * DMA support, but must be (re-)compiled against this kernel version or later.
36: *
37: * To enable DMA, use "hdparm -d1 /dev/hd?" on a per-drive basis after booting.
38: * If problems arise, ide.c will disable DMA operation after a few retries.
39: * This error recovery mechanism works and has been extremely well exercised.
40: *
41: * IDE drives, depending on their vintage, may support several different modes
42: * of DMA operation. The boot-time modes are indicated with a "*" in
43: * the "hdparm -i" listing, and can be changed with *knowledgeable* use of
44: * the "hdparm -X" feature. There is seldom a need to do this, as drives
45: * normally power-up with their "best" PIO/DMA modes enabled.
46: *
47: * Testing was done with an ASUS P55TP4XE/100 system and the following drives:
48: *
49: * Quantum Fireball 1080A (1Gig w/83kB buffer), DMA mode2, PIO mode4.
50: * - DMA mode2 works well (7.4MB/sec), despite the tiny on-drive buffer.
51: * - This drive also does PIO mode4, at about the same speed as DMA mode2.
52: * An awesome drive for the price!
53: *
54: * Fujitsu M1606TA (1Gig w/256kB buffer), DMA mode2, PIO mode4.
55: * - DMA mode2 gives horrible performance (1.6MB/sec), despite the good
56: * size of the on-drive buffer and a boasted 10ms average access time.
57: * - PIO mode4 was better, but peaked at a mere 4.5MB/sec.
58: *
59: * Micropolis MC2112A (1Gig w/508kB buffer), drive pre-dates EIDE and ATA2.
60: * - DMA works fine (2.2MB/sec), probably due to the large on-drive buffer.
61: * - This older drive can also be tweaked for fastPIO (3.7MB/sec) by using
62: * maximum clock settings (5,4) and setting all flags except prefetch.
63: *
64: * Western Digital AC31000H (1Gig w/128kB buffer), DMA mode1, PIO mode3.
65: * - DMA does not work reliably. The drive appears to be somewhat tardy
66: * in deasserting DMARQ at the end of a sector. This is evident in
67: * the observation that WRITEs work most of the time, depending on
68: * cache-buffer occupancy, but multi-sector reads seldom work.
69: *
70: * Testing was done with a Gigabyte GA-586 ATE system and the following drive:
71: * (Uwe Bonnes - [email protected])
72: *
73: * Western Digital AC31600H (1.6Gig w/128kB buffer), DMA mode2, PIO mode4.
74: * - much better than its 1Gig cousin, this drive is reported to work
75: * very well with DMA (7.3MB/sec).
76: *
77: * Other drives:
78: *
79: * Maxtor 7540AV (515Meg w/32kB buffer), DMA modes mword0/sword2, PIO mode3.
80: * - a budget drive, with budget performance, around 3MB/sec.
81: *
82: * Western Digital AC2850F (814Meg w/64kB buffer), DMA mode1, PIO mode3.
83: * - another "caviar" drive, similar to the AC31000, except that this one
84: * worked with DMA in at least one system. Throughput is about 3.8MB/sec
85: * for both DMA and PIO.
86: *
87: * Conner CFS850A (812Meg w/64kB buffer), DMA mode2, PIO mode4.
88: * - like most Conner models, this drive proves that even a fast interface
89: * cannot improve slow media. Both DMA and PIO peak around 3.5MB/sec.
90: *
91: * Maxtor 71260AT (1204Meg w/256kB buffer), DMA mword0/sword2, PIO mode3.
92: * - works with DMA, on some systems (but not always on others, eg. Dell),
93: * giving 3-4MB/sec performance, about the same as mode3.
94: *
95: * If you have any drive models to add, email your results to: [email protected]
96: * Keep an eye on /var/adm/messages for "DMA disabled" messages.
97: *
98: * Some people have reported trouble with Intel Zappa motherboards.
99: * This can be fixed by upgrading the AMI BIOS to version 1.00.04.BS0,
100: * available from ftp://ftp.intel.com/pub/bios/10004bs0.exe
101: * (thanks to Glen Morrell <[email protected]> for researching this).
102: *
103: * And, yes, Intel Zappa boards really *do* use the Triton IDE ports.
104: */
105: #include <linux/config.h>
106: #include <linux/types.h>
107: #include <linux/kernel.h>
108: #include <linux/timer.h>
109: #include <linux/mm.h>
110: #include <linux/ioport.h>
111: #include <linux/interrupt.h>
112: #include <linux/blkdev.h>
113: #include <linux/hdreg.h>
114: #include <linux/pci.h>
115: #include <linux/bios32.h>
116:
117: #include <asm/io.h>
118: #include <asm/dma.h>
119:
120: #include "ide.h"
121:
122: #undef DISPLAY_TRITON_TIMINGS /* define this to display timings */
123:
124: /*
125: * good_dma_drives() lists the model names (from "hdparm -i")
126: * of drives which do not support mword2 DMA but which are
127: * known to work fine with this interface under Linux.
128: */
129: const char *good_dma_drives[] = {"Micropolis 2112A",
130: "CONNER CTMA 4000",
131: "CONNER CTT8000-A",
132: NULL};
133:
134: /*
135: * Our Physical Region Descriptor (PRD) table should be large enough
136: * to handle the biggest I/O request we are likely to see. Since requests
137: * can have no more than 256 sectors, and since the typical blocksize is
138: * two sectors, we could get by with a limit of 128 entries here for the
139: * usual worst case. Most requests seem to include some contiguous blocks,
140: * further reducing the number of table entries required.
141: *
142: * The driver reverts to PIO mode for individual requests that exceed
143: * this limit (possible with 512 byte blocksizes, eg. MSDOS f/s), so handling
144: * 100% of all crazy scenarios here is not necessary.
145: *
146: * As it turns out though, we must allocate a full 4KB page for this,
147: * so the two PRD tables (ide0 & ide1) will each get half of that,
148: * allowing each to have about 256 entries (8 bytes each) from this.
149: */
150: #define PRD_BYTES 8
151: #define PRD_ENTRIES (PAGE_SIZE / (2 * PRD_BYTES))
152: #define DEFAULT_BMIBA 0xe800 /* in case BIOS did not init it */
153:
154: /*
155: * dma_intr() is the handler for disk read/write DMA interrupts
156: */
157: static void dma_intr (ide_drive_t *drive)
158: {
159: byte stat, dma_stat;
160: int i;
161: struct request *rq = HWGROUP(drive)->rq;
162: unsigned short dma_base = HWIF(drive)->dma_base;
163:
164: dma_stat = inb(dma_base+2); /* get DMA status */
165: outb(inb(dma_base)&~1, dma_base); /* stop DMA operation */
166: stat = GET_STAT(); /* get drive status */
167: if (OK_STAT(stat,DRIVE_READY,drive->bad_wstat|DRQ_STAT)) {
168: if ((dma_stat & 7) == 4) { /* verify good DMA status */
169: rq = HWGROUP(drive)->rq;
170: for (i = rq->nr_sectors; i > 0;) {
171: i -= rq->current_nr_sectors;
172: ide_end_request(1, HWGROUP(drive));
173: }
174: return;
175: }
176: printk("%s: bad DMA status: 0x%02x\n", drive->name, dma_stat);
177: }
178: sti();
179: ide_error(drive, "dma_intr", stat);
180: }
181:
182: /*
183: * build_dmatable() prepares a dma request.
184: * Returns 0 if all went okay, returns 1 otherwise.
185: */
186: static int build_dmatable (ide_drive_t *drive)
187: {
188: struct request *rq = HWGROUP(drive)->rq;
189: struct buffer_head *bh = rq->bh;
190: unsigned long size, addr, *table = HWIF(drive)->dmatable;
191: unsigned int count = 0;
192:
193: do {
194: /*
195: * Determine addr and size of next buffer area. We assume that
196: * individual virtual buffers are always composed linearly in
197: * physical memory. For example, we assume that any 8kB buffer
198: * is always composed of two adjacent physical 4kB pages rather
199: * than two possibly non-adjacent physical 4kB pages.
200: */
201: if (bh == NULL) { /* paging and tape requests have (rq->bh == NULL) */
202: addr = virt_to_bus (rq->buffer);
203: #ifdef CONFIG_BLK_DEV_IDETAPE
204: if (drive->media == ide_tape)
205: size = drive->tape.pc->request_transfer;
206: else
207: #endif /* CONFIG_BLK_DEV_IDETAPE */
208: size = rq->nr_sectors << 9;
209: } else {
210: /* group sequential buffers into one large buffer */
211: addr = virt_to_bus (bh->b_data);
212: size = bh->b_size;
213: while ((bh = bh->b_reqnext) != NULL) {
214: if ((addr + size) != virt_to_bus (bh->b_data))
215: break;
216: size += bh->b_size;
217: }
218: }
219:
220: /*
221: * Fill in the dma table, without crossing any 64kB boundaries.
222: * We assume 16-bit alignment of all blocks.
223: */
224: while (size) {
225: if (++count >= PRD_ENTRIES) {
226: printk("%s: DMA table too small\n", drive->name);
227: return 1; /* revert to PIO for this request */
228: } else {
229: unsigned long bcount = 0x10000 - (addr & 0xffff);
230: if (bcount > size)
231: bcount = size;
232: *table++ = addr;
233: *table++ = bcount & 0xffff;
234: addr += bcount;
235: size -= bcount;
236: }
237: }
238: } while (bh != NULL);
239: if (count) {
240: *--table |= 0x80000000; /* set End-Of-Table (EOT) bit */
241: return 0;
242: }
243: printk("%s: empty DMA table?\n", drive->name);
244: return 1; /* let the PIO routines handle this weirdness */
245: }
246:
247: static int config_drive_for_dma (ide_drive_t *drive)
248: {
249: const char **list;
250: struct hd_driveid *id = drive->id;
251:
252: if (id && (id->capability & 1)) {
253: /* Enable DMA on any drive that has UltraDMA (mode 0/1/2) enabled */
254: if (id->field_valid & 4) /* UltraDMA */
255: if ((id->dma_ultra & (id->dma_ultra >> 8) & 7)) {
256: drive->using_dma = 1;
257: return 0; /* dma enabled */
258: }
259: /* Enable DMA on any drive that has mode2 DMA (multi or single) enabled */
260: if (id->field_valid & 2) /* regular DMA */
261: if ((id->dma_mword & 0x404) == 0x404 || (id->dma_1word & 0x404) == 0x404) {
262: drive->using_dma = 1;
263: return 0; /* dma enabled */
264: }
265: /* Consult the list of known "good" drives */
266: list = good_dma_drives;
267: while (*list) {
268: if (!strcmp(*list++,id->model)) {
269: drive->using_dma = 1;
270: return 0; /* DMA enabled */
271: }
272: }
273: }
274: return 1; /* DMA not enabled */
275: }
276:
277: /*
278: * triton_dmaproc() initiates/aborts DMA read/write operations on a drive.
279: *
280: * The caller is assumed to have selected the drive and programmed the drive's
281: * sector address using CHS or LBA. All that remains is to prepare for DMA
282: * and then issue the actual read/write DMA/PIO command to the drive.
283: *
284: * For ATAPI devices, we just prepare for DMA and return. The caller should
285: * then issue the packet command to the drive and call us again with
286: * ide_dma_begin afterwards.
287: *
288: * Returns 0 if all went well.
289: * Returns 1 if DMA read/write could not be started, in which case
290: * the caller should revert to PIO for the current request.
291: */
292: static int triton_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
293: {
294: unsigned long dma_base = HWIF(drive)->dma_base;
295: unsigned int reading = (1 << 3);
296:
297: switch (func) {
298: case ide_dma_abort:
299: outb(inb(dma_base)&~1, dma_base); /* stop DMA */
300: return 0;
301: case ide_dma_check:
302: return config_drive_for_dma (drive);
303: case ide_dma_write:
304: reading = 0;
305: case ide_dma_read:
306: break;
307: case ide_dma_status_bad:
308: return ((inb(dma_base+2) & 7) != 4); /* verify good DMA status */
309: case ide_dma_transferred:
310: #if 0
311: return (number of bytes actually transferred);
312: #else
313: return (0);
314: #endif
315: case ide_dma_begin:
316: outb(inb(dma_base)|1, dma_base); /* begin DMA */
317: return 0;
318: default:
319: printk("triton_dmaproc: unsupported func: %d\n", func);
320: return 1;
321: }
322: if (build_dmatable (drive))
323: return 1;
324: outl(virt_to_bus (HWIF(drive)->dmatable), dma_base + 4); /* PRD table */
325: outb(reading, dma_base); /* specify r/w */
326: outb(inb(dma_base+2)|0x06, dma_base+2); /* clear status bits */
327: #ifdef CONFIG_BLK_DEV_IDEATAPI
328: if (drive->media != ide_disk)
329: return 0;
330: #endif /* CONFIG_BLK_DEV_IDEATAPI */
331: ide_set_handler(drive, &dma_intr, WAIT_CMD); /* issue cmd to drive */
332: OUT_BYTE(reading ? WIN_READDMA : WIN_WRITEDMA, IDE_COMMAND_REG);
333: outb(inb(dma_base)|1, dma_base); /* begin DMA */
334: return 0;
335: }
336:
337: #ifdef DISPLAY_TRITON_TIMINGS
338: /*
339: * print_triton_drive_flags() displays the currently programmed options
340: * in the i82371 (Triton) for a given drive.
341: *
342: * If fastDMA is "no", then slow ISA timings are used for DMA data xfers.
343: * If fastPIO is "no", then slow ISA timings are used for PIO data xfers.
344: * If IORDY is "no", then IORDY is assumed to always be asserted.
345: * If PreFetch is "no", then data pre-fetch/post are not used.
346: *
347: * When "fastPIO" and/or "fastDMA" are "yes", then faster PCI timings and
348: * back-to-back 16-bit data transfers are enabled, using the sample_CLKs
349: * and recovery_CLKs (PCI clock cycles) timing parameters for that interface.
350: */
351: static void print_triton_drive_flags (unsigned int unit, byte flags)
352: {
353: printk(" %s ", unit ? "slave :" : "master:");
354: printk( "fastDMA=%s", (flags&9) ? "on " : "off");
355: printk(" PreFetch=%s", (flags&4) ? "on " : "off");
356: printk(" IORDY=%s", (flags&2) ? "on " : "off");
357: printk(" fastPIO=%s\n", ((flags&9)==1) ? "on " : "off");
358: }
359: #endif /* DISPLAY_TRITON_TIMINGS */
360:
361: static void init_triton_dma (ide_hwif_t *hwif, unsigned short base)
362: {
363: static unsigned long dmatable = 0;
364:
365: printk(" %s: BM-DMA at 0x%04x-0x%04x", hwif->name, base, base+7);
366: if (check_region(base, 8)) {
367: printk(" -- ERROR, PORTS ALREADY IN USE");
368: } else {
369: request_region(base, 8, "IDE DMA");
370: hwif->dma_base = base;
371: if (!dmatable) {
372: /*
373: * The BM-DMA uses a full 32-bits, so we can
374: * safely use __get_free_page() here instead
375: * of __get_dma_pages() -- no ISA limitations.
376: */
377: dmatable = __get_free_pages(GFP_KERNEL, 1, 0);
378: }
379: if (dmatable) {
380: hwif->dmatable = (unsigned long *) dmatable;
381: dmatable += (PRD_ENTRIES * PRD_BYTES);
382: outl(virt_to_bus(hwif->dmatable), base + 4);
383: hwif->dmaproc = &triton_dmaproc;
384: }
385: }
386: printk("\n");
387: }
388:
389: /*
390: * ide_init_triton() prepares the IDE driver for DMA operation.
391: * This routine is called once, from ide.c during driver initialization,
392: * for each triton chipset which is found (unlikely to be more than one).
393: */
394: void ide_init_triton (byte bus, byte fn)
395: {
396: int rc = 0, h;
397: int dma_enabled = 0;
398: unsigned short pcicmd;
399: unsigned int bmiba, timings;
400:
401: printk("ide: i82371 PIIX (Triton) on PCI bus %d function %d\n", bus, fn);
402: /*
403: * See if IDE and BM-DMA features are enabled:
404: */
405: if ((rc = pcibios_read_config_word(bus, fn, 0x04, &pcicmd)))
406: goto quit;
407: if ((pcicmd & 1) == 0) {
408: printk("ide: ports are not enabled (BIOS)\n");
409: goto quit;
410: }
411: if ((pcicmd & 4) == 0) {
412: printk("ide: BM-DMA feature is not enabled (BIOS)\n");
413: } else {
414: /*
415: * Get the bmiba base address
416: */
417: int try_again = 1;
418: do {
419: if ((rc = pcibios_read_config_dword(bus, fn, 0x20, &bmiba)))
420: goto quit;
421: bmiba &= 0xfff0; /* extract port base address */
422: if (bmiba) {
423: dma_enabled = 1;
424: break;
425: } else {
426: printk("ide: BM-DMA base register is invalid (0x%04x, PnP BIOS problem)\n", bmiba);
427: if (inb(DEFAULT_BMIBA) != 0xff || !try_again)
428: break;
429: printk("ide: setting BM-DMA base register to 0x%04x\n", DEFAULT_BMIBA);
430: if ((rc = pcibios_write_config_word(bus, fn, 0x04, pcicmd&~1)))
431: goto quit;
432: rc = pcibios_write_config_dword(bus, fn, 0x20, DEFAULT_BMIBA|1);
433: if (pcibios_write_config_word(bus, fn, 0x04, pcicmd|5) || rc)
434: goto quit;
435: }
436: } while (try_again--);
437: }
438:
439: /*
440: * See if ide port(s) are enabled
441: */
442: if ((rc = pcibios_read_config_dword(bus, fn, 0x40, &timings)))
443: goto quit;
444: if (!(timings & 0x80008000)) {
445: printk("ide: neither port is enabled\n");
446: goto quit;
447: }
448:
449: /*
450: * Save the dma_base port addr for each interface
451: */
452: for (h = 0; h < MAX_HWIFS; ++h) {
453: #ifdef DISPLAY_TRITON_TIMINGS
454: byte s_clks, r_clks;
455: unsigned short devid;
456: #endif /* DISPLAY_TRITON_TIMINGS */
457: ide_hwif_t *hwif = &ide_hwifs[h];
458: unsigned short time;
459: if (hwif->io_base == 0x1f0) {
460: time = timings & 0xffff;
461: if ((time & 0x8000) == 0) /* interface enabled? */
462: continue;
463: hwif->chipset = ide_triton;
464: if (dma_enabled)
465: init_triton_dma(hwif, bmiba);
466: } else if (hwif->io_base == 0x170) {
467: time = timings >> 16;
468: if ((time & 0x8000) == 0) /* interface enabled? */
469: continue;
470: hwif->chipset = ide_triton;
471: if (dma_enabled)
472: init_triton_dma(hwif, bmiba + 8);
473: } else
474: continue;
475: #ifdef DISPLAY_TRITON_TIMINGS
476: s_clks = ((~time >> 12) & 3) + 2;
477: r_clks = ((~time >> 8) & 3) + 1;
478: printk(" %s timing: (0x%04x) sample_CLKs=%d, recovery_CLKs=%d\n",
479: hwif->name, time, s_clks, r_clks);
480: if ((time & 0x40) && !pcibios_read_config_word(bus, fn, 0x02, &devid)
481: && devid == PCI_DEVICE_ID_INTEL_82371SB_1)
482: {
483: byte stime;
484: if (pcibios_read_config_byte(bus, fn, 0x44, &stime)) {
485: if (hwif->io_base == 0x1f0) {
486: s_clks = ~stime >> 6;
487: r_clks = ~stime >> 4;
488: } else {
489: s_clks = ~stime >> 2;
490: r_clks = ~stime;
491: }
492: s_clks = (s_clks & 3) + 2;
493: r_clks = (r_clks & 3) + 1;
494: printk(" slave: sample_CLKs=%d, recovery_CLKs=%d\n",
495: s_clks, r_clks);
496: }
497: }
498: print_triton_drive_flags (0, time & 0xf);
499: print_triton_drive_flags (1, (time >> 4) & 0xf);
500: #endif /* DISPLAY_TRITON_TIMINGS */
501: }
502:
503: quit: if (rc) printk("ide: pcibios access failed - %s\n", pcibios_strerror(rc));
504: }
505:
506: void ide_init_promise (byte bus, byte fn, ide_hwif_t *hwif0, ide_hwif_t *hwif1, unsigned short dma)
507: {
508: int rc;
509: unsigned short pcicmd;
510: unsigned int bmiba = 0;
511:
512: printk("ide: Enabling DMA for Promise Technology IDE Ultra-DMA 33 on PCI bus %d function %d, port 0x%04x\n", bus, fn, dma);
513: if ((rc = pcibios_read_config_word(bus, fn, 0x04, &pcicmd)) || (pcicmd & 1) == 0 || (pcicmd & 4) == 0)
514: goto abort;
515: if ((rc = pcibios_read_config_dword(bus, fn, 0x20, &bmiba)))
516: goto abort;
517: bmiba &= 0xfff0; /* extract port base address */
518: if (bmiba != dma || !bmiba)
519: goto abort;
520: hwif0->chipset = ide_promise_udma;
521: hwif1->chipset = ide_promise_udma;
522: init_triton_dma(hwif0, bmiba);
523: init_triton_dma(hwif1, bmiba + 0x08);
524: return;
525: abort:
526: printk(KERN_WARNING "ide: Promise/33 not configured correctly (BIOS)\n");
527: }
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