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1.1 root 1: /* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
2: /*
3: Written 1996-1998 by Donald Becker.
4:
5: This software may be used and distributed according to the terms
6: of the GNU Public License, incorporated herein by reference.
7:
8: This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
9: Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
10: and the EtherLink XL 3c900 and 3c905 cards.
11:
12: The author may be reached as [email protected], or C/O
13: Center of Excellence in Space Data and Information Sciences
14: Code 930.5, Goddard Space Flight Center, Greenbelt MD 20771
15: */
16:
17: static char *version =
18: "3c59x.c:v0.99H 11/17/98 Donald Becker http://cesdis.gsfc.nasa.gov/linux/drivers/vortex.html\n";
19:
20: /* "Knobs" that adjust features and parameters. */
21: /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
22: Setting to > 1512 effectively disables this feature. */
23: static const int rx_copybreak = 200;
24: /* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
25: static const int mtu = 1500;
26: /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
27: static int max_interrupt_work = 20;
28:
29: /* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
30: #define vortex_debug debug
31: #ifdef VORTEX_DEBUG
32: static int vortex_debug = VORTEX_DEBUG;
33: #else
34: static int vortex_debug = 1;
35: #endif
36:
37: /* Some values here only for performance evaluation and path-coverage
38: debugging. */
39: static int rx_nocopy = 0, rx_copy = 0, queued_packet = 0, rx_csumhits;
40:
41: /* A few values that may be tweaked. */
42: /* Time in jiffies before concluding the transmitter is hung. */
43: #define TX_TIMEOUT ((400*HZ)/1000)
44:
45: /* Keep the ring sizes a power of two for efficiency. */
46: #define TX_RING_SIZE 16
47: #define RX_RING_SIZE 32
48: #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
49:
50: #include <linux/config.h>
51: #include <linux/version.h>
52: #ifdef MODULE
53: #ifdef MODVERSIONS
54: #include <linux/modversions.h>
55: #endif
56: #include <linux/module.h>
57: #else
58: #define MOD_INC_USE_COUNT
59: #define MOD_DEC_USE_COUNT
60: #endif
61:
62: #include <linux/kernel.h>
63: #include <linux/sched.h>
64: #include <linux/string.h>
65: #include <linux/timer.h>
66: #include <linux/errno.h>
67: #include <linux/in.h>
68: #include <linux/ioport.h>
69: #include <linux/malloc.h>
70: #include <linux/interrupt.h>
71: #include <linux/pci.h>
72: #include <linux/netdevice.h>
73: #include <linux/etherdevice.h>
74: #include <linux/skbuff.h>
75: #if LINUX_VERSION_CODE < 0x20155 || defined(CARDBUS)
76: #include <linux/bios32.h>
77: #endif
78: #include <asm/irq.h> /* For NR_IRQS only. */
79: #include <asm/bitops.h>
80: #include <asm/io.h>
81:
82: /* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
83: This is only in the support-all-kernels source code. */
84:
85: #define RUN_AT(x) (jiffies + (x))
86:
87: #include <linux/delay.h>
88:
89: #if (LINUX_VERSION_CODE <= 0x20100)
90: #ifndef __alpha__
91: #define ioremap(a,b) \
92: (((a)<0x100000) ? (void *)((u_long)(a)) : vremap(a,b))
93: #define iounmap(v) \
94: do { if ((u_long)(v) > 0x100000) vfree(v); } while (0)
95: #endif
96: #endif
97: #if LINUX_VERSION_CODE <= 0x20139
98: #define net_device_stats enet_statistics
99: #define NETSTATS_VER2
100: #endif
101: #if LINUX_VERSION_CODE < 0x20138
102: #define test_and_set_bit(val, addr) set_bit(val, addr)
103: #define le32_to_cpu(val) (val)
104: #define cpu_to_le32(val) (val)
105: #endif
106: #if LINUX_VERSION_CODE < 0x20155
107: #define PCI_SUPPORT_VER1
108: #else
109: #define PCI_SUPPORT_VER2
110: #endif
111: #if LINUX_VERSION_CODE < 0x20159
112: #define DEV_FREE_SKB(skb) dev_kfree_skb (skb, FREE_WRITE);
113: #else /* Grrr, unneeded incompatible change. */
114: #define DEV_FREE_SKB(skb) dev_kfree_skb(skb);
115: #endif
116:
117: #if defined(MODULE) && LINUX_VERSION_CODE > 0x20115
118: MODULE_AUTHOR("Donald Becker <[email protected]>");
119: MODULE_DESCRIPTION("3Com 3c590/3c900 series Vortex/Boomerang driver");
120: MODULE_PARM(debug, "i");
121: MODULE_PARM(options, "1-" __MODULE_STRING(8) "i");
122: MODULE_PARM(full_duplex, "1-" __MODULE_STRING(8) "i");
123: MODULE_PARM(rx_copybreak, "i");
124: MODULE_PARM(max_interrupt_work, "i");
125: MODULE_PARM(compaq_ioaddr, "i");
126: MODULE_PARM(compaq_irq, "i");
127: MODULE_PARM(compaq_device_id, "i");
128: #endif
129:
130: /* Operational parameter that usually are not changed. */
131:
132: /* The Vortex size is twice that of the original EtherLinkIII series: the
133: runtime register window, window 1, is now always mapped in.
134: The Boomerang size is twice as large as the Vortex -- it has additional
135: bus master control registers. */
136: #define VORTEX_TOTAL_SIZE 0x20
137: #define BOOMERANG_TOTAL_SIZE 0x40
138:
139: /* Set iff a MII transceiver on any interface requires mdio preamble.
140: This only set with the original DP83840 on older 3c905 boards, so the extra
141: code size of a per-interface flag is not worthwhile. */
142: static char mii_preamble_required = 0;
143:
144: /*
145: Theory of Operation
146:
147: I. Board Compatibility
148:
149: This device driver is designed for the 3Com FastEtherLink and FastEtherLink
150: XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs
151: versions of the FastEtherLink cards. The supported product IDs are
152: 3c590, 3c592, 3c595, 3c597, 3c900, 3c905
153:
154: The related ISA 3c515 is supported with a separate driver, 3c515.c, included
155: with the kernel source or available from
156: cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
157:
158: II. Board-specific settings
159:
160: PCI bus devices are configured by the system at boot time, so no jumpers
161: need to be set on the board. The system BIOS should be set to assign the
162: PCI INTA signal to an otherwise unused system IRQ line.
163:
164: The EEPROM settings for media type and forced-full-duplex are observed.
165: The EEPROM media type should be left at the default "autoselect" unless using
166: 10base2 or AUI connections which cannot be reliably detected.
167:
168: III. Driver operation
169:
170: The 3c59x series use an interface that's very similar to the previous 3c5x9
171: series. The primary interface is two programmed-I/O FIFOs, with an
172: alternate single-contiguous-region bus-master transfer (see next).
173:
174: The 3c900 "Boomerang" series uses a full-bus-master interface with separate
175: lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
176: DEC Tulip and Intel Speedo3. The first chip version retains a compatible
177: programmed-I/O interface that has been removed in 'B' and subsequent board
178: revisions.
179:
180: One extension that is advertised in a very large font is that the adapters
181: are capable of being bus masters. On the Vortex chip this capability was
182: only for a single contiguous region making it far less useful than the full
183: bus master capability. There is a significant performance impact of taking
184: an extra interrupt or polling for the completion of each transfer, as well
185: as difficulty sharing the single transfer engine between the transmit and
186: receive threads. Using DMA transfers is a win only with large blocks or
187: with the flawed versions of the Intel Orion motherboard PCI controller.
188:
189: The Boomerang chip's full-bus-master interface is useful, and has the
190: currently-unused advantages over other similar chips that queued transmit
191: packets may be reordered and receive buffer groups are associated with a
192: single frame.
193:
194: With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
195: Rather than a fixed intermediate receive buffer, this scheme allocates
196: full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as
197: the copying breakpoint: it is chosen to trade-off the memory wasted by
198: passing the full-sized skbuff to the queue layer for all frames vs. the
199: copying cost of copying a frame to a correctly-sized skbuff.
200:
201:
202: IIIC. Synchronization
203: The driver runs as two independent, single-threaded flows of control. One
204: is the send-packet routine, which enforces single-threaded use by the
205: dev->tbusy flag. The other thread is the interrupt handler, which is single
206: threaded by the hardware and other software.
207:
208: IV. Notes
209:
210: Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
211: 3c590, 3c595, and 3c900 boards.
212: The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
213: the EISA version is called "Demon". According to Terry these names come
214: from rides at the local amusement park.
215:
216: The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
217: This driver only supports ethernet packets because of the skbuff allocation
218: limit of 4K.
219: */
220:
221: /* This table drives the PCI probe routines. It's mostly boilerplate in all
222: of the drivers, and will likely be provided by some future kernel.
223: */
224: enum pci_flags_bit {
225: PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
226: PCI_ADDR0=0x10<<0, PCI_ADDR1=0x10<<1, PCI_ADDR2=0x10<<2, PCI_ADDR3=0x10<<3,
227: };
228: struct pci_id_info {
229: const char *name;
230: u16 vendor_id, device_id, device_id_mask, flags;
231: int drv_flags, io_size;
232: struct device *(*probe1)(int pci_bus, int pci_devfn, struct device *dev,
233: long ioaddr, int irq, int chip_idx, int fnd_cnt);
234: };
235:
236: enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4,
237: HAS_PWR_CTRL=0x10, HAS_MII=0x20, HAS_NWAY=0x40, HAS_CB_FNS=0x80, };
238: static struct device *vortex_probe1(int pci_bus, int pci_devfn,
239: struct device *dev, long ioaddr,
240: int irq, int dev_id, int card_idx);
241: static struct pci_id_info pci_tbl[] = {
242: {"3c590 Vortex 10Mbps", 0x10B7, 0x5900, 0xffff,
243: PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, vortex_probe1},
244: {"3c595 Vortex 100baseTx", 0x10B7, 0x5950, 0xffff,
245: PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, vortex_probe1},
246: {"3c595 Vortex 100baseT4", 0x10B7, 0x5951, 0xffff,
247: PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, vortex_probe1},
248: {"3c595 Vortex 100base-MII", 0x10B7, 0x5952, 0xffff,
249: PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, vortex_probe1},
250: {"3Com Vortex", 0x10B7, 0x5900, 0xff00,
251: PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG, 64, vortex_probe1},
252: {"3c900 Boomerang 10baseT", 0x10B7, 0x9000, 0xffff,
253: PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG, 64, vortex_probe1},
254: {"3c900 Boomerang 10Mbps Combo", 0x10B7, 0x9001, 0xffff,
255: PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG, 64, vortex_probe1},
256: {"3c900 Cyclone 10Mbps Combo", 0x10B7, 0x9005, 0xffff,
257: PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE, 128, vortex_probe1},
258: {"3c900B-FL Cyclone 10base-FL", 0x10B7, 0x900A, 0xffff,
259: PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE, 128, vortex_probe1},
260: {"3c905 Boomerang 100baseTx", 0x10B7, 0x9050, 0xffff,
261: PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII, 64, vortex_probe1},
262: {"3c905 Boomerang 100baseT4", 0x10B7, 0x9051, 0xffff,
263: PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII, 64, vortex_probe1},
264: {"3c905B Cyclone 100baseTx", 0x10B7, 0x9055, 0xffff,
265: PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY, 128, vortex_probe1},
266: {"3c905B-FX Cyclone 100baseFx", 0x10B7, 0x905A, 0xffff,
267: PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE, 128, vortex_probe1},
268: {"3c980 Cyclone", 0x10B7, 0x9800, 0xfff0,
269: PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE, 128, vortex_probe1},
270: {"3c575 Boomerang CardBus", 0x10B7, 0x5057, 0xffff,
271: PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII, 64, vortex_probe1},
272: {"3CCFE575 Cyclone CardBus", 0x10B7, 0x5157, 0xffff,
273: PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS,
274: 128, vortex_probe1},
275: {"3c575 series CardBus (unknown version)", 0x10B7, 0x5057, 0xf0ff,
276: PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII, 64, vortex_probe1},
277: {"3Com Boomerang (unknown version)", 0x10B7, 0x9000, 0xff00,
278: PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG, 64, vortex_probe1},
279: {0,}, /* 0 terminated list. */
280: };
281:
282: /* Operational definitions.
283: These are not used by other compilation units and thus are not
284: exported in a ".h" file.
285:
286: First the windows. There are eight register windows, with the command
287: and status registers available in each.
288: */
289: #define EL3WINDOW(win_num) outw(SelectWindow + (win_num), ioaddr + EL3_CMD)
290: #define EL3_CMD 0x0e
291: #define EL3_STATUS 0x0e
292:
293: /* The top five bits written to EL3_CMD are a command, the lower
294: 11 bits are the parameter, if applicable.
295: Note that 11 parameters bits was fine for ethernet, but the new chip
296: can handle FDDI length frames (~4500 octets) and now parameters count
297: 32-bit 'Dwords' rather than octets. */
298:
299: enum vortex_cmd {
300: TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
301: RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
302: UpStall = 6<<11, UpUnstall = (6<<11)+1,
303: DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
304: RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
305: FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
306: SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
307: SetTxThreshold = 18<<11, SetTxStart = 19<<11,
308: StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
309: StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
310:
311: /* The SetRxFilter command accepts the following classes: */
312: enum RxFilter {
313: RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
314:
315: /* Bits in the general status register. */
316: enum vortex_status {
317: IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
318: TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
319: IntReq = 0x0040, StatsFull = 0x0080,
320: DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
321: DMAInProgress = 1<<11, /* DMA controller is still busy.*/
322: CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
323: };
324:
325: /* Register window 1 offsets, the window used in normal operation.
326: On the Vortex this window is always mapped at offsets 0x10-0x1f. */
327: enum Window1 {
328: TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
329: RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
330: TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
331: };
332: enum Window0 {
333: Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
334: Wn0EepromData = 12, /* Window 0: EEPROM results register. */
335: IntrStatus=0x0E, /* Valid in all windows. */
336: };
337: enum Win0_EEPROM_bits {
338: EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
339: EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
340: EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
341: };
342: /* EEPROM locations. */
343: enum eeprom_offset {
344: PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
345: EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
346: NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
347: DriverTune=13, Checksum=15};
348:
349: enum Window2 { /* Window 2. */
350: Wn2_ResetOptions=12,
351: };
352: enum Window3 { /* Window 3: MAC/config bits. */
353: Wn3_Config=0, Wn3_MAC_Ctrl=6, Wn3_Options=8,
354: };
355: union wn3_config {
356: int i;
357: struct w3_config_fields {
358: unsigned int ram_size:3, ram_width:1, ram_speed:2, rom_size:2;
359: int pad8:8;
360: unsigned int ram_split:2, pad18:2, xcvr:4, autoselect:1;
361: int pad24:7;
362: } u;
363: };
364:
365: enum Window4 { /* Window 4: Xcvr/media bits. */
366: Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
367: };
368: enum Win4_Media_bits {
369: Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
370: Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
371: Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
372: Media_LnkBeat = 0x0800,
373: };
374: enum Window7 { /* Window 7: Bus Master control. */
375: Wn7_MasterAddr = 0, Wn7_MasterLen = 6, Wn7_MasterStatus = 12,
376: };
377: /* Boomerang bus master control registers. */
378: enum MasterCtrl {
379: PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
380: TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
381: };
382:
383: /* The Rx and Tx descriptor lists.
384: Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
385: alignment contraint on tx_ring[] and rx_ring[]. */
386: #define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
387: struct boom_rx_desc {
388: u32 next; /* Last entry points to 0. */
389: s32 status;
390: u32 addr; /* Up to 63 addr/len pairs possible. */
391: s32 length; /* Set LAST_FRAG to indicate last pair. */
392: };
393: /* Values for the Rx status entry. */
394: enum rx_desc_status {
395: RxDComplete=0x00008000, RxDError=0x4000,
396: /* See boomerang_rx() for actual error bits */
397: IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
398: IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
399: };
400:
401: struct boom_tx_desc {
402: u32 next; /* Last entry points to 0. */
403: s32 status; /* bits 0:12 length, others see below. */
404: u32 addr;
405: s32 length;
406: };
407:
408: /* Values for the Tx status entry. */
409: enum tx_desc_status {
410: CRCDisable=0x2000, TxDComplete=0x8000,
411: AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
412: TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
413: };
414:
415: /* Chip features we care about in vp->capabilities, read from the EEPROM. */
416: enum ChipCaps { CapBusMaster=0x20 };
417:
418: struct vortex_private {
419: /* The Rx and Tx rings should be quad-word-aligned. */
420: struct boom_rx_desc rx_ring[RX_RING_SIZE];
421: struct boom_tx_desc tx_ring[TX_RING_SIZE];
422: /* The addresses of transmit- and receive-in-place skbuffs. */
423: struct sk_buff* rx_skbuff[RX_RING_SIZE];
424: struct sk_buff* tx_skbuff[TX_RING_SIZE];
425: struct device *next_module;
426: void *priv_addr;
427: unsigned int cur_rx, cur_tx; /* The next free ring entry */
428: unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
429: struct net_device_stats stats;
430: struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
431:
432: /* PCI configuration space information. */
433: u8 pci_bus, pci_devfn; /* PCI bus location, for power management. */
434: char *cb_fn_base; /* CardBus function status addr space. */
435: int chip_id;
436:
437: /* The remainder are related to chip state, mostly media selection. */
438: unsigned long in_interrupt;
439: struct timer_list timer; /* Media selection timer. */
440: int options; /* User-settable misc. driver options. */
441: unsigned int media_override:3, /* Passed-in media type. */
442: default_media:4, /* Read from the EEPROM/Wn3_Config. */
443: full_duplex:1, force_fd:1, autoselect:1,
444: bus_master:1, /* Vortex can only do a fragment bus-m. */
445: full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */
446: hw_csums:1, /* Has hardware checksums. */
447: tx_full:1;
448: u16 status_enable;
449: u16 intr_enable;
450: u16 available_media; /* From Wn3_Options. */
451: u16 capabilities, info1, info2; /* Various, from EEPROM. */
452: u16 advertising; /* NWay media advertisement */
453: unsigned char phys[2]; /* MII device addresses. */
454: };
455:
456: /* The action to take with a media selection timer tick.
457: Note that we deviate from the 3Com order by checking 10base2 before AUI.
458: */
459: enum xcvr_types {
460: XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
461: XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
462: };
463:
464: static struct media_table {
465: char *name;
466: unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
467: mask:8, /* The transceiver-present bit in Wn3_Config.*/
468: next:8; /* The media type to try next. */
469: int wait; /* Time before we check media status. */
470: } media_tbl[] = {
471: { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
472: { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
473: { "undefined", 0, 0x80, XCVR_10baseT, 10000},
474: { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
475: { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
476: { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
477: { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
478: { "undefined", 0, 0x01, XCVR_10baseT, 10000},
479: { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
480: { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
481: { "Default", 0, 0xFF, XCVR_10baseT, 10000},
482: };
483:
484: #ifndef CARDBUS
485: static int vortex_scan(struct device *dev, struct pci_id_info pci_tbl[]);
486: #endif
487: static int vortex_open(struct device *dev);
488: static void mdio_sync(long ioaddr, int bits);
489: static int mdio_read(long ioaddr, int phy_id, int location);
490: static void mdio_write(long ioaddr, int phy_id, int location, int value);
491: static void vortex_timer(unsigned long arg);
492: static int vortex_start_xmit(struct sk_buff *skb, struct device *dev);
493: static int boomerang_start_xmit(struct sk_buff *skb, struct device *dev);
494: static int vortex_rx(struct device *dev);
495: static int boomerang_rx(struct device *dev);
496: static void vortex_interrupt(int irq, void *dev_id, struct pt_regs *regs);
497: static int vortex_close(struct device *dev);
498: static void update_stats(long ioaddr, struct device *dev);
499: static struct net_device_stats *vortex_get_stats(struct device *dev);
500: static void set_rx_mode(struct device *dev);
501: static int vortex_ioctl(struct device *dev, struct ifreq *rq, int cmd);
502:
503:
504: /* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
505: /* Option count limit only -- unlimited interfaces are supported. */
506: #define MAX_UNITS 8
507: static int options[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1,};
508: static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
509: /* A list of all installed Vortex devices, for removing the driver module. */
510: static struct device *root_vortex_dev = NULL;
511:
512: #ifdef MODULE
513: #ifndef CARDBUS
514: /* Variables to work-around the Compaq PCI BIOS32 problem. */
515: static int compaq_ioaddr = 0, compaq_irq = 0, compaq_device_id = 0x5900;
516: #endif
517:
518: #ifdef CARDBUS
519:
520: #include <pcmcia/driver_ops.h>
521:
522: static dev_node_t *vortex_attach(dev_locator_t *loc)
523: {
524: u16 dev_id, vendor_id;
525: u32 io;
526: u8 bus, devfn, irq;
527: struct device *dev;
528: int chip_idx;
529:
530: if (loc->bus != LOC_PCI) return NULL;
531: bus = loc->b.pci.bus; devfn = loc->b.pci.devfn;
532: pcibios_read_config_dword(bus, devfn, PCI_BASE_ADDRESS_0, &io);
533: pcibios_read_config_byte(bus, devfn, PCI_INTERRUPT_LINE, &irq);
534: pcibios_read_config_word(bus, devfn, PCI_VENDOR_ID, &vendor_id);
535: pcibios_read_config_word(bus, devfn, PCI_DEVICE_ID, &dev_id);
536: printk(KERN_INFO "vortex_attach(bus %d, function %d, device %4.4x)\n",
537: bus, devfn, dev_id);
538: io &= ~3;
539: if (io == 0 || irq == 0) {
540: printk(KERN_ERR "The 3Com CardBus Ethernet interface was not "
541: "assigned an %s.\n" KERN_ERR " It will not be activated.\n",
542: io == 0 ? "I/O address" : "IRQ");
543: return NULL;
544: }
545: for (chip_idx = 0; pci_tbl[chip_idx].vendor_id; chip_idx++)
546: if (vendor_id == pci_tbl[chip_idx].vendor_id
547: && (dev_id & pci_tbl[chip_idx].device_id_mask) ==
548: pci_tbl[chip_idx].device_id)
549: break;
550: if (pci_tbl[chip_idx].vendor_id == 0) { /* Compiled out! */
551: printk(KERN_INFO "Unable to match chip type %4.4x %4.4x in "
552: "vortex_attach().\n", vendor_id, dev_id);
553: return NULL;
554: }
555: dev = vortex_probe1(bus, devfn, NULL, io, irq, chip_idx, MAX_UNITS+1);
556: if (dev) {
557: dev_node_t *node = kmalloc(sizeof(dev_node_t), GFP_KERNEL);
558: strcpy(node->dev_name, dev->name);
559: node->major = node->minor = 0;
560: node->next = NULL;
561: MOD_INC_USE_COUNT;
562: return node;
563: }
564: return NULL;
565: }
566:
567: static void vortex_detach(dev_node_t *node)
568: {
569: struct device **devp, **next;
570: printk(KERN_INFO "vortex_detach(%s)\n", node->dev_name);
571: for (devp = &root_vortex_dev; *devp; devp = next) {
572: next = &((struct vortex_private *)(*devp)->priv)->next_module;
573: if (strcmp((*devp)->name, node->dev_name) == 0) break;
574: }
575: if (*devp) {
576: struct device *dev = *devp;
577: struct vortex_private *vp = dev->priv;
578: if (dev->flags & IFF_UP)
579: vortex_close(dev);
580: dev->flags &= ~(IFF_UP|IFF_RUNNING);
581: unregister_netdev(dev);
582: if (vp->cb_fn_base) iounmap(vp->cb_fn_base);
583: kfree(dev);
584: *devp = *next;
585: kfree(vp);
586: kfree(node);
587: MOD_DEC_USE_COUNT;
588: }
589: }
590:
591: struct driver_operations vortex_ops = {
592: "3c575_cb", vortex_attach, NULL, NULL, vortex_detach
593: };
594:
595: #endif /* Cardbus support */
596:
597:
598: int init_module(void)
599: {
600: if (vortex_debug)
601: printk(KERN_INFO "%s", version);
602: #ifdef CARDBUS
603: register_driver(&vortex_ops);
604: return 0;
605: #else
606: return vortex_scan(0, pci_tbl);
607: #endif
608: }
609:
610: #else
611: int tc59x_probe(struct device *dev)
612: {
613: static int scanned=0;
614: if(scanned++)
615: return -ENODEV;
616: printk(KERN_INFO "%s", version);
617: return vortex_scan(dev, pci_tbl);
618: }
619: #endif /* not MODULE */
620:
621: #ifndef CARDBUS
622: static int vortex_scan(struct device *dev, struct pci_id_info pci_tbl[])
623: {
624: int cards_found = 0;
625:
626: /* Allow an EISA-only driver. */
627: #if defined(CONFIG_PCI) || (defined(MODULE) && !defined(NO_PCI))
628: /* Ideally we would detect all cards in slot order. That would
629: be best done a central PCI probe dispatch, which wouldn't work
630: well with the current structure. So instead we detect 3Com cards
631: in slot order. */
632: if (pcibios_present()) {
633: static int pci_index = 0;
634: unsigned char pci_bus, pci_device_fn;
635:
636: for (;pci_index < 0xff; pci_index++) {
637: u16 vendor, device, pci_command, new_command, pwr_cmd;
638: int chip_idx, irq;
639: long ioaddr;
640:
641: if (pcibios_find_class (PCI_CLASS_NETWORK_ETHERNET << 8, pci_index,
642: &pci_bus, &pci_device_fn)
643: != PCIBIOS_SUCCESSFUL)
644: break;
645: pcibios_read_config_word(pci_bus, pci_device_fn,
646: PCI_VENDOR_ID, &vendor);
647: pcibios_read_config_word(pci_bus, pci_device_fn,
648: PCI_DEVICE_ID, &device);
649: for (chip_idx = 0; pci_tbl[chip_idx].vendor_id; chip_idx++)
650: if (vendor == pci_tbl[chip_idx].vendor_id
651: && (device & pci_tbl[chip_idx].device_id_mask) ==
652: pci_tbl[chip_idx].device_id)
653: break;
654: if (pci_tbl[chip_idx].vendor_id == 0) /* Compiled out! */
655: continue;
656:
657: {
658: #if LINUX_VERSION_CODE >= 0x20155
659: struct pci_dev *pdev = pci_find_slot(pci_bus, pci_device_fn);
660: ioaddr = pdev->base_address[0] & ~3;
661: irq = pdev->irq;
662: #else
663: u32 pci_ioaddr;
664: u8 pci_irq_line;
665: pcibios_read_config_byte(pci_bus, pci_device_fn,
666: PCI_INTERRUPT_LINE, &pci_irq_line);
667: pcibios_read_config_dword(pci_bus, pci_device_fn,
668: PCI_BASE_ADDRESS_0, &pci_ioaddr);
669: ioaddr = pci_ioaddr & ~3;;
670: irq = pci_irq_line;
671: #endif
672: }
673:
674: /* Power-up the card. */
675: pcibios_read_config_word(pci_bus, pci_device_fn,
676: 0xe0, &pwr_cmd);
677: if (pwr_cmd & 0x3) {
678: /* Save the ioaddr and IRQ info! */
679: printk(KERN_INFO " A 3Com network adapter is powered down!"
680: " Setting the power state %4.4x->%4.4x.\n",
681: pwr_cmd, pwr_cmd & ~3);
682: pcibios_write_config_word(pci_bus, pci_device_fn,
683: 0xe0, pwr_cmd & ~3);
684: printk(KERN_INFO " Setting the IRQ to %d, IOADDR to %#lx.\n",
685: irq, ioaddr);
686: pcibios_write_config_byte(pci_bus, pci_device_fn,
687: PCI_INTERRUPT_LINE, irq);
688: pcibios_write_config_dword(pci_bus, pci_device_fn,
689: PCI_BASE_ADDRESS_0, ioaddr);
690: }
691:
692: if (ioaddr == 0) {
693: printk(KERN_WARNING " A 3Com network adapter has been found, "
694: "however it has not been assigned an I/O address.\n"
695: " You may need to power-cycle the machine for this "
696: "device to work!\n");
697: continue;
698: }
699:
700: if (check_region(ioaddr, pci_tbl[chip_idx].io_size))
701: continue;
702:
703: /* Activate the card. */
704: pcibios_read_config_word(pci_bus, pci_device_fn,
705: PCI_COMMAND, &pci_command);
706: new_command = pci_command | PCI_COMMAND_MASTER|PCI_COMMAND_IO;
707: if (pci_command != new_command) {
708: printk(KERN_INFO " The PCI BIOS has not enabled the device "
709: "at %d/%d. Updating PCI command %4.4x->%4.4x.\n",
710: pci_bus, pci_device_fn, pci_command, new_command);
711: pcibios_write_config_word(pci_bus, pci_device_fn,
712: PCI_COMMAND, new_command);
713: }
714:
715: dev = vortex_probe1(pci_bus, pci_device_fn, dev, ioaddr, irq,
716: chip_idx, cards_found);
717:
718: if (dev) {
719: /* Get and check the latency values. On the 3c590 series
720: the latency timer must be set to the maximum value to avoid
721: data corruption that occurs when the timer expires during
722: a transfer -- a bug in the Vortex chip only. */
723: u8 pci_latency;
724: u8 new_latency = (device & 0xff00) == 0x5900 ? 248 : 32;
725:
726: pcibios_read_config_byte(pci_bus, pci_device_fn,
727: PCI_LATENCY_TIMER, &pci_latency);
728: if (pci_latency < new_latency) {
729: printk(KERN_INFO "%s: Overriding PCI latency"
730: " timer (CFLT) setting of %d, new value is %d.\n",
731: dev->name, pci_latency, new_latency);
732: pcibios_write_config_byte(pci_bus, pci_device_fn,
733: PCI_LATENCY_TIMER, new_latency);
734: }
735: dev = 0;
736: cards_found++;
737: }
738: }
739: }
740: #endif /* NO_PCI */
741:
742: /* Now check all slots of the EISA bus. */
743: if (EISA_bus) {
744: static long ioaddr = 0x1000;
745: for ( ; ioaddr < 0x9000; ioaddr += 0x1000) {
746: int device_id;
747: if (check_region(ioaddr, VORTEX_TOTAL_SIZE))
748: continue;
749: /* Check the standard EISA ID register for an encoded '3Com'. */
750: if (inw(ioaddr + 0xC80) != 0x6d50)
751: continue;
752: /* Check for a product that we support, 3c59{2,7} any rev. */
753: device_id = (inb(ioaddr + 0xC82)<<8) + inb(ioaddr + 0xC83);
754: if ((device_id & 0xFF00) != 0x5900)
755: continue;
756: vortex_probe1(0, 0, dev, ioaddr, inw(ioaddr + 0xC88) >> 12,
757: 4, cards_found);
758: dev = 0;
759: cards_found++;
760: }
761: }
762:
763: #ifdef MODULE
764: /* Special code to work-around the Compaq PCI BIOS32 problem. */
765: if (compaq_ioaddr) {
766: vortex_probe1(0, 0, dev, compaq_ioaddr, compaq_irq,
767: compaq_device_id, cards_found++);
768: dev = 0;
769: }
770: #endif
771:
772: return cards_found ? 0 : -ENODEV;
773: }
774: #endif /* ! Cardbus */
775:
776: static struct device *vortex_probe1(int pci_bus, int pci_devfn,
777: struct device *dev, long ioaddr,
778: int irq, int chip_idx, int card_idx)
779: {
780: struct vortex_private *vp;
781: int option;
782: unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
783: int i;
784:
785: dev = init_etherdev(dev, 0);
786:
787: printk(KERN_INFO "%s: 3Com %s at 0x%lx, ",
788: dev->name, pci_tbl[chip_idx].name, ioaddr);
789:
790: dev->base_addr = ioaddr;
791: dev->irq = irq;
792: dev->mtu = mtu;
793:
794: /* Make certain the descriptor lists are aligned. */
795: {
796: void *mem = kmalloc(sizeof(*vp) + 15, GFP_KERNEL);
797: vp = (void *)(((long)mem + 15) & ~15);
798: vp->priv_addr = mem;
799: }
800: memset(vp, 0, sizeof(*vp));
801: dev->priv = vp;
802:
803: vp->next_module = root_vortex_dev;
804: root_vortex_dev = dev;
805:
806: vp->chip_id = chip_idx;
807: vp->pci_bus = pci_bus;
808: vp->pci_devfn = pci_devfn;
809:
810: /* The lower four bits are the media type. */
811: if (dev->mem_start)
812: option = dev->mem_start;
813: else if (card_idx < MAX_UNITS)
814: option = options[card_idx];
815: else
816: option = -1;
817:
818: if (option >= 0) {
819: vp->media_override = ((option & 7) == 2) ? 0 : option & 7;
820: vp->full_duplex = (option & 8) ? 1 : 0;
821: vp->bus_master = (option & 16) ? 1 : 0;
822: } else {
823: vp->media_override = 7;
824: vp->full_duplex = 0;
825: vp->bus_master = 0;
826: }
827: if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0)
828: vp->full_duplex = 1;
829:
830: vp->force_fd = vp->full_duplex;
831: vp->options = option;
832:
833: /* Read the station address from the EEPROM. */
834: EL3WINDOW(0);
835: for (i = 0; i < 0x40; i++) {
836: int timer;
837: #ifdef CARDBUS
838: outw(0x230 + i, ioaddr + Wn0EepromCmd);
839: #else
840: outw(EEPROM_Read + i, ioaddr + Wn0EepromCmd);
841: #endif
842: /* Pause for at least 162 us. for the read to take place. */
843: for (timer = 10; timer >= 0; timer--) {
844: udelay(162);
845: if ((inw(ioaddr + Wn0EepromCmd) & 0x8000) == 0)
846: break;
847: }
848: eeprom[i] = inw(ioaddr + Wn0EepromData);
849: }
850: for (i = 0; i < 0x18; i++)
851: checksum ^= eeprom[i];
852: checksum = (checksum ^ (checksum >> 8)) & 0xff;
853: if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */
854: while (i < 0x21)
855: checksum ^= eeprom[i++];
856: checksum = (checksum ^ (checksum >> 8)) & 0xff;
857: }
858: if (checksum != 0x00)
859: printk(" ***INVALID CHECKSUM %4.4x*** ", checksum);
860:
861: for (i = 0; i < 3; i++)
862: ((u16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
863: for (i = 0; i < 6; i++)
864: printk("%c%2.2x", i ? ':' : ' ', dev->dev_addr[i]);
865: #ifdef __sparc__
866: printk(", IRQ %s\n", __irq_itoa(dev->irq));
867: #else
868: printk(", IRQ %d\n", dev->irq);
869: /* Tell them about an invalid IRQ. */
870: if (vortex_debug && (dev->irq <= 0 || dev->irq >= NR_IRQS))
871: printk(KERN_WARNING " *** Warning: IRQ %d is unlikely to work! ***\n",
872: dev->irq);
873: #endif
874:
875: if (pci_tbl[vp->chip_id].drv_flags & HAS_CB_FNS) {
876: u32 fn_st_addr; /* Cardbus function status space */
877: pcibios_read_config_dword(pci_bus, pci_devfn, PCI_BASE_ADDRESS_2,
878: &fn_st_addr);
879: if (fn_st_addr)
880: vp->cb_fn_base = ioremap(fn_st_addr & ~3, 128);
881: printk("%s: CardBus functions mapped %8.8x->%p (PCMCIA committee"
882: " brain-damage).\n", dev->name, fn_st_addr, vp->cb_fn_base);
883: EL3WINDOW(2);
884: outw(0x10 | inw(ioaddr + Wn2_ResetOptions), ioaddr + Wn2_ResetOptions);
885: }
886:
887: /* Extract our information from the EEPROM data. */
888: vp->info1 = eeprom[13];
889: vp->info2 = eeprom[15];
890: vp->capabilities = eeprom[16];
891:
892: if (vp->info1 & 0x8000)
893: vp->full_duplex = 1;
894:
895: {
896: char *ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
897: union wn3_config config;
898: EL3WINDOW(3);
899: vp->available_media = inw(ioaddr + Wn3_Options);
900: if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
901: vp->available_media = 0x40;
902: config.i = inl(ioaddr + Wn3_Config);
903: if (vortex_debug > 1)
904: printk(KERN_DEBUG " Internal config register is %4.4x, "
905: "transceivers %#x.\n", config.i, inw(ioaddr + Wn3_Options));
906: printk(KERN_INFO " %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
907: 8 << config.u.ram_size,
908: config.u.ram_width ? "word" : "byte",
909: ram_split[config.u.ram_split],
910: config.u.autoselect ? "autoselect/" : "",
911: config.u.xcvr > XCVR_ExtMII ? "<invalid transceiver>" :
912: media_tbl[config.u.xcvr].name);
913: vp->default_media = config.u.xcvr;
914: vp->autoselect = config.u.autoselect;
915: }
916:
917: if (vp->media_override != 7) {
918: printk(KERN_INFO " Media override to transceiver type %d (%s).\n",
919: vp->media_override, media_tbl[vp->media_override].name);
920: dev->if_port = vp->media_override;
921: } else
922: dev->if_port = vp->default_media;
923:
924: if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
925: int phy, phy_idx = 0;
926: EL3WINDOW(4);
927: mii_preamble_required++;
928: mii_preamble_required++;
929: mdio_read(ioaddr, 24, 1);
930: for (phy = 1; phy <= 32 && phy_idx < sizeof(vp->phys); phy++) {
931: int mii_status, phyx = phy & 0x1f;
932: mii_status = mdio_read(ioaddr, phyx, 1);
933: if (mii_status && mii_status != 0xffff) {
934: vp->phys[phy_idx++] = phyx;
935: printk(KERN_INFO " MII transceiver found at address %d,"
936: " status %4x.\n", phyx, mii_status);
937: if ((mii_status & 0x0040) == 0)
938: mii_preamble_required++;
939: }
940: }
941: mii_preamble_required--;
942: if (phy_idx == 0) {
943: printk(KERN_WARNING" ***WARNING*** No MII transceivers found!\n");
944: vp->phys[0] = 24;
945: } else {
946: vp->advertising = mdio_read(ioaddr, vp->phys[0], 4);
947: if (vp->full_duplex) {
948: /* Only advertise the FD media types. */
949: vp->advertising &= ~0x02A0;
950: mdio_write(ioaddr, vp->phys[0], 4, vp->advertising);
951: }
952: }
953: }
954:
955: if (vp->capabilities & CapBusMaster) {
956: vp->full_bus_master_tx = 1;
957: printk(KERN_INFO" Enabling bus-master transmits and %s receives.\n",
958: (vp->info2 & 1) ? "early" : "whole-frame" );
959: vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
960: }
961:
962: /* We do a request_region() to register /proc/ioports info. */
963: request_region(ioaddr, pci_tbl[chip_idx].io_size, dev->name);
964:
965: /* The 3c59x-specific entries in the device structure. */
966: dev->open = &vortex_open;
967: dev->hard_start_xmit = &vortex_start_xmit;
968: dev->stop = &vortex_close;
969: dev->get_stats = &vortex_get_stats;
970: dev->do_ioctl = &vortex_ioctl;
971: dev->set_multicast_list = &set_rx_mode;
972:
973: return dev;
974: }
975:
976:
977: static int
978: vortex_open(struct device *dev)
979: {
980: long ioaddr = dev->base_addr;
981: struct vortex_private *vp = (struct vortex_private *)dev->priv;
982: union wn3_config config;
983: int i;
984:
985: /* Before initializing select the active media port. */
986: EL3WINDOW(3);
987: config.i = inl(ioaddr + Wn3_Config);
988:
989: if (vp->media_override != 7) {
990: if (vortex_debug > 1)
991: printk(KERN_INFO "%s: Media override to transceiver %d (%s).\n",
992: dev->name, vp->media_override,
993: media_tbl[vp->media_override].name);
994: dev->if_port = vp->media_override;
995: } else if (vp->autoselect && pci_tbl[vp->chip_id].drv_flags & HAS_NWAY) {
996: dev->if_port = XCVR_NWAY;
997: } else if (vp->autoselect) {
998: /* Find first available media type, starting with 100baseTx. */
999: dev->if_port = XCVR_100baseTx;
1000: while (! (vp->available_media & media_tbl[dev->if_port].mask))
1001: dev->if_port = media_tbl[dev->if_port].next;
1002: } else
1003: dev->if_port = vp->default_media;
1004:
1005: init_timer(&vp->timer);
1006: vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait);
1007: vp->timer.data = (unsigned long)dev;
1008: vp->timer.function = &vortex_timer; /* timer handler */
1009: add_timer(&vp->timer);
1010:
1011: if (vortex_debug > 1)
1012: printk(KERN_DEBUG "%s: Initial media type %s.\n",
1013: dev->name, media_tbl[dev->if_port].name);
1014:
1015: vp->full_duplex = vp->force_fd;
1016: config.u.xcvr = dev->if_port;
1017: outl(config.i, ioaddr + Wn3_Config);
1018:
1019: if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1020: int mii_reg1, mii_reg5;
1021: EL3WINDOW(4);
1022: /* Read BMSR (reg1) only to clear old status. */
1023: mii_reg1 = mdio_read(ioaddr, vp->phys[0], 1);
1024: mii_reg5 = mdio_read(ioaddr, vp->phys[0], 5);
1025: if (mii_reg5 == 0xffff || mii_reg5 == 0x0000)
1026: ; /* No MII device or no link partner report */
1027: else if ((mii_reg5 & 0x0100) != 0 /* 100baseTx-FD */
1028: || (mii_reg5 & 0x00C0) == 0x0040) /* 10T-FD, but not 100-HD */
1029: vp->full_duplex = 1;
1030: if (vortex_debug > 1)
1031: printk(KERN_INFO "%s: MII #%d status %4.4x, link partner capability %4.4x,"
1032: " setting %s-duplex.\n", dev->name, vp->phys[0],
1033: mii_reg1, mii_reg5, vp->full_duplex ? "full" : "half");
1034: EL3WINDOW(3);
1035: }
1036:
1037: /* Set the full-duplex bit. */
1038: outb(((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1039: (dev->mtu > 1500 ? 0x40 : 0), ioaddr + Wn3_MAC_Ctrl);
1040:
1041: if (vortex_debug > 1) {
1042: printk(KERN_DEBUG "%s: vortex_open() InternalConfig %8.8x.\n",
1043: dev->name, config.i);
1044: }
1045:
1046: outw(TxReset, ioaddr + EL3_CMD);
1047: for (i = 2000; i >= 0 ; i--)
1048: if ( ! (inw(ioaddr + EL3_STATUS) & CmdInProgress))
1049: break;
1050:
1051: outw(RxReset, ioaddr + EL3_CMD);
1052: /* Wait a few ticks for the RxReset command to complete. */
1053: for (i = 2000; i >= 0 ; i--)
1054: if ( ! (inw(ioaddr + EL3_STATUS) & CmdInProgress))
1055: break;
1056:
1057: outw(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1058:
1059: /* Use the now-standard shared IRQ implementation. */
1060: if (request_irq(dev->irq, &vortex_interrupt, SA_SHIRQ, dev->name, dev)) {
1061: return -EAGAIN;
1062: }
1063:
1064: if (vortex_debug > 1) {
1065: EL3WINDOW(4);
1066: printk(KERN_DEBUG "%s: vortex_open() irq %d media status %4.4x.\n",
1067: dev->name, dev->irq, inw(ioaddr + Wn4_Media));
1068: }
1069:
1070: /* Set the station address and mask in window 2 each time opened. */
1071: EL3WINDOW(2);
1072: for (i = 0; i < 6; i++)
1073: outb(dev->dev_addr[i], ioaddr + i);
1074: for (; i < 12; i+=2)
1075: outw(0, ioaddr + i);
1076:
1077: if (dev->if_port == XCVR_10base2)
1078: /* Start the thinnet transceiver. We should really wait 50ms...*/
1079: outw(StartCoax, ioaddr + EL3_CMD);
1080: if (dev->if_port != XCVR_NWAY) {
1081: EL3WINDOW(4);
1082: outw((inw(ioaddr + Wn4_Media) & ~(Media_10TP|Media_SQE)) |
1083: media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1084: }
1085:
1086: /* Switch to the stats window, and clear all stats by reading. */
1087: outw(StatsDisable, ioaddr + EL3_CMD);
1088: EL3WINDOW(6);
1089: for (i = 0; i < 10; i++)
1090: inb(ioaddr + i);
1091: inw(ioaddr + 10);
1092: inw(ioaddr + 12);
1093: /* New: On the Vortex we must also clear the BadSSD counter. */
1094: EL3WINDOW(4);
1095: inb(ioaddr + 12);
1096: /* ..and on the Boomerang we enable the extra statistics bits. */
1097: outw(0x0040, ioaddr + Wn4_NetDiag);
1098:
1099: /* Switch to register set 7 for normal use. */
1100: EL3WINDOW(7);
1101:
1102: if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1103: vp->cur_rx = vp->dirty_rx = 0;
1104: /* Initialize the RxEarly register as recommended. */
1105: outw(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1106: outl(0x0020, ioaddr + PktStatus);
1107: if (vortex_debug > 2)
1108: printk(KERN_DEBUG "%s: Filling in the Rx ring.\n", dev->name);
1109: for (i = 0; i < RX_RING_SIZE; i++) {
1110: struct sk_buff *skb;
1111: vp->rx_ring[i].next = cpu_to_le32(virt_to_bus(&vp->rx_ring[i+1]));
1112: vp->rx_ring[i].status = 0; /* Clear complete bit. */
1113: vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
1114: skb = dev_alloc_skb(PKT_BUF_SZ);
1115: vp->rx_skbuff[i] = skb;
1116: if (skb == NULL)
1117: break; /* Bad news! */
1118: skb->dev = dev; /* Mark as being used by this device. */
1119: #if LINUX_VERSION_CODE >= 0x10300
1120: skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1121: vp->rx_ring[i].addr = cpu_to_le32(virt_to_bus(skb->tail));
1122: #else
1123: vp->rx_ring[i].addr = virt_to_bus(skb->data);
1124: #endif
1125: }
1126: /* Wrap the ring. */
1127: vp->rx_ring[i-1].next = cpu_to_le32(virt_to_bus(&vp->rx_ring[0]));
1128: outl(virt_to_bus(&vp->rx_ring[0]), ioaddr + UpListPtr);
1129: }
1130: if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
1131: dev->hard_start_xmit = &boomerang_start_xmit;
1132: vp->cur_tx = vp->dirty_tx = 0;
1133: outb(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
1134: /* Clear the Tx ring. */
1135: for (i = 0; i < TX_RING_SIZE; i++)
1136: vp->tx_skbuff[i] = 0;
1137: outl(0, ioaddr + DownListPtr);
1138: }
1139: /* Set reciever mode: presumably accept b-case and phys addr only. */
1140: set_rx_mode(dev);
1141: outw(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1142:
1143: vp->in_interrupt = 0;
1144: dev->tbusy = 0;
1145: dev->interrupt = 0;
1146: dev->start = 1;
1147:
1148: outw(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1149: outw(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1150: /* Allow status bits to be seen. */
1151: vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1152: (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1153: (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1154: (vp->bus_master ? DMADone : 0);
1155: vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable | RxComplete |
1156: StatsFull | HostError | TxComplete | IntReq
1157: | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
1158: outw(vp->status_enable, ioaddr + EL3_CMD);
1159: /* Ack all pending events, and set active indicator mask. */
1160: outw(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1161: ioaddr + EL3_CMD);
1162: outw(vp->intr_enable, ioaddr + EL3_CMD);
1163: if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
1164: writel(0x8000, vp->cb_fn_base + 4);
1165:
1166: MOD_INC_USE_COUNT;
1167:
1168: return 0;
1169: }
1170:
1171: static void vortex_timer(unsigned long data)
1172: {
1173: struct device *dev = (struct device *)data;
1174: struct vortex_private *vp = (struct vortex_private *)dev->priv;
1175: long ioaddr = dev->base_addr;
1176: int next_tick = 0;
1177: int ok = 0;
1178: int media_status, mii_status, old_window;
1179:
1180: if (vortex_debug > 1)
1181: printk(KERN_DEBUG "%s: Media selection timer tick happened, %s.\n",
1182: dev->name, media_tbl[dev->if_port].name);
1183:
1184: disable_irq(dev->irq);
1185: old_window = inw(ioaddr + EL3_CMD) >> 13;
1186: EL3WINDOW(4);
1187: media_status = inw(ioaddr + Wn4_Media);
1188: switch (dev->if_port) {
1189: case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1190: if (media_status & Media_LnkBeat) {
1191: ok = 1;
1192: if (vortex_debug > 1)
1193: printk(KERN_DEBUG "%s: Media %s has link beat, %x.\n",
1194: dev->name, media_tbl[dev->if_port].name, media_status);
1195: } else if (vortex_debug > 1)
1196: printk(KERN_DEBUG "%s: Media %s is has no link beat, %x.\n",
1197: dev->name, media_tbl[dev->if_port].name, media_status);
1198: break;
1199: case XCVR_MII: case XCVR_NWAY:
1200: mii_status = mdio_read(ioaddr, vp->phys[0], 1);
1201: ok = 1;
1202: if (debug > 1)
1203: printk(KERN_DEBUG "%s: MII transceiver has status %4.4x.\n",
1204: dev->name, mii_status);
1205: if (mii_status & 0x0004) {
1206: int mii_reg5 = mdio_read(ioaddr, vp->phys[0], 5);
1207: if (! vp->force_fd && mii_reg5 != 0xffff) {
1208: int duplex = (mii_reg5&0x0100) ||
1209: (mii_reg5 & 0x01C0) == 0x0040;
1210: if (vp->full_duplex != duplex) {
1211: vp->full_duplex = duplex;
1212: printk(KERN_INFO "%s: Setting %s-duplex based on MII "
1213: "#%d link partner capability of %4.4x.\n",
1214: dev->name, vp->full_duplex ? "full" : "half",
1215: vp->phys[0], mii_reg5);
1216: /* Set the full-duplex bit. */
1217: outb((vp->full_duplex ? 0x20 : 0) |
1218: (dev->mtu > 1500 ? 0x40 : 0),
1219: ioaddr + Wn3_MAC_Ctrl);
1220: }
1221: next_tick = 60*HZ;
1222: }
1223: }
1224: break;
1225: default: /* Other media types handled by Tx timeouts. */
1226: if (vortex_debug > 1)
1227: printk(KERN_DEBUG "%s: Media %s is has no indication, %x.\n",
1228: dev->name, media_tbl[dev->if_port].name, media_status);
1229: ok = 1;
1230: }
1231: if ( ! ok) {
1232: union wn3_config config;
1233:
1234: do {
1235: dev->if_port = media_tbl[dev->if_port].next;
1236: } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1237: if (dev->if_port == XCVR_Default) { /* Go back to default. */
1238: dev->if_port = vp->default_media;
1239: if (vortex_debug > 1)
1240: printk(KERN_DEBUG "%s: Media selection failing, using default "
1241: "%s port.\n",
1242: dev->name, media_tbl[dev->if_port].name);
1243: } else {
1244: if (vortex_debug > 1)
1245: printk(KERN_DEBUG "%s: Media selection failed, now trying "
1246: "%s port.\n",
1247: dev->name, media_tbl[dev->if_port].name);
1248: next_tick = media_tbl[dev->if_port].wait;
1249: }
1250: outw((media_status & ~(Media_10TP|Media_SQE)) |
1251: media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1252:
1253: EL3WINDOW(3);
1254: config.i = inl(ioaddr + Wn3_Config);
1255: config.u.xcvr = dev->if_port;
1256: outl(config.i, ioaddr + Wn3_Config);
1257:
1258: outw(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1259: ioaddr + EL3_CMD);
1260: }
1261: EL3WINDOW(old_window);
1262: enable_irq(dev->irq);
1263:
1264: if (vortex_debug > 2)
1265: printk(KERN_DEBUG "%s: Media selection timer finished, %s.\n",
1266: dev->name, media_tbl[dev->if_port].name);
1267:
1268: if (next_tick) {
1269: vp->timer.expires = RUN_AT(next_tick);
1270: add_timer(&vp->timer);
1271: }
1272: return;
1273: }
1274:
1275: static void vortex_tx_timeout(struct device *dev)
1276: {
1277: struct vortex_private *vp = (struct vortex_private *)dev->priv;
1278: long ioaddr = dev->base_addr;
1279: int j;
1280:
1281: printk(KERN_ERR "%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
1282: dev->name, inb(ioaddr + TxStatus),
1283: inw(ioaddr + EL3_STATUS));
1284: /* Slight code bloat to be user friendly. */
1285: if ((inb(ioaddr + TxStatus) & 0x88) == 0x88)
1286: printk(KERN_ERR "%s: Transmitter encountered 16 collisions --"
1287: " network cable problem?\n", dev->name);
1288: if (inw(ioaddr + EL3_STATUS) & IntLatch) {
1289: printk(KERN_ERR "%s: Interrupt posted but not delivered --"
1290: " IRQ blocked by another device?\n", dev->name);
1291: /* Bad idea here.. but we might as well handle a few events. */
1292: vortex_interrupt(dev->irq, dev, 0);
1293: }
1294: outw(TxReset, ioaddr + EL3_CMD);
1295: for (j = 200; j >= 0 ; j--)
1296: if ( ! (inw(ioaddr + EL3_STATUS) & CmdInProgress))
1297: break;
1298:
1299: #if ! defined(final_version) && LINUX_VERSION_CODE >= 0x10300
1300: if (vp->full_bus_master_tx) {
1301: int i;
1302: printk(KERN_DEBUG " Flags; bus-master %d, full %d; dirty %d "
1303: "current %d.\n",
1304: vp->full_bus_master_tx, vp->tx_full, vp->dirty_tx, vp->cur_tx);
1305: printk(KERN_DEBUG " Transmit list %8.8x vs. %p.\n",
1306: inl(ioaddr + DownListPtr),
1307: &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
1308: for (i = 0; i < TX_RING_SIZE; i++) {
1309: printk(KERN_DEBUG " %d: @%p length %8.8x status %8.8x\n", i,
1310: &vp->tx_ring[i],
1311: le32_to_cpu(vp->tx_ring[i].length),
1312: le32_to_cpu(vp->tx_ring[i].status));
1313: }
1314: }
1315: #endif
1316: vp->stats.tx_errors++;
1317: if (vp->full_bus_master_tx) {
1318: if (vortex_debug > 0)
1319: printk(KERN_DEBUG "%s: Resetting the Tx ring pointer.\n",
1320: dev->name);
1321: if (vp->cur_tx - vp->dirty_tx > 0 && inl(ioaddr + DownListPtr) == 0)
1322: outl(virt_to_bus(&vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]),
1323: ioaddr + DownListPtr);
1324: if (vp->tx_full && (vp->cur_tx - vp->dirty_tx <= TX_RING_SIZE - 1)) {
1325: vp->tx_full = 0;
1326: clear_bit(0, (void*)&dev->tbusy);
1327: }
1328: outb(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
1329: outw(DownUnstall, ioaddr + EL3_CMD);
1330: } else
1331: vp->stats.tx_dropped++;
1332:
1333: /* Issue Tx Enable */
1334: outw(TxEnable, ioaddr + EL3_CMD);
1335: dev->trans_start = jiffies;
1336:
1337: /* Switch to register set 7 for normal use. */
1338: EL3WINDOW(7);
1339: }
1340:
1341: /*
1342: * Handle uncommon interrupt sources. This is a separate routine to minimize
1343: * the cache impact.
1344: */
1345: static void
1346: vortex_error(struct device *dev, int status)
1347: {
1348: struct vortex_private *vp = (struct vortex_private *)dev->priv;
1349: long ioaddr = dev->base_addr;
1350: int do_tx_reset = 0;
1351: int i;
1352:
1353: if (status & TxComplete) { /* Really "TxError" for us. */
1354: unsigned char tx_status = inb(ioaddr + TxStatus);
1355: /* Presumably a tx-timeout. We must merely re-enable. */
1356: if (vortex_debug > 2
1357: || (tx_status != 0x88 && vortex_debug > 0))
1358: printk(KERN_DEBUG"%s: Transmit error, Tx status register %2.2x.\n",
1359: dev->name, tx_status);
1360: if (tx_status & 0x14) vp->stats.tx_fifo_errors++;
1361: if (tx_status & 0x38) vp->stats.tx_aborted_errors++;
1362: outb(0, ioaddr + TxStatus);
1363: if (tx_status & 0x30)
1364: do_tx_reset = 1;
1365: else /* Merely re-enable the transmitter. */
1366: outw(TxEnable, ioaddr + EL3_CMD);
1367: }
1368: if (status & RxEarly) { /* Rx early is unused. */
1369: vortex_rx(dev);
1370: outw(AckIntr | RxEarly, ioaddr + EL3_CMD);
1371: }
1372: if (status & StatsFull) { /* Empty statistics. */
1373: static int DoneDidThat = 0;
1374: if (vortex_debug > 4)
1375: printk(KERN_DEBUG "%s: Updating stats.\n", dev->name);
1376: update_stats(ioaddr, dev);
1377: /* HACK: Disable statistics as an interrupt source. */
1378: /* This occurs when we have the wrong media type! */
1379: if (DoneDidThat == 0 &&
1380: inw(ioaddr + EL3_STATUS) & StatsFull) {
1381: printk(KERN_WARNING "%s: Updating statistics failed, disabling "
1382: "stats as an interrupt source.\n", dev->name);
1383: EL3WINDOW(5);
1384: outw(SetIntrEnb | (inw(ioaddr + 10) & ~StatsFull), ioaddr + EL3_CMD);
1385: EL3WINDOW(7);
1386: DoneDidThat++;
1387: }
1388: }
1389: if (status & IntReq) { /* Restore all interrupt sources. */
1390: outw(vp->status_enable, ioaddr + EL3_CMD);
1391: outw(vp->intr_enable, ioaddr + EL3_CMD);
1392: }
1393: if (status & HostError) {
1394: u16 fifo_diag;
1395: EL3WINDOW(4);
1396: fifo_diag = inw(ioaddr + Wn4_FIFODiag);
1397: if (vortex_debug > 0)
1398: printk(KERN_ERR "%s: Host error, FIFO diagnostic register %4.4x.\n",
1399: dev->name, fifo_diag);
1400: /* Adapter failure requires Tx/Rx reset and reinit. */
1401: if (vp->full_bus_master_tx) {
1402: outw(TotalReset | 0xff, ioaddr + EL3_CMD);
1403: for (i = 2000; i >= 0 ; i--)
1404: if ( ! (inw(ioaddr + EL3_STATUS) & CmdInProgress))
1405: break;
1406: /* Re-enable the receiver. */
1407: outw(RxEnable, ioaddr + EL3_CMD);
1408: outw(TxEnable, ioaddr + EL3_CMD);
1409: } else if (fifo_diag & 0x0400)
1410: do_tx_reset = 1;
1411: if (fifo_diag & 0x3000) {
1412: outw(RxReset, ioaddr + EL3_CMD);
1413: for (i = 2000; i >= 0 ; i--)
1414: if ( ! (inw(ioaddr + EL3_STATUS) & CmdInProgress))
1415: break;
1416: /* Set the Rx filter to the current state. */
1417: set_rx_mode(dev);
1418: outw(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
1419: outw(AckIntr | HostError, ioaddr + EL3_CMD);
1420: }
1421: }
1422: if (do_tx_reset) {
1423: int j;
1424: outw(TxReset, ioaddr + EL3_CMD);
1425: for (j = 200; j >= 0 ; j--)
1426: if ( ! (inw(ioaddr + EL3_STATUS) & CmdInProgress))
1427: break;
1428: outw(TxEnable, ioaddr + EL3_CMD);
1429: }
1430:
1431: }
1432:
1433:
1434: static int
1435: vortex_start_xmit(struct sk_buff *skb, struct device *dev)
1436: {
1437: struct vortex_private *vp = (struct vortex_private *)dev->priv;
1438: long ioaddr = dev->base_addr;
1439:
1440: if (test_and_set_bit(0, (void*)&dev->tbusy) != 0) {
1441: if (jiffies - dev->trans_start >= TX_TIMEOUT)
1442: vortex_tx_timeout(dev);
1443: return 1;
1444: }
1445:
1446: /* Put out the doubleword header... */
1447: outl(skb->len, ioaddr + TX_FIFO);
1448: if (vp->bus_master) {
1449: /* Set the bus-master controller to transfer the packet. */
1450: outl(virt_to_bus(skb->data), ioaddr + Wn7_MasterAddr);
1451: outw((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
1452: vp->tx_skb = skb;
1453: outw(StartDMADown, ioaddr + EL3_CMD);
1454: /* dev->tbusy will be cleared at the DMADone interrupt. */
1455: } else {
1456: /* ... and the packet rounded to a doubleword. */
1457: outsl(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
1458: DEV_FREE_SKB(skb);
1459: if (inw(ioaddr + TxFree) > 1536) {
1460: clear_bit(0, (void*)&dev->tbusy);
1461: } else
1462: /* Interrupt us when the FIFO has room for max-sized packet. */
1463: outw(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
1464: }
1465:
1466: dev->trans_start = jiffies;
1467:
1468: /* Clear the Tx status stack. */
1469: {
1470: int tx_status;
1471: int i = 32;
1472:
1473: while (--i > 0 && (tx_status = inb(ioaddr + TxStatus)) > 0) {
1474: if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
1475: if (vortex_debug > 2)
1476: printk(KERN_DEBUG "%s: Tx error, status %2.2x.\n",
1477: dev->name, tx_status);
1478: if (tx_status & 0x04) vp->stats.tx_fifo_errors++;
1479: if (tx_status & 0x38) vp->stats.tx_aborted_errors++;
1480: if (tx_status & 0x30) {
1481: int j;
1482: outw(TxReset, ioaddr + EL3_CMD);
1483: for (j = 200; j >= 0 ; j--)
1484: if ( ! (inw(ioaddr + EL3_STATUS) & CmdInProgress))
1485: break;
1486: }
1487: outw(TxEnable, ioaddr + EL3_CMD);
1488: }
1489: outb(0x00, ioaddr + TxStatus); /* Pop the status stack. */
1490: }
1491: }
1492: /* vp->stats.tx_bytes += skb->len; */
1493: return 0;
1494: }
1495:
1496: static int
1497: boomerang_start_xmit(struct sk_buff *skb, struct device *dev)
1498: {
1499: struct vortex_private *vp = (struct vortex_private *)dev->priv;
1500: long ioaddr = dev->base_addr;
1501:
1502: if (test_and_set_bit(0, (void*)&dev->tbusy) != 0) {
1503: if (jiffies - dev->trans_start >= TX_TIMEOUT)
1504: vortex_tx_timeout(dev);
1505: return 1;
1506: } else {
1507: /* Calculate the next Tx descriptor entry. */
1508: int entry = vp->cur_tx % TX_RING_SIZE;
1509: struct boom_tx_desc *prev_entry =
1510: &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
1511: unsigned long flags;
1512: int i;
1513:
1514: if (vortex_debug > 3)
1515: printk(KERN_DEBUG "%s: Trying to send a packet, Tx index %d.\n",
1516: dev->name, vp->cur_tx);
1517: if (vp->tx_full) {
1518: if (vortex_debug >0)
1519: printk(KERN_WARNING "%s: Tx Ring full, refusing to send buffer.\n",
1520: dev->name);
1521: return 1;
1522: }
1523: vp->tx_skbuff[entry] = skb;
1524: vp->tx_ring[entry].next = 0;
1525: vp->tx_ring[entry].addr = cpu_to_le32(virt_to_bus(skb->data));
1526: vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
1527: vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
1528:
1529: save_flags(flags);
1530: cli();
1531: outw(DownStall, ioaddr + EL3_CMD);
1532: /* Wait for the stall to complete. */
1533: for (i = 600; i >= 0 ; i--)
1534: if ( (inw(ioaddr + EL3_STATUS) & CmdInProgress) == 0)
1535: break;
1536: prev_entry->next = cpu_to_le32(virt_to_bus(&vp->tx_ring[entry]));
1537: if (inl(ioaddr + DownListPtr) == 0) {
1538: outl(virt_to_bus(&vp->tx_ring[entry]), ioaddr + DownListPtr);
1539: queued_packet++;
1540: }
1541: outw(DownUnstall, ioaddr + EL3_CMD);
1542: restore_flags(flags);
1543:
1544: vp->cur_tx++;
1545: if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1)
1546: vp->tx_full = 1;
1547: else { /* Clear previous interrupt enable. */
1548: prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
1549: clear_bit(0, (void*)&dev->tbusy);
1550: }
1551: dev->trans_start = jiffies;
1552: /* vp->stats.tx_bytes += skb->len; */
1553: return 0;
1554: }
1555: }
1556:
1557: /* The interrupt handler does all of the Rx thread work and cleans up
1558: after the Tx thread. */
1559: static void vortex_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1560: {
1561: struct device *dev = dev_id;
1562: struct vortex_private *vp = (struct vortex_private *)dev->priv;
1563: long ioaddr;
1564: int latency, status;
1565: int work_done = max_interrupt_work;
1566:
1567: #if defined(__i386__)
1568: /* A lock to prevent simultaneous entry bug on Intel SMP machines. */
1569: if (test_and_set_bit(0, (void*)&dev->interrupt)) {
1570: printk(KERN_ERR"%s: SMP simultaneous entry of an interrupt handler.\n",
1571: dev->name);
1572: dev->interrupt = 0; /* Avoid halting machine. */
1573: return;
1574: }
1575: #else
1576: if (dev->interrupt) {
1577: printk(KERN_ERR "%s: Re-entering the interrupt handler.\n", dev->name);
1578: return;
1579: }
1580: dev->interrupt = 1;
1581: #endif
1582:
1583: dev->interrupt = 1;
1584: ioaddr = dev->base_addr;
1585: latency = inb(ioaddr + Timer);
1586: status = inw(ioaddr + EL3_STATUS);
1587:
1588: if (vortex_debug > 4)
1589: printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
1590: dev->name, status, latency);
1591: do {
1592: if (vortex_debug > 5)
1593: printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
1594: dev->name, status);
1595: if (status & RxComplete)
1596: vortex_rx(dev);
1597: if (status & UpComplete) {
1598: outw(AckIntr | UpComplete, ioaddr + EL3_CMD);
1599: boomerang_rx(dev);
1600: }
1601:
1602: if (status & TxAvailable) {
1603: if (vortex_debug > 5)
1604: printk(KERN_DEBUG " TX room bit was handled.\n");
1605: /* There's room in the FIFO for a full-sized packet. */
1606: outw(AckIntr | TxAvailable, ioaddr + EL3_CMD);
1607: clear_bit(0, (void*)&dev->tbusy);
1608: mark_bh(NET_BH);
1609: }
1610:
1611: if (status & DownComplete) {
1612: unsigned int dirty_tx = vp->dirty_tx;
1613:
1614: while (vp->cur_tx - dirty_tx > 0) {
1615: int entry = dirty_tx % TX_RING_SIZE;
1616: if (inl(ioaddr + DownListPtr) ==
1617: virt_to_bus(&vp->tx_ring[entry]))
1618: break; /* It still hasn't been processed. */
1619: if (vp->tx_skbuff[entry]) {
1620: DEV_FREE_SKB(vp->tx_skbuff[entry]);
1621: vp->tx_skbuff[entry] = 0;
1622: }
1623: /* vp->stats.tx_packets++; Counted below. */
1624: dirty_tx++;
1625: }
1626: vp->dirty_tx = dirty_tx;
1627: outw(AckIntr | DownComplete, ioaddr + EL3_CMD);
1628: if (vp->tx_full && (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1)) {
1629: vp->tx_full= 0;
1630: clear_bit(0, (void*)&dev->tbusy);
1631: mark_bh(NET_BH);
1632: }
1633: }
1634: if (status & DMADone) {
1635: if (inw(ioaddr + Wn7_MasterStatus) & 0x1000) {
1636: outw(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
1637: DEV_FREE_SKB(vp->tx_skb); /* Release the transfered buffer */
1638: if (inw(ioaddr + TxFree) > 1536) {
1639: clear_bit(0, (void*)&dev->tbusy);
1640: mark_bh(NET_BH);
1641: } else /* Interrupt when FIFO has room for max-sized packet. */
1642: outw(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
1643: }
1644: }
1645: /* Check for all uncommon interrupts at once. */
1646: if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
1647: if (status == 0xffff)
1648: break;
1649: vortex_error(dev, status);
1650: }
1651:
1652: if (--work_done < 0) {
1653: if ((status & (0x7fe - (UpComplete | DownComplete))) == 0) {
1654: /* Just ack these and return. */
1655: outw(AckIntr | UpComplete | DownComplete, ioaddr + EL3_CMD);
1656: } else {
1657: printk(KERN_WARNING "%s: Too much work in interrupt, status "
1658: "%4.4x. Temporarily disabling functions (%4.4x).\n",
1659: dev->name, status, SetStatusEnb | ((~status) & 0x7FE));
1660: /* Disable all pending interrupts. */
1661: outw(SetStatusEnb | ((~status) & 0x7FE), ioaddr + EL3_CMD);
1662: outw(AckIntr | 0x7FF, ioaddr + EL3_CMD);
1663: /* The timer will reenable interrupts. */
1664: break;
1665: }
1666: }
1667: /* Acknowledge the IRQ. */
1668: outw(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
1669: if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
1670: writel(0x8000, vp->cb_fn_base + 4);
1671:
1672: } while ((status = inw(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
1673:
1674: if (vortex_debug > 4)
1675: printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
1676: dev->name, status);
1677:
1678: #if defined(__i386__)
1679: clear_bit(0, (void*)&dev->interrupt);
1680: #else
1681: dev->interrupt = 0;
1682: #endif
1683: return;
1684: }
1685:
1686: static int vortex_rx(struct device *dev)
1687: {
1688: struct vortex_private *vp = (struct vortex_private *)dev->priv;
1689: long ioaddr = dev->base_addr;
1690: int i;
1691: short rx_status;
1692:
1693: if (vortex_debug > 5)
1694: printk(KERN_DEBUG" In rx_packet(), status %4.4x, rx_status %4.4x.\n",
1695: inw(ioaddr+EL3_STATUS), inw(ioaddr+RxStatus));
1696: while ((rx_status = inw(ioaddr + RxStatus)) > 0) {
1697: if (rx_status & 0x4000) { /* Error, update stats. */
1698: unsigned char rx_error = inb(ioaddr + RxErrors);
1699: if (vortex_debug > 2)
1700: printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
1701: vp->stats.rx_errors++;
1702: if (rx_error & 0x01) vp->stats.rx_over_errors++;
1703: if (rx_error & 0x02) vp->stats.rx_length_errors++;
1704: if (rx_error & 0x04) vp->stats.rx_frame_errors++;
1705: if (rx_error & 0x08) vp->stats.rx_crc_errors++;
1706: if (rx_error & 0x10) vp->stats.rx_length_errors++;
1707: } else {
1708: /* The packet length: up to 4.5K!. */
1709: int pkt_len = rx_status & 0x1fff;
1710: struct sk_buff *skb;
1711:
1712: skb = dev_alloc_skb(pkt_len + 5);
1713: if (vortex_debug > 4)
1714: printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
1715: pkt_len, rx_status);
1716: if (skb != NULL) {
1717: skb->dev = dev;
1718: skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1719: /* 'skb_put()' points to the start of sk_buff data area. */
1720: if (vp->bus_master &&
1721: ! (inw(ioaddr + Wn7_MasterStatus) & 0x8000)) {
1722: outl(virt_to_bus(skb_put(skb, pkt_len)),
1723: ioaddr + Wn7_MasterAddr);
1724: outw((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
1725: outw(StartDMAUp, ioaddr + EL3_CMD);
1726: while (inw(ioaddr + Wn7_MasterStatus) & 0x8000)
1727: ;
1728: } else {
1729: insl(ioaddr + RX_FIFO, skb_put(skb, pkt_len),
1730: (pkt_len + 3) >> 2);
1731: }
1732: outw(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
1733: skb->protocol = eth_type_trans(skb, dev);
1734: netif_rx(skb);
1735: dev->last_rx = jiffies;
1736: vp->stats.rx_packets++;
1737: /* vp->stats.rx_bytes += skb->len; */
1738: /* Wait a limited time to go to next packet. */
1739: for (i = 200; i >= 0; i--)
1740: if ( ! (inw(ioaddr + EL3_STATUS) & CmdInProgress))
1741: break;
1742: continue;
1743: } else if (vortex_debug)
1744: printk(KERN_NOTICE "%s: No memory to allocate a sk_buff of "
1745: "size %d.\n", dev->name, pkt_len);
1746: }
1747: outw(RxDiscard, ioaddr + EL3_CMD);
1748: vp->stats.rx_dropped++;
1749: /* Wait a limited time to skip this packet. */
1750: for (i = 200; i >= 0; i--)
1751: if ( ! (inw(ioaddr + EL3_STATUS) & CmdInProgress))
1752: break;
1753: }
1754:
1755: return 0;
1756: }
1757:
1758: static int
1759: boomerang_rx(struct device *dev)
1760: {
1761: struct vortex_private *vp = (struct vortex_private *)dev->priv;
1762: int entry = vp->cur_rx % RX_RING_SIZE;
1763: long ioaddr = dev->base_addr;
1764: int rx_status;
1765: int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx;
1766:
1767: if (vortex_debug > 5)
1768: printk(KERN_DEBUG " In boomerang_rx(), status %4.4x, rx_status "
1769: "%4.4x.\n",
1770: inw(ioaddr+EL3_STATUS), inw(ioaddr+RxStatus));
1771: while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
1772: if (--rx_work_limit < 0)
1773: break;
1774: if (rx_status & RxDError) { /* Error, update stats. */
1775: unsigned char rx_error = rx_status >> 16;
1776: if (vortex_debug > 2)
1777: printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
1778: vp->stats.rx_errors++;
1779: if (rx_error & 0x01) vp->stats.rx_over_errors++;
1780: if (rx_error & 0x02) vp->stats.rx_length_errors++;
1781: if (rx_error & 0x04) vp->stats.rx_frame_errors++;
1782: if (rx_error & 0x08) vp->stats.rx_crc_errors++;
1783: if (rx_error & 0x10) vp->stats.rx_length_errors++;
1784: } else {
1785: /* The packet length: up to 4.5K!. */
1786: int pkt_len = rx_status & 0x1fff;
1787: struct sk_buff *skb;
1788:
1789: /* vp->stats.rx_bytes += pkt_len;*/
1790: if (vortex_debug > 4)
1791: printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
1792: pkt_len, rx_status);
1793:
1794: /* Check if the packet is long enough to just accept without
1795: copying to a properly sized skbuff. */
1796: if (pkt_len < rx_copybreak
1797: && (skb = dev_alloc_skb(pkt_len + 2)) != 0) {
1798: skb->dev = dev;
1799: skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1800: /* 'skb_put()' points to the start of sk_buff data area. */
1801: memcpy(skb_put(skb, pkt_len),
1802: bus_to_virt(le32_to_cpu(vp->rx_ring[entry].addr)),
1803: pkt_len);
1804: rx_copy++;
1805: } else {
1806: void *temp;
1807: /* Pass up the skbuff already on the Rx ring. */
1808: skb = vp->rx_skbuff[entry];
1809: vp->rx_skbuff[entry] = NULL;
1810: temp = skb_put(skb, pkt_len);
1811: /* Remove this checking code for final release. */
1812: if (bus_to_virt(le32_to_cpu(vp->rx_ring[entry].addr)) != temp)
1813: printk(KERN_ERR "%s: Warning -- the skbuff addresses do not match"
1814: " in boomerang_rx: %p vs. %p.\n", dev->name,
1815: bus_to_virt(le32_to_cpu(vp->rx_ring[entry].addr)),
1816: temp);
1817: rx_nocopy++;
1818: }
1819: skb->protocol = eth_type_trans(skb, dev);
1820: { /* Use hardware checksum info. */
1821: int csum_bits = rx_status & 0xee000000;
1822: if (csum_bits &&
1823: (csum_bits == (IPChksumValid | TCPChksumValid) ||
1824: csum_bits == (IPChksumValid | UDPChksumValid))) {
1825: skb->ip_summed = CHECKSUM_UNNECESSARY;
1826: rx_csumhits++;
1827: }
1828: }
1829: netif_rx(skb);
1830: dev->last_rx = jiffies;
1831: vp->stats.rx_packets++;
1832: }
1833: entry = (++vp->cur_rx) % RX_RING_SIZE;
1834: }
1835: /* Refill the Rx ring buffers. */
1836: for (; vp->dirty_rx < vp->cur_rx; vp->dirty_rx++) {
1837: struct sk_buff *skb;
1838: entry = vp->dirty_rx % RX_RING_SIZE;
1839: if (vp->rx_skbuff[entry] == NULL) {
1840: skb = dev_alloc_skb(PKT_BUF_SZ);
1841: if (skb == NULL)
1842: break; /* Bad news! */
1843: skb->dev = dev; /* Mark as being used by this device. */
1844: skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1845: vp->rx_ring[entry].addr = cpu_to_le32(virt_to_bus(skb->tail));
1846: vp->rx_skbuff[entry] = skb;
1847: }
1848: vp->rx_ring[entry].status = 0; /* Clear complete bit. */
1849: outw(UpUnstall, ioaddr + EL3_CMD);
1850: }
1851: return 0;
1852: }
1853:
1854: static int
1855: vortex_close(struct device *dev)
1856: {
1857: struct vortex_private *vp = (struct vortex_private *)dev->priv;
1858: long ioaddr = dev->base_addr;
1859: int i;
1860:
1861: dev->start = 0;
1862: dev->tbusy = 1;
1863:
1864: if (vortex_debug > 1) {
1865: printk(KERN_DEBUG"%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
1866: dev->name, inw(ioaddr + EL3_STATUS), inb(ioaddr + TxStatus));
1867: printk(KERN_DEBUG "%s: vortex close stats: rx_nocopy %d rx_copy %d"
1868: " tx_queued %d Rx pre-checksummed %d.\n",
1869: dev->name, rx_nocopy, rx_copy, queued_packet, rx_csumhits);
1870: }
1871:
1872: del_timer(&vp->timer);
1873:
1874: /* Turn off statistics ASAP. We update vp->stats below. */
1875: outw(StatsDisable, ioaddr + EL3_CMD);
1876:
1877: /* Disable the receiver and transmitter. */
1878: outw(RxDisable, ioaddr + EL3_CMD);
1879: outw(TxDisable, ioaddr + EL3_CMD);
1880:
1881: if (dev->if_port == XCVR_10base2)
1882: /* Turn off thinnet power. Green! */
1883: outw(StopCoax, ioaddr + EL3_CMD);
1884:
1885: free_irq(dev->irq, dev);
1886:
1887: outw(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
1888:
1889: update_stats(ioaddr, dev);
1890: if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
1891: outl(0, ioaddr + UpListPtr);
1892: for (i = 0; i < RX_RING_SIZE; i++)
1893: if (vp->rx_skbuff[i]) {
1894: #if LINUX_VERSION_CODE < 0x20100
1895: vp->rx_skbuff[i]->free = 1;
1896: #endif
1897: DEV_FREE_SKB(vp->rx_skbuff[i]);
1898: vp->rx_skbuff[i] = 0;
1899: }
1900: }
1901: if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
1902: outl(0, ioaddr + DownListPtr);
1903: for (i = 0; i < TX_RING_SIZE; i++)
1904: if (vp->tx_skbuff[i]) {
1905: DEV_FREE_SKB(vp->tx_skbuff[i]);
1906: vp->tx_skbuff[i] = 0;
1907: }
1908: }
1909:
1910: MOD_DEC_USE_COUNT;
1911:
1912: return 0;
1913: }
1914:
1915: static struct net_device_stats *vortex_get_stats(struct device *dev)
1916: {
1917: struct vortex_private *vp = (struct vortex_private *)dev->priv;
1918: unsigned long flags;
1919:
1920: if (dev->start) {
1921: save_flags(flags);
1922: cli();
1923: update_stats(dev->base_addr, dev);
1924: restore_flags(flags);
1925: }
1926: return &vp->stats;
1927: }
1928:
1929: /* Update statistics.
1930: Unlike with the EL3 we need not worry about interrupts changing
1931: the window setting from underneath us, but we must still guard
1932: against a race condition with a StatsUpdate interrupt updating the
1933: table. This is done by checking that the ASM (!) code generated uses
1934: atomic updates with '+='.
1935: */
1936: static void update_stats(long ioaddr, struct device *dev)
1937: {
1938: struct vortex_private *vp = (struct vortex_private *)dev->priv;
1939:
1940: /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
1941: /* Switch to the stats window, and read everything. */
1942: EL3WINDOW(6);
1943: vp->stats.tx_carrier_errors += inb(ioaddr + 0);
1944: vp->stats.tx_heartbeat_errors += inb(ioaddr + 1);
1945: /* Multiple collisions. */ inb(ioaddr + 2);
1946: vp->stats.collisions += inb(ioaddr + 3);
1947: vp->stats.tx_window_errors += inb(ioaddr + 4);
1948: vp->stats.rx_fifo_errors += inb(ioaddr + 5);
1949: vp->stats.tx_packets += inb(ioaddr + 6);
1950: vp->stats.tx_packets += (inb(ioaddr + 9)&0x30) << 4;
1951: /* Rx packets */ inb(ioaddr + 7); /* Must read to clear */
1952: /* Tx deferrals */ inb(ioaddr + 8);
1953: /* Don't bother with register 9, an extension of registers 6&7.
1954: If we do use the 6&7 values the atomic update assumption above
1955: is invalid. */
1956: inw(ioaddr + 10); /* Total Rx and Tx octets. */
1957: inw(ioaddr + 12);
1958: /* New: On the Vortex we must also clear the BadSSD counter. */
1959: EL3WINDOW(4);
1960: inb(ioaddr + 12);
1961:
1962: /* We change back to window 7 (not 1) with the Vortex. */
1963: EL3WINDOW(7);
1964: return;
1965: }
1966:
1967: static int vortex_ioctl(struct device *dev, struct ifreq *rq, int cmd)
1968: {
1969: struct vortex_private *vp = (struct vortex_private *)dev->priv;
1970: long ioaddr = dev->base_addr;
1971: u16 *data = (u16 *)&rq->ifr_data;
1972: int phy = vp->phys[0] & 0x1f;
1973:
1974: switch(cmd) {
1975: case SIOCDEVPRIVATE: /* Get the address of the PHY in use. */
1976: data[0] = phy;
1977: case SIOCDEVPRIVATE+1: /* Read the specified MII register. */
1978: EL3WINDOW(4);
1979: data[3] = mdio_read(ioaddr, data[0] & 0x1f, data[1] & 0x1f);
1980: return 0;
1981: case SIOCDEVPRIVATE+2: /* Write the specified MII register */
1982: if (!suser())
1983: return -EPERM;
1984: EL3WINDOW(4);
1985: mdio_write(ioaddr, data[0] & 0x1f, data[1] & 0x1f, data[2]);
1986: return 0;
1987: default:
1988: return -EOPNOTSUPP;
1989: }
1990: }
1991:
1992: /* Pre-Cyclone chips have no documented multicast filter, so the only
1993: multicast setting is to receive all multicast frames. At least
1994: the chip has a very clean way to set the mode, unlike many others. */
1995: static void set_rx_mode(struct device *dev)
1996: {
1997: long ioaddr = dev->base_addr;
1998: int new_mode;
1999:
2000: if (dev->flags & IFF_PROMISC) {
2001: if (vortex_debug > 0)
2002: printk(KERN_NOTICE "%s: Setting promiscuous mode.\n", dev->name);
2003: new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
2004: } else if ((dev->mc_list) || (dev->flags & IFF_ALLMULTI)) {
2005: new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
2006: } else
2007: new_mode = SetRxFilter | RxStation | RxBroadcast;
2008:
2009: outw(new_mode, ioaddr + EL3_CMD);
2010: }
2011:
2012:
2013: /* MII transceiver control section.
2014: Read and write the MII registers using software-generated serial
2015: MDIO protocol. See the MII specifications or DP83840A data sheet
2016: for details. */
2017:
2018: /* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
2019: met by back-to-back PCI I/O cycles, but we insert a delay to avoid
2020: "overclocking" issues. */
2021: #define mdio_delay() inl(mdio_addr)
2022:
2023: #define MDIO_SHIFT_CLK 0x01
2024: #define MDIO_DIR_WRITE 0x04
2025: #define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
2026: #define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
2027: #define MDIO_DATA_READ 0x02
2028: #define MDIO_ENB_IN 0x00
2029:
2030: /* Generate the preamble required for initial synchronization and
2031: a few older transceivers. */
2032: static void mdio_sync(long ioaddr, int bits)
2033: {
2034: long mdio_addr = ioaddr + Wn4_PhysicalMgmt;
2035:
2036: /* Establish sync by sending at least 32 logic ones. */
2037: while (-- bits >= 0) {
2038: outw(MDIO_DATA_WRITE1, mdio_addr);
2039: mdio_delay();
2040: outw(MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
2041: mdio_delay();
2042: }
2043: }
2044:
2045: static int mdio_read(long ioaddr, int phy_id, int location)
2046: {
2047: int i;
2048: int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
2049: unsigned int retval = 0;
2050: long mdio_addr = ioaddr + Wn4_PhysicalMgmt;
2051:
2052: if (mii_preamble_required)
2053: mdio_sync(ioaddr, 32);
2054:
2055: /* Shift the read command bits out. */
2056: for (i = 14; i >= 0; i--) {
2057: int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
2058: outw(dataval, mdio_addr);
2059: mdio_delay();
2060: outw(dataval | MDIO_SHIFT_CLK, mdio_addr);
2061: mdio_delay();
2062: }
2063: /* Read the two transition, 16 data, and wire-idle bits. */
2064: for (i = 19; i > 0; i--) {
2065: outw(MDIO_ENB_IN, mdio_addr);
2066: mdio_delay();
2067: retval = (retval << 1) | ((inw(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
2068: outw(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
2069: mdio_delay();
2070: }
2071: #if 0
2072: return (retval>>1) & 0x1ffff;
2073: #else
2074: return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
2075: #endif
2076: }
2077:
2078: static void mdio_write(long ioaddr, int phy_id, int location, int value)
2079: {
2080: int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
2081: long mdio_addr = ioaddr + Wn4_PhysicalMgmt;
2082: int i;
2083:
2084: if (mii_preamble_required)
2085: mdio_sync(ioaddr, 32);
2086:
2087: /* Shift the command bits out. */
2088: for (i = 31; i >= 0; i--) {
2089: int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
2090: outw(dataval, mdio_addr);
2091: mdio_delay();
2092: outw(dataval | MDIO_SHIFT_CLK, mdio_addr);
2093: mdio_delay();
2094: }
2095: /* Leave the interface idle. */
2096: for (i = 1; i >= 0; i--) {
2097: outw(MDIO_ENB_IN, mdio_addr);
2098: mdio_delay();
2099: outw(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
2100: mdio_delay();
2101: }
2102:
2103: return;
2104: }
2105:
2106:
2107: #ifdef MODULE
2108: void cleanup_module(void)
2109: {
2110: struct device *next_dev;
2111:
2112: #ifdef CARDBUS
2113: unregister_driver(&vortex_ops);
2114: #endif
2115:
2116: /* No need to check MOD_IN_USE, as sys_delete_module() checks. */
2117: while (root_vortex_dev) {
2118: struct vortex_private *vp=(void *)(root_vortex_dev->priv);
2119: next_dev = vp->next_module;
2120: unregister_netdev(root_vortex_dev);
2121: outw(TotalReset, root_vortex_dev->base_addr + EL3_CMD);
2122: release_region(root_vortex_dev->base_addr,
2123: pci_tbl[vp->chip_id].io_size);
2124: kfree(root_vortex_dev);
2125: kfree(vp->priv_addr);
2126: root_vortex_dev = next_dev;
2127: }
2128: }
2129:
2130: #endif /* MODULE */
2131:
2132: /*
2133: * Local variables:
2134: * compile-command: "gcc -DMODULE -D__KERNEL__ -Wall -Wstrict-prototypes -O6 -c 3c59x.c `[ -f /usr/include/linux/modversions.h ] && echo -DMODVERSIONS`"
2135: * SMP-compile-command: "gcc -D__SMP__ -DMODULE -D__KERNEL__ -Wall -Wstrict-prototypes -O6 -c 3c59x.c"
2136: * cardbus-compile-command: "gcc -DCARDBUS -DMODULE -D__KERNEL__ -Wall -Wstrict-prototypes -O6 -c 3c59x.c -o 3c575_cb.o -I/usr/src/pcmcia-cs-3.0.5/include/"
2137: * c-indent-level: 4
2138: * c-basic-offset: 4
2139: * tab-width: 4
2140: * End:
2141: */
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