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1.1 root 1: /* de4x5.c: A DIGITAL DC21x4x DECchip and DE425/DE434/DE435/DE450/DE500
2: ethernet driver for Linux.
3:
4: Copyright 1994, 1995 Digital Equipment Corporation.
5:
6: Testing resources for this driver have been made available
7: in part by NASA Ames Research Center ([email protected]).
8:
9: The author may be reached at [email protected].
10:
11: This program is free software; you can redistribute it and/or modify it
12: under the terms of the GNU General Public License as published by the
13: Free Software Foundation; either version 2 of the License, or (at your
14: option) any later version.
15:
16: THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17: WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18: MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19: NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20: INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21: NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22: USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23: ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24: (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25: THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26:
27: You should have received a copy of the GNU General Public License along
28: with this program; if not, write to the Free Software Foundation, Inc.,
29: 675 Mass Ave, Cambridge, MA 02139, USA.
30:
31: Originally, this driver was written for the Digital Equipment
32: Corporation series of EtherWORKS ethernet cards:
33:
34: DE425 TP/COAX EISA
35: DE434 TP PCI
36: DE435 TP/COAX/AUI PCI
37: DE450 TP/COAX/AUI PCI
38: DE500 10/100 PCI Fasternet
39:
40: but it will now attempt to support all cards which conform to the
41: Digital Semiconductor SROM Specification. The driver currently
42: recognises the following chips:
43:
44: DC21040 (no SROM)
45: DC21041[A]
46: DC21140[A]
47: DC21142
48: DC21143
49:
50: So far the driver is known to work with the following cards:
51:
52: KINGSTON
53: Linksys
54: ZNYX342
55: SMC8432
56: SMC9332 (w/new SROM)
57: ZNYX31[45]
58: ZNYX346 10/100 4 port (can act as a 10/100 bridge!)
59:
60: The driver has been tested on a relatively busy network using the DE425,
61: DE434, DE435 and DE500 cards and benchmarked with 'ttcp': it transferred
62: 16M of data to a DECstation 5000/200 as follows:
63:
64: TCP UDP
65: TX RX TX RX
66: DE425 1030k 997k 1170k 1128k
67: DE434 1063k 995k 1170k 1125k
68: DE435 1063k 995k 1170k 1125k
69: DE500 1063k 998k 1170k 1125k in 10Mb/s mode
70:
71: All values are typical (in kBytes/sec) from a sample of 4 for each
72: measurement. Their error is +/-20k on a quiet (private) network and also
73: depend on what load the CPU has.
74:
75: =========================================================================
76: This driver has been written substantially from scratch, although its
77: inheritance of style and stack interface from 'ewrk3.c' and in turn from
78: Donald Becker's 'lance.c' should be obvious. With the module autoload of
79: every usable DECchip board, I pinched Donald's 'next_module' field to
80: link my modules together.
81:
82: Upto 15 EISA cards can be supported under this driver, limited primarily
83: by the available IRQ lines. I have checked different configurations of
84: multiple depca, EtherWORKS 3 cards and de4x5 cards and have not found a
85: problem yet (provided you have at least depca.c v0.38) ...
86:
87: PCI support has been added to allow the driver to work with the DE434,
88: DE435, DE450 and DE500 cards. The I/O accesses are a bit of a kludge due
89: to the differences in the EISA and PCI CSR address offsets from the base
90: address.
91:
92: The ability to load this driver as a loadable module has been included
93: and used extensively during the driver development (to save those long
94: reboot sequences). Loadable module support under PCI and EISA has been
95: achieved by letting the driver autoprobe as if it were compiled into the
96: kernel. Do make sure you're not sharing interrupts with anything that
97: cannot accommodate interrupt sharing!
98:
99: To utilise this ability, you have to do 8 things:
100:
101: 0) have a copy of the loadable modules code installed on your system.
102: 1) copy de4x5.c from the /linux/drivers/net directory to your favourite
103: temporary directory.
104: 2) for fixed autoprobes (not recommended), edit the source code near
105: line 5594 to reflect the I/O address you're using, or assign these when
106: loading by:
107:
108: insmod de4x5 io=0xghh where g = bus number
109: hh = device number
110:
111: NB: autoprobing for modules is now supported by default. You may just
112: use:
113:
114: insmod de4x5
115:
116: to load all available boards. For a specific board, still use
117: the 'io=?' above.
118: 3) compile de4x5.c, but include -DMODULE in the command line to ensure
119: that the correct bits are compiled (see end of source code).
120: 4) if you are wanting to add a new card, goto 5. Otherwise, recompile a
121: kernel with the de4x5 configuration turned off and reboot.
122: 5) insmod de4x5 [io=0xghh]
123: 6) run the net startup bits for your new eth?? interface(s) manually
124: (usually /etc/rc.inet[12] at boot time).
125: 7) enjoy!
126:
127: To unload a module, turn off the associated interface(s)
128: 'ifconfig eth?? down' then 'rmmod de4x5'.
129:
130: Automedia detection is included so that in principal you can disconnect
131: from, e.g. TP, reconnect to BNC and things will still work (after a
132: pause whilst the driver figures out where its media went). My tests
133: using ping showed that it appears to work....
134:
135: By default, the driver will now autodetect any DECchip based card.
136: Should you have a need to restrict the driver to DIGITAL only cards, you
137: can compile with a DEC_ONLY define, or if loading as a module, use the
138: 'dec_only=1' parameter.
139:
140: I've changed the timing routines to use the kernel timer and scheduling
141: functions so that the hangs and other assorted problems that occurred
142: while autosensing the media should be gone. A bonus for the DC21040
143: auto media sense algorithm is that it can now use one that is more in
144: line with the rest (the DC21040 chip doesn't have a hardware timer).
145: The downside is the 1 'jiffies' (10ms) resolution.
146:
147: IEEE 802.3u MII interface code has been added in anticipation that some
148: products may use it in the future.
149:
150: The SMC9332 card has a non-compliant SROM which needs fixing - I have
151: patched this driver to detect it because the SROM format used complies
152: to a previous DEC-STD format.
153:
154: I have removed the buffer copies needed for receive on Intels. I cannot
155: remove them for Alphas since the Tulip hardware only does longword
156: aligned DMA transfers and the Alphas get alignment traps with non
157: longword aligned data copies (which makes them really slow). No comment.
158:
159: I have added SROM decoding routines to make this driver work with any
160: card that supports the Digital Semiconductor SROM spec. This will help
161: all cards running the dc2114x series chips in particular. Cards using
162: the dc2104x chips should run correctly with the basic driver. I'm in
163: debt to <[email protected]> for the testing and feedback that helped get
164: this feature working. So far we have tested KINGSTON, SMC8432, SMC9332
165: (with the latest SROM complying with the SROM spec V3: their first was
166: broken), ZNYX342 and LinkSys. ZYNX314 (dual 21041 MAC) and ZNYX 315
167: (quad 21041 MAC) cards also appear to work despite their incorrectly
168: wired IRQs.
169:
170: I have added a temporary fix for interrupt problems when some SCSI cards
171: share the same interrupt as the DECchip based cards. The problem occurs
172: because the SCSI card wants to grab the interrupt as a fast interrupt
173: (runs the service routine with interrupts turned off) vs. this card
174: which really needs to run the service routine with interrupts turned on.
175: This driver will now add the interrupt service routine as a fast
176: interrupt if it is bounced from the slow interrupt. THIS IS NOT A
177: RECOMMENDED WAY TO RUN THE DRIVER and has been done for a limited time
178: until people sort out their compatibility issues and the kernel
179: interrupt service code is fixed. YOU SHOULD SEPARATE OUT THE FAST
180: INTERRUPT CARDS FROM THE SLOW INTERRUPT CARDS to ensure that they do not
181: run on the same interrupt. PCMCIA/CardBus is another can of worms...
182:
183: Finally, I think I have really fixed the module loading problem with
184: more than one DECchip based card. As a side effect, I don't mess with
185: the device structure any more which means that if more than 1 card in
186: 2.0.x is installed (4 in 2.1.x), the user will have to edit
187: linux/drivers/net/Space.c to make room for them. Hence, module loading
188: is the preferred way to use this driver, since it doesn't have this
189: limitation.
190:
191: Where SROM media detection is used and full duplex is specified in the
192: SROM, the feature is ignored unless lp->params.fdx is set at compile
193: time OR during a module load (insmod de4x5 args='eth??:fdx' [see
194: below]). This is because there is no way to automatically detect full
195: duplex links except through autonegotiation. When I include the
196: autonegotiation feature in the SROM autoconf code, this detection will
197: occur automatically for that case.
198:
199: Command line arguments are now allowed, similar to passing arguments
200: through LILO. This will allow a per adapter board set up of full duplex
201: and media. The only lexical constraints are: the board name (dev->name)
202: appears in the list before its parameters. The list of parameters ends
203: either at the end of the parameter list or with another board name. The
204: following parameters are allowed:
205:
206: fdx for full duplex
207: autosense to set the media/speed; with the following
208: sub-parameters:
209: TP, TP_NW, BNC, AUI, BNC_AUI, 100Mb, 10Mb, AUTO
210:
211: Case sensitivity is important for the sub-parameters. They *must* be
212: upper case. Examples:
213:
214: insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
215:
216: For a compiled in driver, in linux/drivers/net/CONFIG, place e.g.
217: DE4X5_OPTS = -DDE4X5_PARM='"eth0:fdx autosense=AUI eth2:autosense=TP"'
218:
219: Yes, I know full duplex isn't permissible on BNC or AUI; they're just
220: examples. By default, full duplex is turned off and AUTO is the default
221: autosense setting. In reality, I expect only the full duplex option to
222: be used. Note the use of single quotes in the two examples above and the
223: lack of commas to separate items.
224:
225: TO DO:
226: ------
227:
228: o check what revision numbers the 21142 and 21143 have
229: o
230:
231: Revision History
232: ----------------
233:
234: Version Date Description
235:
236: 0.1 17-Nov-94 Initial writing. ALPHA code release.
237: 0.2 13-Jan-95 Added PCI support for DE435's.
238: 0.21 19-Jan-95 Added auto media detection.
239: 0.22 10-Feb-95 Fix interrupt handler call <[email protected]>.
240: Fix recognition bug reported by <[email protected]>.
241: Add request/release_region code.
242: Add loadable modules support for PCI.
243: Clean up loadable modules support.
244: 0.23 28-Feb-95 Added DC21041 and DC21140 support.
245: Fix missed frame counter value and initialisation.
246: Fixed EISA probe.
247: 0.24 11-Apr-95 Change delay routine to use <linux/udelay>.
248: Change TX_BUFFS_AVAIL macro.
249: Change media autodetection to allow manual setting.
250: Completed DE500 (DC21140) support.
251: 0.241 18-Apr-95 Interim release without DE500 Autosense Algorithm.
252: 0.242 10-May-95 Minor changes.
253: 0.30 12-Jun-95 Timer fix for DC21140.
254: Portability changes.
255: Add ALPHA changes from <[email protected]>.
256: Add DE500 semi automatic autosense.
257: Add Link Fail interrupt TP failure detection.
258: Add timer based link change detection.
259: Plugged a memory leak in de4x5_queue_pkt().
260: 0.31 13-Jun-95 Fixed PCI stuff for 1.3.1.
261: 0.32 26-Jun-95 Added verify_area() calls in de4x5_ioctl() from a
262: suggestion by <[email protected]>.
263: 0.33 8-Aug-95 Add shared interrupt support (not released yet).
264: 0.331 21-Aug-95 Fix de4x5_open() with fast CPUs.
265: Fix de4x5_interrupt().
266: Fix dc21140_autoconf() mess.
267: No shared interrupt support.
268: 0.332 11-Sep-95 Added MII management interface routines.
269: 0.40 5-Mar-96 Fix setup frame timeout <[email protected]>.
270: Add kernel timer code (h/w is too flaky).
271: Add MII based PHY autosense.
272: Add new multicasting code.
273: Add new autosense algorithms for media/mode
274: selection using kernel scheduling/timing.
275: Re-formatted.
276: Made changes suggested by <[email protected]>:
277: Change driver to detect all DECchip based cards
278: with DEC_ONLY restriction a special case.
279: Changed driver to autoprobe as a module. No irq
280: checking is done now - assume BIOS is good!
281: Added SMC9332 detection <[email protected]>
282: 0.41 21-Mar-96 Don't check for get_hw_addr checksum unless DEC card
283: only <[email protected]>
284: Fix for multiple PCI cards reported by <[email protected]>
285: Duh, put the SA_SHIRQ flag into request_interrupt().
286: Fix SMC ethernet address in enet_det[].
287: Print chip name instead of "UNKNOWN" during boot.
288: 0.42 26-Apr-96 Fix MII write TA bit error.
289: Fix bug in dc21040 and dc21041 autosense code.
290: Remove buffer copies on receive for Intels.
291: Change sk_buff handling during media disconnects to
292: eliminate DUP packets.
293: Add dynamic TX thresholding.
294: Change all chips to use perfect multicast filtering.
295: Fix alloc_device() bug <[email protected]>
296: 0.43 21-Jun-96 Fix unconnected media TX retry bug.
297: Add Accton to the list of broken cards.
298: Fix TX under-run bug for non DC21140 chips.
299: Fix boot command probe bug in alloc_device() as
300: reported by <[email protected]> and
301: <[email protected]>.
302: Add cache locks to prevent a race condition as
303: reported by <[email protected]> and
304: <[email protected]>.
305: Upgraded alloc_device() code.
306: 0.431 28-Jun-96 Fix potential bug in queue_pkt() from discussion
307: with <[email protected]>
308: 0.44 13-Aug-96 Fix RX overflow bug in 2114[023] chips.
309: Fix EISA probe bugs reported by <[email protected]>
310: and <[email protected]>.
311: 0.441 9-Sep-96 Change dc21041_autoconf() to probe quiet BNC media
312: with a loopback packet.
313: 0.442 9-Sep-96 Include AUI in dc21041 media printout. Bug reported
314: by <[email protected]>
315: 0.45 8-Dec-96 Include endian functions for PPC use, from work
316: by <[email protected]> and <[email protected]>.
317: 0.451 28-Dec-96 Added fix to allow autoprobe for modules after
318: suggestion from <[email protected]>.
319: 0.5 30-Jan-97 Added SROM decoding functions.
320: Updated debug flags.
321: Fix sleep/wakeup calls for PCI cards, bug reported
322: by <[email protected]>.
323: Added multi-MAC, one SROM feature from discussion
324: with <[email protected]>.
325: Added full module autoprobe capability.
326: Added attempt to use an SMC9332 with broken SROM.
327: Added fix for ZYNX multi-mac cards that didn't
328: get their IRQs wired correctly.
329: 0.51 13-Feb-97 Added endian fixes for the SROM accesses from
330: <[email protected]>
331: Fix init_connection() to remove extra device reset.
332: Fix MAC/PHY reset ordering in dc21140m_autoconf().
333: Fix initialisation problem with lp->timeout in
334: typeX_infoblock() from <[email protected]>.
335: Fix MII PHY reset problem from work done by
336: <[email protected]>.
337: 0.52 26-Apr-97 Some changes may not credit the right people -
338: a disk crash meant I lost some mail.
339: Change RX interrupt routine to drop rather than
340: defer packets to avoid hang reported by
341: <[email protected]>.
342: Fix srom_exec() to return for COMPACT and type 1
343: infoblocks.
344: Added DC21142 and DC21143 functions.
345: Added byte counters from <[email protected]>
346: Added SA_INTERRUPT temporary fix from
347: <[email protected]>.
348: 0.53 12-Nov-97 Fix the *_probe() to include 'eth??' name during
349: module load: bug reported by
350: <[email protected]>
351: Fix multi-MAC, one SROM, to work with 2114x chips:
352: bug reported by <[email protected]>.
353: Make above search independent of BIOS device scan
354: direction.
355: Completed DC2114[23] autosense functions.
356: 0.531 21-Dec-97 Fix DE500-XA 100Mb/s bug reported by
357: <[email protected]
358: Fix type1_infoblock() bug introduced in 0.53, from
359: problem reports by
360: <[email protected]> and
361: <[email protected]>.
362: Added argument list to set up each board from either
363: a module's command line or a compiled in #define.
364: Added generic MII PHY functionality to deal with
365: newer PHY chips.
366: Fix the mess in 2.1.67.
367: 0.532 5-Jan-98 Fix bug in mii_get_phy() reported by
368: <[email protected]>.
369: Fix bug in pci_probe() for 64 bit systems reported
370: by <[email protected]>.
371: 0.533 9-Jan-98 Fix more 64 bit bugs reported by <[email protected]>.
372: 0.534 24-Jan-98 Fix last (?) endian bug from
373: <[email protected]>
374: 0.535 21-Feb-98 Fix Ethernet Address PROM reset bug for DC21040.
375: 0.5351 4-Oct-98 Atomicize assertion of dev->interrupt for SMP (not
376: for Alpha arch.) from <[email protected]>
377: Add TP, AUI and BNC cases to 21140m_autoconf() for
378: case where a 21140 under SROM control uses, e.g. AUI
379: from problem report by <[email protected]>
380: Add MII parallel detection to 2114x_autoconf() for
381: case where no autonegotiation partner exists from
382: problem report by <[email protected]>.
383: Add ability to force connection type directly even
384: when using SROM control from problem report by
385: <[email protected]>.
386: Fix is_anc_capable() bug reported by
387: <[email protected]>.
388: Fix type[13]_infoblock() bug: during MII search, PHY
389: lp->rst not run because lp->ibn not initialised -
390: from report & fix by <[email protected]>.
391: Fix probe bug with EISA & PCI cards present from
392: report by <[email protected]>.
393: Fix compiler problems associated with i386-string
394: ops from multiple bug reports and temporary fix
395: from <[email protected]>.
396: Add an_exception() for old ZYNX346 and fix compile
397: warning on PPC & SPARC, from <[email protected]>.
398: Fix lastPCI to correctly work with compiled in
399: kernels and modules from bug report by
400: <[email protected]> et al.
401: Fix dc2114x_autoconf() to stop multiple messages
402: when media is unconnected.
403: Change dev->interrupt to lp->interrupt to ensure
404: alignment for Alpha's and avoid their unaligned
405: access traps. This flag is merely for log messages:
406: should do something more definitive though...
407:
408: =========================================================================
409: */
410:
411: static const char *version = "de4x5.c:V0.5351 1998/10/4 [email protected]\n";
412:
413: #include <linux/module.h>
414:
415: #include <linux/kernel.h>
416: #include <linux/sched.h>
417: #include <linux/string.h>
418: #include <linux/interrupt.h>
419: #include <linux/ptrace.h>
420: #include <linux/errno.h>
421: #include <linux/ioport.h>
422: #include <linux/malloc.h>
423: #include <linux/bios32.h>
424: #include <linux/pci.h>
425: #include <linux/delay.h>
426: #include <asm/bitops.h>
427: #include <asm/io.h>
428: #include <asm/dma.h>
429: #include <asm/byteorder.h>
430: #include <asm/unaligned.h>
431:
432: #include <linux/netdevice.h>
433: #include <linux/etherdevice.h>
434: #include <linux/skbuff.h>
435:
436: #include <linux/time.h>
437: #include <linux/types.h>
438: #include <linux/unistd.h>
439: #include <linux/ctype.h>
440:
441: #include "de4x5.h"
442:
443: #define c_char const char
444:
445: #include <linux/version.h>
446: #if LINUX_VERSION_CODE < LinuxVersionCode(2,1,0)
447: # define __initfunc(__arginit) __arginit
1.1.1.2 ! root 448: //# define test_and_set_bit set_bit
1.1 root 449: # define net_device_stats enet_statistics
450: # define copy_to_user(a,b,c) memcpy_tofs(a,b,c)
451: # define copy_from_user(a,b,c) memcpy_fromfs(a,b,c)
452: # define le16_to_cpu(a) cpu_to_le16(a)
453: # define le32_to_cpu(a) cpu_to_le32(a)
454: # ifdef __powerpc__
455: # define cpu_to_le16(a) ((((a) & 0x00ffU) << 8) | (((a) & 0xff00U) >> 8))
456: # define cpu_to_le32(a) ((((a) & 0x000000ffU) << 24) |\
457: (((a) & 0x0000ff00U) << 8) |\
458: (((a) & 0x00ff0000U) >> 8) |\
459: (((a) & 0xff000000U) >> 24))
460: # else
461: # define cpu_to_le16(a) (a)
462: # define cpu_to_le32(a) (a)
463: # endif /* __powerpc__ */
464: # include <asm/segment.h>
465: #else
466: # include <asm/uaccess.h>
467: # include <linux/init.h>
468: #endif /* LINUX_VERSION_CODE */
469: #define TWIDDLE(a) (u_short)le16_to_cpu(get_unaligned((u_short *)(a)))
470:
471: /*
472: ** MII Information
473: */
474: struct phy_table {
475: int reset; /* Hard reset required? */
476: int id; /* IEEE OUI */
477: int ta; /* One cycle TA time - 802.3u is confusing here */
478: struct { /* Non autonegotiation (parallel) speed det. */
479: int reg;
480: int mask;
481: int value;
482: } spd;
483: };
484:
485: struct mii_phy {
486: int reset; /* Hard reset required? */
487: int id; /* IEEE OUI */
488: int ta; /* One cycle TA time */
489: struct { /* Non autonegotiation (parallel) speed det. */
490: int reg;
491: int mask;
492: int value;
493: } spd;
494: int addr; /* MII address for the PHY */
495: u_char *gep; /* Start of GEP sequence block in SROM */
496: u_char *rst; /* Start of reset sequence in SROM */
497: u_int mc; /* Media Capabilities */
498: u_int ana; /* NWay Advertisement */
499: u_int fdx; /* Full DupleX capabilites for each media */
500: u_int ttm; /* Transmit Threshold Mode for each media */
501: u_int mci; /* 21142 MII Connector Interrupt info */
502: };
503:
504: #define DE4X5_MAX_PHY 8 /* Allow upto 8 attached PHY devices per board */
505:
506: struct sia_phy {
507: u_char mc; /* Media Code */
508: u_char ext; /* csr13-15 valid when set */
509: int csr13; /* SIA Connectivity Register */
510: int csr14; /* SIA TX/RX Register */
511: int csr15; /* SIA General Register */
512: int gepc; /* SIA GEP Control Information */
513: int gep; /* SIA GEP Data */
514: };
515:
516: /*
517: ** Define the know universe of PHY devices that can be
518: ** recognised by this driver.
519: */
520: static struct phy_table phy_info[] = {
521: {0, NATIONAL_TX, 1, {0x19, 0x40, 0x00}}, /* National TX */
522: {1, BROADCOM_T4, 1, {0x10, 0x02, 0x02}}, /* Broadcom T4 */
523: {0, SEEQ_T4 , 1, {0x12, 0x10, 0x10}}, /* SEEQ T4 */
524: {0, CYPRESS_T4 , 1, {0x05, 0x20, 0x20}}, /* Cypress T4 */
525: {0, 0x7810 , 1, {0x05, 0x0380, 0x0380}} /* Level One? */
526: };
527:
528: /*
529: ** These GENERIC values assumes that the PHY devices follow 802.3u and
530: ** allow parallel detection to set the link partner ability register.
531: ** Detection of 100Base-TX [H/F Duplex] and 100Base-T4 is supported.
532: */
533: #define GENERIC_REG 0x05 /* Autoneg. Link Partner Advertisement Reg. */
534: #define GENERIC_MASK MII_ANLPA_100M /* All 100Mb/s Technologies */
535: #define GENERIC_VALUE MII_ANLPA_100M /* 100B-TX, 100B-TX FDX, 100B-T4 */
536:
537: /*
538: ** Define special SROM detection cases
539: */
540: static c_char enet_det[][ETH_ALEN] = {
541: {0x00, 0x00, 0xc0, 0x00, 0x00, 0x00},
542: {0x00, 0x00, 0xe8, 0x00, 0x00, 0x00}
543: };
544:
545: #define SMC 1
546: #define ACCTON 2
547:
548: /*
549: ** SROM Repair definitions. If a broken SROM is detected a card may
550: ** use this information to help figure out what to do. This is a
551: ** "stab in the dark" and so far for SMC9332's only.
552: */
553: static c_char srom_repair_info[][100] = {
554: {0x00,0x1e,0x00,0x00,0x00,0x08, /* SMC9332 */
555: 0x1f,0x01,0x8f,0x01,0x00,0x01,0x00,0x02,
556: 0x01,0x00,0x00,0x78,0xe0,0x01,0x00,0x50,
557: 0x00,0x18,}
558: };
559:
560:
561: #ifdef DE4X5_DEBUG
562: static int de4x5_debug = DE4X5_DEBUG;
563: #else
564: /*static int de4x5_debug = (DEBUG_MII | DEBUG_SROM | DEBUG_PCICFG | DEBUG_MEDIA | DEBUG_VERSION);*/
565: static int de4x5_debug = (DEBUG_MEDIA | DEBUG_VERSION);
566: #endif
567:
568: /*
569: ** Allow per adapter set up. For modules this is simply a command line
570: ** parameter, e.g.:
571: ** insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
572: **
573: ** For a compiled in driver, place e.g.
574: ** DE4X5_OPTS = -DDE4X5_PARM='"eth0:fdx autosense=AUI eth2:autosense=TP"'
575: ** in linux/drivers/net/CONFIG
576: */
577: #ifdef DE4X5_PARM
578: static char *args = DE4X5_PARM;
579: #else
580: static char *args = NULL;
581: #endif
582:
583: struct parameters {
584: int fdx;
585: int autosense;
586: };
587:
588: #define DE4X5_AUTOSENSE_MS 250 /* msec autosense tick (DE500) */
589:
590: #define DE4X5_NDA 0xffe0 /* No Device (I/O) Address */
591:
592: /*
593: ** Ethernet PROM defines
594: */
595: #define PROBE_LENGTH 32
596: #define ETH_PROM_SIG 0xAA5500FFUL
597:
598: /*
599: ** Ethernet Info
600: */
601: #define PKT_BUF_SZ 1536 /* Buffer size for each Tx/Rx buffer */
602: #define IEEE802_3_SZ 1518 /* Packet + CRC */
603: #define MAX_PKT_SZ 1514 /* Maximum ethernet packet length */
604: #define MAX_DAT_SZ 1500 /* Maximum ethernet data length */
605: #define MIN_DAT_SZ 1 /* Minimum ethernet data length */
606: #define PKT_HDR_LEN 14 /* Addresses and data length info */
607: #define FAKE_FRAME_LEN (MAX_PKT_SZ + 1)
608: #define QUEUE_PKT_TIMEOUT (3*HZ) /* 3 second timeout */
609:
610:
611: #define CRC_POLYNOMIAL_BE 0x04c11db7UL /* Ethernet CRC, big endian */
612: #define CRC_POLYNOMIAL_LE 0xedb88320UL /* Ethernet CRC, little endian */
613:
614: /*
615: ** EISA bus defines
616: */
617: #define DE4X5_EISA_IO_PORTS 0x0c00 /* I/O port base address, slot 0 */
618: #define DE4X5_EISA_TOTAL_SIZE 0x100 /* I/O address extent */
619:
620: #define MAX_EISA_SLOTS 16
621: #define EISA_SLOT_INC 0x1000
622: #define EISA_ALLOWED_IRQ_LIST {5, 9, 10, 11}
623:
624: #define DE4X5_SIGNATURE {"DE425","DE434","DE435","DE450","DE500"}
625: #define DE4X5_NAME_LENGTH 8
626:
627: /*
628: ** Ethernet PROM defines for DC21040
629: */
630: #define PROBE_LENGTH 32
631: #define ETH_PROM_SIG 0xAA5500FFUL
632:
633: /*
634: ** PCI Bus defines
635: */
636: #define PCI_MAX_BUS_NUM 8
637: #define DE4X5_PCI_TOTAL_SIZE 0x80 /* I/O address extent */
638: #define DE4X5_CLASS_CODE 0x00020000 /* Network controller, Ethernet */
639: #define NO_MORE_PCI -2 /* PCI bus search all done */
640:
641: /*
642: ** Memory Alignment. Each descriptor is 4 longwords long. To force a
643: ** particular alignment on the TX descriptor, adjust DESC_SKIP_LEN and
644: ** DESC_ALIGN. ALIGN aligns the start address of the private memory area
645: ** and hence the RX descriptor ring's first entry.
646: */
647: #define ALIGN4 ((u_long)4 - 1) /* 1 longword align */
648: #define ALIGN8 ((u_long)8 - 1) /* 2 longword align */
649: #define ALIGN16 ((u_long)16 - 1) /* 4 longword align */
650: #define ALIGN32 ((u_long)32 - 1) /* 8 longword align */
651: #define ALIGN64 ((u_long)64 - 1) /* 16 longword align */
652: #define ALIGN128 ((u_long)128 - 1) /* 32 longword align */
653:
654: #define ALIGN ALIGN32 /* Keep the DC21040 happy... */
655: #define CACHE_ALIGN CAL_16LONG
656: #define DESC_SKIP_LEN DSL_0 /* Must agree with DESC_ALIGN */
657: /*#define DESC_ALIGN u32 dummy[4]; / * Must agree with DESC_SKIP_LEN */
658: #define DESC_ALIGN
659:
660: #ifndef DEC_ONLY /* See README.de4x5 for using this */
661: static int dec_only = 0;
662: #else
663: static int dec_only = 1;
664: #endif
665:
666: /*
667: ** DE4X5 IRQ ENABLE/DISABLE
668: */
669: #define ENABLE_IRQs { \
670: imr |= lp->irq_en;\
671: outl(imr, DE4X5_IMR); /* Enable the IRQs */\
672: }
673:
674: #define DISABLE_IRQs {\
675: imr = inl(DE4X5_IMR);\
676: imr &= ~lp->irq_en;\
677: outl(imr, DE4X5_IMR); /* Disable the IRQs */\
678: }
679:
680: #define UNMASK_IRQs {\
681: imr |= lp->irq_mask;\
682: outl(imr, DE4X5_IMR); /* Unmask the IRQs */\
683: }
684:
685: #define MASK_IRQs {\
686: imr = inl(DE4X5_IMR);\
687: imr &= ~lp->irq_mask;\
688: outl(imr, DE4X5_IMR); /* Mask the IRQs */\
689: }
690:
691: /*
692: ** DE4X5 START/STOP
693: */
694: #define START_DE4X5 {\
695: omr = inl(DE4X5_OMR);\
696: omr |= OMR_ST | OMR_SR;\
697: outl(omr, DE4X5_OMR); /* Enable the TX and/or RX */\
698: }
699:
700: #define STOP_DE4X5 {\
701: omr = inl(DE4X5_OMR);\
702: omr &= ~(OMR_ST|OMR_SR);\
703: outl(omr, DE4X5_OMR); /* Disable the TX and/or RX */ \
704: }
705:
706: /*
707: ** DE4X5 SIA RESET
708: */
709: #define RESET_SIA outl(0, DE4X5_SICR); /* Reset SIA connectivity regs */
710:
711: /*
712: ** DE500 AUTOSENSE TIMER INTERVAL (MILLISECS)
713: */
714: #define DE4X5_AUTOSENSE_MS 250
715:
716: /*
717: ** SROM Structure
718: */
719: struct de4x5_srom {
720: char sub_vendor_id[2];
721: char sub_system_id[2];
722: char reserved[12];
723: char id_block_crc;
724: char reserved2;
725: char version;
726: char num_controllers;
727: char ieee_addr[6];
728: char info[100];
729: short chksum;
730: };
731: #define SUB_VENDOR_ID 0x500a
732:
733: /*
734: ** DE4X5 Descriptors. Make sure that all the RX buffers are contiguous
735: ** and have sizes of both a power of 2 and a multiple of 4.
736: ** A size of 256 bytes for each buffer could be chosen because over 90% of
737: ** all packets in our network are <256 bytes long and 64 longword alignment
738: ** is possible. 1536 showed better 'ttcp' performance. Take your pick. 32 TX
739: ** descriptors are needed for machines with an ALPHA CPU.
740: */
741: #define NUM_RX_DESC 8 /* Number of RX descriptors */
742: #define NUM_TX_DESC 32 /* Number of TX descriptors */
743: #define RX_BUFF_SZ 1536 /* Power of 2 for kmalloc and */
744: /* Multiple of 4 for DC21040 */
745: /* Allows 512 byte alignment */
746: struct de4x5_desc {
747: volatile s32 status;
748: u32 des1;
749: u32 buf;
750: u32 next;
751: DESC_ALIGN
752: };
753:
754: /*
755: ** The DE4X5 private structure
756: */
757: #define DE4X5_PKT_STAT_SZ 16
758: #define DE4X5_PKT_BIN_SZ 128 /* Should be >=100 unless you
759: increase DE4X5_PKT_STAT_SZ */
760:
761: struct de4x5_private {
762: char adapter_name[80]; /* Adapter name */
763: u_long interrupt; /* Aligned ISR flag */
764: struct de4x5_desc rx_ring[NUM_RX_DESC]; /* RX descriptor ring */
765: struct de4x5_desc tx_ring[NUM_TX_DESC]; /* TX descriptor ring */
766: struct sk_buff *tx_skb[NUM_TX_DESC]; /* TX skb for freeing when sent */
767: struct sk_buff *rx_skb[NUM_RX_DESC]; /* RX skb's */
768: int rx_new, rx_old; /* RX descriptor ring pointers */
769: int tx_new, tx_old; /* TX descriptor ring pointers */
770: char setup_frame[SETUP_FRAME_LEN]; /* Holds MCA and PA info. */
771: char frame[64]; /* Min sized packet for loopback*/
772: struct net_device_stats stats; /* Public stats */
773: struct {
774: u_int bins[DE4X5_PKT_STAT_SZ]; /* Private stats counters */
775: u_int unicast;
776: u_int multicast;
777: u_int broadcast;
778: u_int excessive_collisions;
779: u_int tx_underruns;
780: u_int excessive_underruns;
781: u_int rx_runt_frames;
782: u_int rx_collision;
783: u_int rx_dribble;
784: u_int rx_overflow;
785: } pktStats;
786: char rxRingSize;
787: char txRingSize;
788: int bus; /* EISA or PCI */
789: int bus_num; /* PCI Bus number */
790: int device; /* Device number on PCI bus */
791: int state; /* Adapter OPENED or CLOSED */
792: int chipset; /* DC21040, DC21041 or DC21140 */
793: s32 irq_mask; /* Interrupt Mask (Enable) bits */
794: s32 irq_en; /* Summary interrupt bits */
795: int media; /* Media (eg TP), mode (eg 100B)*/
796: int c_media; /* Remember the last media conn */
797: int fdx; /* media full duplex flag */
798: int linkOK; /* Link is OK */
799: int autosense; /* Allow/disallow autosensing */
800: int tx_enable; /* Enable descriptor polling */
801: int setup_f; /* Setup frame filtering type */
802: int local_state; /* State within a 'media' state */
803: struct mii_phy phy[DE4X5_MAX_PHY]; /* List of attached PHY devices */
804: struct sia_phy sia; /* SIA PHY Information */
805: int active; /* Index to active PHY device */
806: int mii_cnt; /* Number of attached PHY's */
807: int timeout; /* Scheduling counter */
808: struct timer_list timer; /* Timer info for kernel */
809: int tmp; /* Temporary global per card */
810: struct {
811: void *priv; /* Original kmalloc'd mem addr */
812: void *buf; /* Original kmalloc'd mem addr */
813: u_long lock; /* Lock the cache accesses */
814: s32 csr0; /* Saved Bus Mode Register */
815: s32 csr6; /* Saved Operating Mode Reg. */
816: s32 csr7; /* Saved IRQ Mask Register */
817: s32 gep; /* Saved General Purpose Reg. */
818: s32 gepc; /* Control info for GEP */
819: s32 csr13; /* Saved SIA Connectivity Reg. */
820: s32 csr14; /* Saved SIA TX/RX Register */
821: s32 csr15; /* Saved SIA General Register */
822: int save_cnt; /* Flag if state already saved */
823: struct sk_buff *skb; /* Save the (re-ordered) skb's */
824: } cache;
825: struct de4x5_srom srom; /* A copy of the SROM */
826: struct device *next_module; /* Link to the next module */
827: int rx_ovf; /* Check for 'RX overflow' tag */
828: int useSROM; /* For non-DEC card use SROM */
829: int useMII; /* Infoblock using the MII */
830: int asBitValid; /* Autosense bits in GEP? */
831: int asPolarity; /* 0 => asserted high */
832: int asBit; /* Autosense bit number in GEP */
833: int defMedium; /* SROM default medium */
834: int tcount; /* Last infoblock number */
835: int infoblock_init; /* Initialised this infoblock? */
836: int infoleaf_offset; /* SROM infoleaf for controller */
837: s32 infoblock_csr6; /* csr6 value in SROM infoblock */
838: int infoblock_media; /* infoblock media */
839: int (*infoleaf_fn)(struct device *); /* Pointer to infoleaf function */
840: u_char *rst; /* Pointer to Type 5 reset info */
841: u_char ibn; /* Infoblock number */
842: struct parameters params; /* Command line/ #defined params */
843: };
844:
845: /*
846: ** Kludge to get around the fact that the CSR addresses have different
847: ** offsets in the PCI and EISA boards. Also note that the ethernet address
848: ** PROM is accessed differently.
849: */
850: static struct bus_type {
851: int bus;
852: int bus_num;
853: int device;
854: int chipset;
855: struct de4x5_srom srom;
856: int autosense;
857: int useSROM;
858: } bus;
859:
860: /*
861: ** To get around certain poxy cards that don't provide an SROM
862: ** for the second and more DECchip, I have to key off the first
863: ** chip's address. I'll assume there's not a bad SROM iff:
864: **
865: ** o the chipset is the same
866: ** o the bus number is the same and > 0
867: ** o the sum of all the returned hw address bytes is 0 or 0x5fa
868: **
869: ** Also have to save the irq for those cards whose hardware designers
870: ** can't follow the PCI to PCI Bridge Architecture spec.
871: */
872: static struct {
873: int chipset;
874: int bus;
875: int irq;
876: u_char addr[ETH_ALEN];
877: } last = {0,};
878:
879: /*
880: ** The transmit ring full condition is described by the tx_old and tx_new
881: ** pointers by:
882: ** tx_old = tx_new Empty ring
883: ** tx_old = tx_new+1 Full ring
884: ** tx_old+txRingSize = tx_new+1 Full ring (wrapped condition)
885: */
886: #define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\
887: lp->tx_old+lp->txRingSize-lp->tx_new-1:\
888: lp->tx_old -lp->tx_new-1)
889:
890: #define TX_PKT_PENDING (lp->tx_old != lp->tx_new)
891:
892: /*
893: ** Public Functions
894: */
895: static int de4x5_open(struct device *dev);
896: static int de4x5_queue_pkt(struct sk_buff *skb, struct device *dev);
897: static void de4x5_interrupt(int irq, void *dev_id, struct pt_regs *regs);
898: static int de4x5_close(struct device *dev);
899: static struct net_device_stats *de4x5_get_stats(struct device *dev);
900: static void de4x5_local_stats(struct device *dev, char *buf, int pkt_len);
901: static void set_multicast_list(struct device *dev);
902: static int de4x5_ioctl(struct device *dev, struct ifreq *rq, int cmd);
903:
904: /*
905: ** Private functions
906: */
907: static int de4x5_hw_init(struct device *dev, u_long iobase);
908: static int de4x5_init(struct device *dev);
909: static int de4x5_sw_reset(struct device *dev);
910: static int de4x5_rx(struct device *dev);
911: static int de4x5_tx(struct device *dev);
912: static int de4x5_ast(struct device *dev);
913: static int de4x5_txur(struct device *dev);
914: static int de4x5_rx_ovfc(struct device *dev);
915:
916: static int autoconf_media(struct device *dev);
917: static void create_packet(struct device *dev, char *frame, int len);
918: static void de4x5_us_delay(u32 usec);
919: static void de4x5_ms_delay(u32 msec);
920: static void load_packet(struct device *dev, char *buf, u32 flags, struct sk_buff *skb);
921: static int dc21040_autoconf(struct device *dev);
922: static int dc21041_autoconf(struct device *dev);
923: static int dc21140m_autoconf(struct device *dev);
924: static int dc2114x_autoconf(struct device *dev);
925: static int srom_autoconf(struct device *dev);
926: static int de4x5_suspect_state(struct device *dev, int timeout, int prev_state, int (*fn)(struct device *, int), int (*asfn)(struct device *));
927: static int dc21040_state(struct device *dev, int csr13, int csr14, int csr15, int timeout, int next_state, int suspect_state, int (*fn)(struct device *, int));
928: static int test_media(struct device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec);
929: static int test_for_100Mb(struct device *dev, int msec);
930: static int wait_for_link(struct device *dev);
931: static int test_mii_reg(struct device *dev, int reg, int mask, int pol, long msec);
932: static int is_spd_100(struct device *dev);
933: static int is_100_up(struct device *dev);
934: static int is_10_up(struct device *dev);
935: static int is_anc_capable(struct device *dev);
936: static int ping_media(struct device *dev, int msec);
937: static struct sk_buff *de4x5_alloc_rx_buff(struct device *dev, int index, int len);
938: static void de4x5_free_rx_buffs(struct device *dev);
939: static void de4x5_free_tx_buffs(struct device *dev);
940: static void de4x5_save_skbs(struct device *dev);
941: static void de4x5_rst_desc_ring(struct device *dev);
942: static void de4x5_cache_state(struct device *dev, int flag);
943: static void de4x5_put_cache(struct device *dev, struct sk_buff *skb);
944: static void de4x5_putb_cache(struct device *dev, struct sk_buff *skb);
945: static struct sk_buff *de4x5_get_cache(struct device *dev);
946: static void de4x5_setup_intr(struct device *dev);
947: static void de4x5_init_connection(struct device *dev);
948: static int de4x5_reset_phy(struct device *dev);
949: static void reset_init_sia(struct device *dev, s32 sicr, s32 strr, s32 sigr);
950: static int test_ans(struct device *dev, s32 irqs, s32 irq_mask, s32 msec);
951: static int test_tp(struct device *dev, s32 msec);
952: static int EISA_signature(char *name, s32 eisa_id);
953: static int PCI_signature(char *name, struct bus_type *lp);
954: static void DevicePresent(u_long iobase);
955: static void enet_addr_rst(u_long aprom_addr);
956: static int de4x5_bad_srom(struct bus_type *lp);
957: static short srom_rd(u_long address, u_char offset);
958: static void srom_latch(u_int command, u_long address);
959: static void srom_command(u_int command, u_long address);
960: static void srom_address(u_int command, u_long address, u_char offset);
961: static short srom_data(u_int command, u_long address);
962: /*static void srom_busy(u_int command, u_long address);*/
963: static void sendto_srom(u_int command, u_long addr);
964: static int getfrom_srom(u_long addr);
965: static int srom_map_media(struct device *dev);
966: static int srom_infoleaf_info(struct device *dev);
967: static void srom_init(struct device *dev);
968: static void srom_exec(struct device *dev, u_char *p);
969: static int mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr);
970: static void mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr);
971: static int mii_rdata(u_long ioaddr);
972: static void mii_wdata(int data, int len, u_long ioaddr);
973: static void mii_ta(u_long rw, u_long ioaddr);
974: static int mii_swap(int data, int len);
975: static void mii_address(u_char addr, u_long ioaddr);
976: static void sendto_mii(u32 command, int data, u_long ioaddr);
977: static int getfrom_mii(u32 command, u_long ioaddr);
978: static int mii_get_oui(u_char phyaddr, u_long ioaddr);
979: static int mii_get_phy(struct device *dev);
980: static void SetMulticastFilter(struct device *dev);
981: static int get_hw_addr(struct device *dev);
982: static void srom_repair(struct device *dev, int card);
983: static int test_bad_enet(struct device *dev, int status);
984: static int an_exception(struct bus_type *lp);
985: #if !defined(__sparc_v9__) && !defined(__powerpc__) && !defined(__alpha__)
986: static void eisa_probe(struct device *dev, u_long iobase);
987: #endif
988: static void pci_probe(struct device *dev, u_long iobase);
989: static void srom_search(int index);
990: static char *build_setup_frame(struct device *dev, int mode);
991: static void disable_ast(struct device *dev);
992: static void enable_ast(struct device *dev, u32 time_out);
993: static long de4x5_switch_mac_port(struct device *dev);
994: static int gep_rd(struct device *dev);
995: static void gep_wr(s32 data, struct device *dev);
996: static void timeout(struct device *dev, void (*fn)(u_long data), u_long data, u_long msec);
997: static void yawn(struct device *dev, int state);
998: static void link_modules(struct device *dev, struct device *tmp);
999: static void de4x5_parse_params(struct device *dev);
1000: static void de4x5_dbg_open(struct device *dev);
1001: static void de4x5_dbg_mii(struct device *dev, int k);
1002: static void de4x5_dbg_media(struct device *dev);
1003: static void de4x5_dbg_srom(struct de4x5_srom *p);
1004: static void de4x5_dbg_rx(struct sk_buff *skb, int len);
1005: static int de4x5_strncmp(char *a, char *b, int n);
1006: static int dc21041_infoleaf(struct device *dev);
1007: static int dc21140_infoleaf(struct device *dev);
1008: static int dc21142_infoleaf(struct device *dev);
1009: static int dc21143_infoleaf(struct device *dev);
1010: static int type0_infoblock(struct device *dev, u_char count, u_char *p);
1011: static int type1_infoblock(struct device *dev, u_char count, u_char *p);
1012: static int type2_infoblock(struct device *dev, u_char count, u_char *p);
1013: static int type3_infoblock(struct device *dev, u_char count, u_char *p);
1014: static int type4_infoblock(struct device *dev, u_char count, u_char *p);
1015: static int type5_infoblock(struct device *dev, u_char count, u_char *p);
1016: static int compact_infoblock(struct device *dev, u_char count, u_char *p);
1017:
1018: #ifdef MODULE
1019: int init_module(void);
1020: void cleanup_module(void);
1021: static struct device *unlink_modules(struct device *p);
1022: static struct device *insert_device(struct device *dev, u_long iobase,
1023: int (*init)(struct device *));
1024: static int count_adapters(void);
1025: static int loading_module = 1;
1026: #if LINUX_VERSION_CODE >= LinuxVersionCode(2,1,0)
1027: MODULE_PARM(de4x5_debug, "i");
1028: MODULE_PARM(dec_only, "i");
1029: MODULE_PARM(args, "s");
1030: #endif /* LINUX_VERSION_CODE */
1031: # else
1032: static int loading_module = 0;
1033: #endif /* MODULE */
1034:
1035: static char name[DE4X5_NAME_LENGTH + 1];
1036: #if !defined(__sparc_v9__) && !defined(__powerpc__) && !defined(__alpha__)
1037: static u_char de4x5_irq[] = EISA_ALLOWED_IRQ_LIST;
1038: static int lastEISA = 0;
1039: #else
1040: static int lastEISA = MAX_EISA_SLOTS; /* Only PCI probes */
1041: #endif
1042: static int num_de4x5s = 0;
1043: static int cfrv = 0, useSROM = 0;
1044: static int lastPCI = -1;
1045: static struct device *lastModule = NULL;
1046:
1047: /*
1048: ** List the SROM infoleaf functions and chipsets
1049: */
1050: struct InfoLeaf {
1051: int chipset;
1052: int (*fn)(struct device *);
1053: };
1054: static struct InfoLeaf infoleaf_array[] = {
1055: {DC21041, dc21041_infoleaf},
1056: {DC21140, dc21140_infoleaf},
1057: {DC21142, dc21142_infoleaf},
1058: {DC21143, dc21143_infoleaf}
1059: };
1060: #define INFOLEAF_SIZE (sizeof(infoleaf_array)/(sizeof(int)+sizeof(int *)))
1061:
1062: /*
1063: ** List the SROM info block functions
1064: */
1065: static int (*dc_infoblock[])(struct device *dev, u_char, u_char *) = {
1066: type0_infoblock,
1067: type1_infoblock,
1068: type2_infoblock,
1069: type3_infoblock,
1070: type4_infoblock,
1071: type5_infoblock,
1072: compact_infoblock
1073: };
1074:
1075: #define COMPACT (sizeof(dc_infoblock)/sizeof(int *) - 1)
1076:
1077: /*
1078: ** Miscellaneous defines...
1079: */
1080: #define RESET_DE4X5 {\
1081: int i;\
1082: i=inl(DE4X5_BMR);\
1083: de4x5_ms_delay(1);\
1084: outl(i | BMR_SWR, DE4X5_BMR);\
1085: de4x5_ms_delay(1);\
1086: outl(i, DE4X5_BMR);\
1087: de4x5_ms_delay(1);\
1088: for (i=0;i<5;i++) {inl(DE4X5_BMR); de4x5_ms_delay(1);}\
1089: de4x5_ms_delay(1);\
1090: }
1091:
1092: #define PHY_HARD_RESET {\
1093: outl(GEP_HRST, DE4X5_GEP); /* Hard RESET the PHY dev. */\
1094: udelay(1000); /* Assert for 1ms */\
1095: outl(0x00, DE4X5_GEP);\
1096: udelay(2000); /* Wait for 2ms */\
1097: }
1098:
1099:
1100: /*
1101: ** Autoprobing in modules is allowed here. See the top of the file for
1102: ** more info.
1103: */
1104: __initfunc(int
1105: de4x5_probe(struct device *dev))
1106: {
1107: u_long iobase = dev->base_addr;
1108:
1109: #if !defined(__sparc_v9__) && !defined(__powerpc__) && !defined(__alpha__)
1110: eisa_probe(dev, iobase);
1111: #endif
1112: if (lastEISA == MAX_EISA_SLOTS) {
1113: pci_probe(dev, iobase);
1114: }
1115:
1116: return (dev->priv ? 0 : -ENODEV);
1117: }
1118:
1119: __initfunc(static int
1120: de4x5_hw_init(struct device *dev, u_long iobase))
1121: {
1122: struct bus_type *lp = &bus;
1123: int i, status=0;
1124: char *tmp;
1125:
1126: /* Ensure we're not sleeping */
1127: if (lp->bus == EISA) {
1128: outb(WAKEUP, PCI_CFPM);
1129: } else {
1130: pcibios_write_config_byte(lp->bus_num, lp->device << 3,
1131: PCI_CFDA_PSM, WAKEUP);
1132: }
1133: de4x5_ms_delay(10);
1134:
1135: RESET_DE4X5;
1136:
1137: if ((inl(DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
1138: return -ENXIO; /* Hardware could not reset */
1139: }
1140:
1141: /*
1142: ** Now find out what kind of DC21040/DC21041/DC21140 board we have.
1143: */
1144: useSROM = FALSE;
1145: if (lp->bus == PCI) {
1146: PCI_signature(name, lp);
1147: } else {
1148: EISA_signature(name, EISA_ID0);
1149: }
1150:
1151: if (*name == '\0') { /* Not found a board signature */
1152: return -ENXIO;
1153: }
1154:
1155: dev->base_addr = iobase;
1156: if (lp->bus == EISA) {
1157: printk("%s: %s at 0x%04lx (EISA slot %ld)",
1158: dev->name, name, iobase, ((iobase>>12)&0x0f));
1159: } else { /* PCI port address */
1160: printk("%s: %s at 0x%04lx (PCI bus %d, device %d)", dev->name, name,
1161: iobase, lp->bus_num, lp->device);
1162: }
1163:
1164: printk(", h/w address ");
1165: status = get_hw_addr(dev);
1166: for (i = 0; i < ETH_ALEN - 1; i++) { /* get the ethernet addr. */
1167: printk("%2.2x:", dev->dev_addr[i]);
1168: }
1169: printk("%2.2x,\n", dev->dev_addr[i]);
1170:
1171: if (status != 0) {
1172: printk(" which has an Ethernet PROM CRC error.\n");
1173: return -ENXIO;
1174: } else {
1175: struct de4x5_private *lp;
1176:
1177: /*
1178: ** Reserve a section of kernel memory for the adapter
1179: ** private area and the TX/RX descriptor rings.
1180: */
1181: dev->priv = (void *) kmalloc(sizeof(struct de4x5_private) + ALIGN,
1182: GFP_KERNEL);
1183: if (dev->priv == NULL) {
1184: return -ENOMEM;
1185: }
1186:
1187: /*
1188: ** Align to a longword boundary
1189: */
1190: tmp = dev->priv;
1191: dev->priv = (void *)(((u_long)dev->priv + ALIGN) & ~ALIGN);
1192: lp = (struct de4x5_private *)dev->priv;
1193: memset(dev->priv, 0, sizeof(struct de4x5_private));
1194: lp->bus = bus.bus;
1195: lp->bus_num = bus.bus_num;
1196: lp->device = bus.device;
1197: lp->chipset = bus.chipset;
1198: lp->cache.priv = tmp;
1199: lp->cache.gepc = GEP_INIT;
1200: lp->asBit = GEP_SLNK;
1201: lp->asPolarity = GEP_SLNK;
1202: lp->asBitValid = TRUE;
1203: lp->timeout = -1;
1204: lp->useSROM = useSROM;
1205: memcpy((char *)&lp->srom,(char *)&bus.srom,sizeof(struct de4x5_srom));
1206: de4x5_parse_params(dev);
1207:
1208: /*
1209: ** Choose correct autosensing in case someone messed up
1210: */
1211: lp->autosense = lp->params.autosense;
1212: if (lp->chipset != DC21140) {
1213: if ((lp->chipset==DC21040) && (lp->params.autosense&TP_NW)) {
1214: lp->params.autosense = TP;
1215: }
1216: if ((lp->chipset==DC21041) && (lp->params.autosense&BNC_AUI)) {
1217: lp->params.autosense = BNC;
1218: }
1219: }
1220: lp->fdx = lp->params.fdx;
1221: sprintf(lp->adapter_name,"%s (%s)", name, dev->name);
1222:
1223: /*
1224: ** Set up the RX descriptor ring (Intels)
1225: ** Allocate contiguous receive buffers, long word aligned (Alphas)
1226: */
1227: #if !defined(__alpha__) && !defined(__powerpc__) && !defined(__sparc_v9__) && !defined(DE4X5_DO_MEMCPY)
1228: for (i=0; i<NUM_RX_DESC; i++) {
1229: lp->rx_ring[i].status = 0;
1230: lp->rx_ring[i].des1 = RX_BUFF_SZ;
1231: lp->rx_ring[i].buf = 0;
1232: lp->rx_ring[i].next = 0;
1233: lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1234: }
1235:
1236: #else
1237: if ((tmp = (void *)kmalloc(RX_BUFF_SZ * NUM_RX_DESC + ALIGN,
1238: GFP_KERNEL)) == NULL) {
1239: kfree(lp->cache.priv);
1240: return -ENOMEM;
1241: }
1242:
1243: lp->cache.buf = tmp;
1244: tmp = (char *)(((u_long) tmp + ALIGN) & ~ALIGN);
1245: for (i=0; i<NUM_RX_DESC; i++) {
1246: lp->rx_ring[i].status = 0;
1247: lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1248: lp->rx_ring[i].buf = cpu_to_le32(virt_to_bus(tmp+i*RX_BUFF_SZ));
1249: lp->rx_ring[i].next = 0;
1250: lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1251: }
1252: #endif
1253:
1254: barrier();
1255:
1256: request_region(iobase, (lp->bus == PCI ? DE4X5_PCI_TOTAL_SIZE :
1257: DE4X5_EISA_TOTAL_SIZE),
1258: lp->adapter_name);
1259:
1260: lp->rxRingSize = NUM_RX_DESC;
1261: lp->txRingSize = NUM_TX_DESC;
1262:
1263: /* Write the end of list marker to the descriptor lists */
1264: lp->rx_ring[lp->rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
1265: lp->tx_ring[lp->txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
1266:
1267: /* Tell the adapter where the TX/RX rings are located. */
1268: outl(virt_to_bus(lp->rx_ring), DE4X5_RRBA);
1269: outl(virt_to_bus(lp->tx_ring), DE4X5_TRBA);
1270:
1271: /* Initialise the IRQ mask and Enable/Disable */
1272: lp->irq_mask = IMR_RIM | IMR_TIM | IMR_TUM | IMR_UNM;
1273: lp->irq_en = IMR_NIM | IMR_AIM;
1274:
1275: /* Create a loopback packet frame for later media probing */
1276: create_packet(dev, lp->frame, sizeof(lp->frame));
1277:
1278: /* Check if the RX overflow bug needs testing for */
1279: i = cfrv & 0x000000fe;
1280: if ((lp->chipset == DC21140) && (i == 0x20)) {
1281: lp->rx_ovf = 1;
1282: }
1283:
1284: /* Initialise the SROM pointers if possible */
1285: if (lp->useSROM) {
1286: lp->state = INITIALISED;
1287: if (srom_infoleaf_info(dev)) {
1288: return -ENXIO;
1289: }
1290: srom_init(dev);
1291: }
1292:
1293: lp->state = CLOSED;
1294:
1295: /*
1296: ** Check for an MII interface
1297: */
1298: if ((lp->chipset != DC21040) && (lp->chipset != DC21041)) {
1299: mii_get_phy(dev);
1300: }
1301:
1302: #ifndef __sparc_v9__
1303: printk(" and requires IRQ%d (provided by %s).\n", dev->irq,
1304: #else
1305: printk(" and requires IRQ%x (provided by %s).\n", dev->irq,
1306: #endif
1307: ((lp->bus == PCI) ? "PCI BIOS" : "EISA CNFG"));
1308: }
1309:
1310: if (de4x5_debug & DEBUG_VERSION) {
1311: printk(version);
1312: }
1313:
1314: /* The DE4X5-specific entries in the device structure. */
1315: dev->open = &de4x5_open;
1316: dev->hard_start_xmit = &de4x5_queue_pkt;
1317: dev->stop = &de4x5_close;
1318: dev->get_stats = &de4x5_get_stats;
1319: dev->set_multicast_list = &set_multicast_list;
1320: dev->do_ioctl = &de4x5_ioctl;
1321:
1322: dev->mem_start = 0;
1323:
1324: /* Fill in the generic fields of the device structure. */
1325: ether_setup(dev);
1326:
1327: /* Let the adapter sleep to save power */
1328: yawn(dev, SLEEP);
1329:
1330: return status;
1331: }
1332:
1333:
1334: static int
1335: de4x5_open(struct device *dev)
1336: {
1337: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1338: u_long iobase = dev->base_addr;
1339: int i, status = 0;
1340: s32 omr;
1341:
1342: /* Allocate the RX buffers */
1343: for (i=0; i<lp->rxRingSize; i++) {
1344: if (de4x5_alloc_rx_buff(dev, i, 0) == NULL) {
1345: de4x5_free_rx_buffs(dev);
1346: return -EAGAIN;
1347: }
1348: }
1349:
1350: /*
1351: ** Wake up the adapter
1352: */
1353: yawn(dev, WAKEUP);
1354:
1355: /*
1356: ** Re-initialize the DE4X5...
1357: */
1358: status = de4x5_init(dev);
1359:
1360: lp->state = OPEN;
1361: de4x5_dbg_open(dev);
1362:
1363: if (request_irq(dev->irq, (void *)de4x5_interrupt, SA_SHIRQ,
1364: lp->adapter_name, dev)) {
1365: printk("de4x5_open(): Requested IRQ%d is busy - attemping FAST/SHARE...", dev->irq);
1366: if (request_irq(dev->irq, de4x5_interrupt, SA_INTERRUPT | SA_SHIRQ,
1367: lp->adapter_name, dev)) {
1368: printk("\n Cannot get IRQ- reconfigure your hardware.\n");
1369: disable_ast(dev);
1370: de4x5_free_rx_buffs(dev);
1371: de4x5_free_tx_buffs(dev);
1372: yawn(dev, SLEEP);
1373: lp->state = CLOSED;
1374: return -EAGAIN;
1375: } else {
1376: printk("\n Succeeded, but you should reconfigure your hardware to avoid this.\n");
1377: printk("WARNING: there may be IRQ related problems in heavily loaded systems.\n");
1378: }
1379: }
1380:
1381: dev->tbusy = 0;
1382: dev->start = 1;
1383: lp->interrupt = UNMASK_INTERRUPTS;
1384: dev->trans_start = jiffies;
1385:
1386: START_DE4X5;
1387:
1388: de4x5_setup_intr(dev);
1389:
1390: if (de4x5_debug & DEBUG_OPEN) {
1391: printk("\tsts: 0x%08x\n", inl(DE4X5_STS));
1392: printk("\tbmr: 0x%08x\n", inl(DE4X5_BMR));
1393: printk("\timr: 0x%08x\n", inl(DE4X5_IMR));
1394: printk("\tomr: 0x%08x\n", inl(DE4X5_OMR));
1395: printk("\tsisr: 0x%08x\n", inl(DE4X5_SISR));
1396: printk("\tsicr: 0x%08x\n", inl(DE4X5_SICR));
1397: printk("\tstrr: 0x%08x\n", inl(DE4X5_STRR));
1398: printk("\tsigr: 0x%08x\n", inl(DE4X5_SIGR));
1399: }
1400:
1401: MOD_INC_USE_COUNT;
1402:
1403: return status;
1404: }
1405:
1406: /*
1407: ** Initialize the DE4X5 operating conditions. NB: a chip problem with the
1408: ** DC21140 requires using perfect filtering mode for that chip. Since I can't
1409: ** see why I'd want > 14 multicast addresses, I have changed all chips to use
1410: ** the perfect filtering mode. Keep the DMA burst length at 8: there seems
1411: ** to be data corruption problems if it is larger (UDP errors seen from a
1412: ** ttcp source).
1413: */
1414: static int
1415: de4x5_init(struct device *dev)
1416: {
1417: /* Lock out other processes whilst setting up the hardware */
1418: test_and_set_bit(0, (void *)&dev->tbusy);
1419:
1420: de4x5_sw_reset(dev);
1421:
1422: /* Autoconfigure the connected port */
1423: autoconf_media(dev);
1424:
1425: return 0;
1426: }
1427:
1428: static int
1429: de4x5_sw_reset(struct device *dev)
1430: {
1431: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1432: u_long iobase = dev->base_addr;
1433: int i, j, status = 0;
1434: s32 bmr, omr;
1435:
1436: /* Select the MII or SRL port now and RESET the MAC */
1437: if (!lp->useSROM) {
1438: if (lp->phy[lp->active].id != 0) {
1439: lp->infoblock_csr6 = OMR_SDP | OMR_PS | OMR_HBD;
1440: } else {
1441: lp->infoblock_csr6 = OMR_SDP | OMR_TTM;
1442: }
1443: de4x5_switch_mac_port(dev);
1444: }
1445:
1446: /*
1447: ** Set the programmable burst length to 8 longwords for all the DC21140
1448: ** Fasternet chips and 4 longwords for all others: DMA errors result
1449: ** without these values. Cache align 16 long.
1450: */
1451: bmr = (lp->chipset==DC21140 ? PBL_8 : PBL_4) | DESC_SKIP_LEN | CACHE_ALIGN;
1452: bmr |= ((lp->chipset & ~0x00ff)==DC2114x ? BMR_RML : 0);
1453: outl(bmr, DE4X5_BMR);
1454:
1455: omr = inl(DE4X5_OMR) & ~OMR_PR; /* Turn off promiscuous mode */
1456: if (lp->chipset == DC21140) {
1457: omr |= (OMR_SDP | OMR_SB);
1458: }
1459: lp->setup_f = PERFECT;
1460: outl(virt_to_bus(lp->rx_ring), DE4X5_RRBA);
1461: outl(virt_to_bus(lp->tx_ring), DE4X5_TRBA);
1462:
1463: lp->rx_new = lp->rx_old = 0;
1464: lp->tx_new = lp->tx_old = 0;
1465:
1466: for (i = 0; i < lp->rxRingSize; i++) {
1467: lp->rx_ring[i].status = cpu_to_le32(R_OWN);
1468: }
1469:
1470: for (i = 0; i < lp->txRingSize; i++) {
1471: lp->tx_ring[i].status = cpu_to_le32(0);
1472: }
1473:
1474: barrier();
1475:
1476: /* Build the setup frame depending on filtering mode */
1477: SetMulticastFilter(dev);
1478:
1479: load_packet(dev, lp->setup_frame, PERFECT_F|TD_SET|SETUP_FRAME_LEN, NULL);
1480: outl(omr|OMR_ST, DE4X5_OMR);
1481:
1482: /* Poll for setup frame completion (adapter interrupts are disabled now) */
1483: sti(); /* Ensure timer interrupts */
1484: for (j=0, i=0;(i<500) && (j==0);i++) { /* Upto 500ms delay */
1485: udelay(1000);
1486: if ((s32)le32_to_cpu(lp->tx_ring[lp->tx_new].status) >= 0) j=1;
1487: }
1488: outl(omr, DE4X5_OMR); /* Stop everything! */
1489:
1490: if (j == 0) {
1491: printk("%s: Setup frame timed out, status %08x\n", dev->name,
1492: inl(DE4X5_STS));
1493: status = -EIO;
1494: }
1495:
1.1.1.2 ! root 1496: lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
1.1 root 1497: lp->tx_old = lp->tx_new;
1498:
1499: return status;
1500: }
1501:
1502: /*
1503: ** Writes a socket buffer address to the next available transmit descriptor.
1504: */
1505: static int
1506: de4x5_queue_pkt(struct sk_buff *skb, struct device *dev)
1507: {
1508: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1509: u_long iobase = dev->base_addr;
1510: int status = 0;
1511:
1512: test_and_set_bit(0, (void*)&dev->tbusy); /* Stop send re-tries */
1513: if (lp->tx_enable == NO) { /* Cannot send for now */
1514: return -1;
1515: }
1516:
1517: /*
1518: ** Clean out the TX ring asynchronously to interrupts - sometimes the
1519: ** interrupts are lost by delayed descriptor status updates relative to
1520: ** the irq assertion, especially with a busy PCI bus.
1521: */
1522: cli();
1523: de4x5_tx(dev);
1524: sti();
1525:
1526: /* Test if cache is already locked - requeue skb if so */
1527: if (test_and_set_bit(0, (void *)&lp->cache.lock) && !lp->interrupt)
1528: return -1;
1529:
1530: /* Transmit descriptor ring full or stale skb */
1531: if (dev->tbusy || lp->tx_skb[lp->tx_new]) {
1532: if (lp->interrupt) {
1533: de4x5_putb_cache(dev, skb); /* Requeue the buffer */
1534: } else {
1535: de4x5_put_cache(dev, skb);
1536: }
1537: if (de4x5_debug & DEBUG_TX) {
1538: printk("%s: transmit busy, lost media or stale skb found:\n STS:%08x\n tbusy:%ld\n IMR:%08x\n OMR:%08x\n Stale skb: %s\n",dev->name, inl(DE4X5_STS), dev->tbusy, inl(DE4X5_IMR), inl(DE4X5_OMR), (lp->tx_skb[lp->tx_new] ? "YES" : "NO"));
1539: }
1540: } else if (skb->len > 0) {
1541: /* If we already have stuff queued locally, use that first */
1542: if (lp->cache.skb && !lp->interrupt) {
1543: de4x5_put_cache(dev, skb);
1544: skb = de4x5_get_cache(dev);
1545: }
1546:
1547: while (skb && !dev->tbusy && !lp->tx_skb[lp->tx_new]) {
1548: cli();
1549: test_and_set_bit(0, (void*)&dev->tbusy);
1550: load_packet(dev, skb->data, TD_IC | TD_LS | TD_FS | skb->len, skb);
1551: #if LINUX_VERSION_CODE >= ((2 << 16) | (1 << 8))
1552: lp->stats.tx_bytes += skb->len;
1553: #endif
1554: outl(POLL_DEMAND, DE4X5_TPD);/* Start the TX */
1555:
1.1.1.2 ! root 1556: lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
1.1 root 1557: dev->trans_start = jiffies;
1558:
1559: if (TX_BUFFS_AVAIL) {
1560: dev->tbusy = 0; /* Another pkt may be queued */
1561: }
1562: skb = de4x5_get_cache(dev);
1563: sti();
1564: }
1565: if (skb) de4x5_putb_cache(dev, skb);
1566: }
1567:
1568: lp->cache.lock = 0;
1569:
1570: return status;
1571: }
1572:
1573: /*
1574: ** The DE4X5 interrupt handler.
1575: **
1576: ** I/O Read/Writes through intermediate PCI bridges are never 'posted',
1577: ** so that the asserted interrupt always has some real data to work with -
1578: ** if these I/O accesses are ever changed to memory accesses, ensure the
1579: ** STS write is read immediately to complete the transaction if the adapter
1580: ** is not on bus 0. Lost interrupts can still occur when the PCI bus load
1581: ** is high and descriptor status bits cannot be set before the associated
1582: ** interrupt is asserted and this routine entered.
1583: */
1584: static void
1585: de4x5_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1586: {
1587: struct device *dev = (struct device *)dev_id;
1588: struct de4x5_private *lp;
1589: s32 imr, omr, sts, limit;
1590: u_long iobase;
1591:
1592: if (dev == NULL) {
1593: printk ("de4x5_interrupt(): irq %d for unknown device.\n", irq);
1594: return;
1595: }
1596: lp = (struct de4x5_private *)dev->priv;
1597: iobase = dev->base_addr;
1598:
1599: DISABLE_IRQs; /* Ensure non re-entrancy */
1600:
1601: if (test_and_set_bit(MASK_INTERRUPTS, (void*) &lp->interrupt))
1602: printk("%s: Re-entering the interrupt handler.\n", dev->name);
1603:
1604: #if LINUX_VERSION_CODE >= ((2 << 16) | (1 << 8))
1605: synchronize_irq();
1606: #endif
1607:
1608: for (limit=0; limit<8; limit++) {
1609: sts = inl(DE4X5_STS); /* Read IRQ status */
1610: outl(sts, DE4X5_STS); /* Reset the board interrupts */
1611:
1612: if (!(sts & lp->irq_mask)) break;/* All done */
1613:
1614: if (sts & (STS_RI | STS_RU)) /* Rx interrupt (packet[s] arrived) */
1615: de4x5_rx(dev);
1616:
1617: if (sts & (STS_TI | STS_TU)) /* Tx interrupt (packet sent) */
1618: de4x5_tx(dev);
1619:
1620: if (sts & STS_LNF) { /* TP Link has failed */
1621: lp->irq_mask &= ~IMR_LFM;
1622: }
1623:
1624: if (sts & STS_UNF) { /* Transmit underrun */
1625: de4x5_txur(dev);
1626: }
1627:
1628: if (sts & STS_SE) { /* Bus Error */
1629: STOP_DE4X5;
1630: printk("%s: Fatal bus error occurred, sts=%#8x, device stopped.\n",
1631: dev->name, sts);
1632: return;
1633: }
1634: }
1635:
1636: /* Load the TX ring with any locally stored packets */
1637: if (!test_and_set_bit(0, (void *)&lp->cache.lock)) {
1638: while (lp->cache.skb && !dev->tbusy && lp->tx_enable) {
1639: de4x5_queue_pkt(de4x5_get_cache(dev), dev);
1640: }
1641: lp->cache.lock = 0;
1642: }
1643:
1644: lp->interrupt = UNMASK_INTERRUPTS;
1645: ENABLE_IRQs;
1646:
1647: return;
1648: }
1649:
1650: static int
1651: de4x5_rx(struct device *dev)
1652: {
1653: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1654: u_long iobase = dev->base_addr;
1655: int entry;
1656: s32 status;
1657:
1658: for (entry=lp->rx_new; (s32)le32_to_cpu(lp->rx_ring[entry].status)>=0;
1659: entry=lp->rx_new) {
1660: status = (s32)le32_to_cpu(lp->rx_ring[entry].status);
1661:
1662: if (lp->rx_ovf) {
1663: if (inl(DE4X5_MFC) & MFC_FOCM) {
1664: de4x5_rx_ovfc(dev);
1665: break;
1666: }
1667: }
1668:
1669: if (status & RD_FS) { /* Remember the start of frame */
1670: lp->rx_old = entry;
1671: }
1672:
1673: if (status & RD_LS) { /* Valid frame status */
1674: if (lp->tx_enable) lp->linkOK++;
1675: if (status & RD_ES) { /* There was an error. */
1676: lp->stats.rx_errors++; /* Update the error stats. */
1677: if (status & (RD_RF | RD_TL)) lp->stats.rx_frame_errors++;
1678: if (status & RD_CE) lp->stats.rx_crc_errors++;
1679: if (status & RD_OF) lp->stats.rx_fifo_errors++;
1680: if (status & RD_TL) lp->stats.rx_length_errors++;
1681: if (status & RD_RF) lp->pktStats.rx_runt_frames++;
1682: if (status & RD_CS) lp->pktStats.rx_collision++;
1683: if (status & RD_DB) lp->pktStats.rx_dribble++;
1684: if (status & RD_OF) lp->pktStats.rx_overflow++;
1685: } else { /* A valid frame received */
1686: struct sk_buff *skb;
1687: short pkt_len = (short)(le32_to_cpu(lp->rx_ring[entry].status)
1688: >> 16) - 4;
1689:
1690: if ((skb = de4x5_alloc_rx_buff(dev, entry, pkt_len)) == NULL) {
1691: printk("%s: Insufficient memory; nuking packet.\n",
1692: dev->name);
1693: lp->stats.rx_dropped++;
1694: } else {
1695: de4x5_dbg_rx(skb, pkt_len);
1696:
1697: /* Push up the protocol stack */
1698: skb->protocol=eth_type_trans(skb,dev);
1699: netif_rx(skb);
1700:
1701: /* Update stats */
1702: lp->stats.rx_packets++;
1703: #if LINUX_VERSION_CODE >= ((2 << 16) | (1 << 8))
1704: lp->stats.rx_bytes += pkt_len;
1705: #endif
1706: de4x5_local_stats(dev, skb->data, pkt_len);
1707: }
1708: }
1709:
1710: /* Change buffer ownership for this frame, back to the adapter */
1.1.1.2 ! root 1711: for (;lp->rx_old!=entry;lp->rx_old=(lp->rx_old+1)%lp->rxRingSize) {
1.1 root 1712: lp->rx_ring[lp->rx_old].status = cpu_to_le32(R_OWN);
1713: barrier();
1714: }
1715: lp->rx_ring[entry].status = cpu_to_le32(R_OWN);
1716: barrier();
1717: }
1718:
1719: /*
1720: ** Update entry information
1721: */
1.1.1.2 ! root 1722: lp->rx_new = (lp->rx_new + 1) % lp->rxRingSize;
1.1 root 1723: }
1724:
1725: return 0;
1726: }
1727:
1728: /*
1729: ** Buffer sent - check for TX buffer errors.
1730: */
1731: static int
1732: de4x5_tx(struct device *dev)
1733: {
1734: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1735: u_long iobase = dev->base_addr;
1736: int entry;
1737: s32 status;
1738:
1739: for (entry = lp->tx_old; entry != lp->tx_new; entry = lp->tx_old) {
1740: status = (s32)le32_to_cpu(lp->tx_ring[entry].status);
1741: if (status < 0) { /* Buffer not sent yet */
1742: break;
1743: } else if (status != 0x7fffffff) { /* Not setup frame */
1744: if (status & TD_ES) { /* An error happened */
1745: lp->stats.tx_errors++;
1746: if (status & TD_NC) lp->stats.tx_carrier_errors++;
1747: if (status & TD_LC) lp->stats.tx_window_errors++;
1748: if (status & TD_UF) lp->stats.tx_fifo_errors++;
1749: if (status & TD_EC) lp->pktStats.excessive_collisions++;
1750: if (status & TD_DE) lp->stats.tx_aborted_errors++;
1751:
1752: if (TX_PKT_PENDING) {
1753: outl(POLL_DEMAND, DE4X5_TPD);/* Restart a stalled TX */
1754: }
1755: } else { /* Packet sent */
1756: lp->stats.tx_packets++;
1757: if (lp->tx_enable) lp->linkOK++;
1758: }
1759: /* Update the collision counter */
1760: lp->stats.collisions += ((status & TD_EC) ? 16 :
1761: ((status & TD_CC) >> 3));
1762:
1763: /* Free the buffer. */
1764: if (lp->tx_skb[entry] != NULL) {
1765: dev_kfree_skb(lp->tx_skb[entry], FREE_WRITE);
1766: lp->tx_skb[entry] = NULL;
1767: }
1768: }
1769:
1770: /* Update all the pointers */
1.1.1.2 ! root 1771: lp->tx_old = (lp->tx_old + 1) % lp->txRingSize;
1.1 root 1772: }
1773:
1774: if (TX_BUFFS_AVAIL && dev->tbusy) { /* Any resources available? */
1775: dev->tbusy = 0; /* Clear TX busy flag */
1776: if (lp->interrupt) mark_bh(NET_BH);
1777: }
1778:
1779: return 0;
1780: }
1781:
1782: static int
1783: de4x5_ast(struct device *dev)
1784: {
1785: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1786: int next_tick = DE4X5_AUTOSENSE_MS;
1787:
1788: disable_ast(dev);
1789:
1790: if (lp->useSROM) {
1791: next_tick = srom_autoconf(dev);
1792: } else if (lp->chipset == DC21140) {
1793: next_tick = dc21140m_autoconf(dev);
1794: } else if (lp->chipset == DC21041) {
1795: next_tick = dc21041_autoconf(dev);
1796: } else if (lp->chipset == DC21040) {
1797: next_tick = dc21040_autoconf(dev);
1798: }
1799: lp->linkOK = 0;
1800: enable_ast(dev, next_tick);
1801:
1802: return 0;
1803: }
1804:
1805: static int
1806: de4x5_txur(struct device *dev)
1807: {
1808: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1809: u_long iobase = dev->base_addr;
1810: int omr;
1811:
1812: omr = inl(DE4X5_OMR);
1813: if (!(omr & OMR_SF) || (lp->chipset==DC21041) || (lp->chipset==DC21040)) {
1814: omr &= ~(OMR_ST|OMR_SR);
1815: outl(omr, DE4X5_OMR);
1816: while (inl(DE4X5_STS) & STS_TS);
1817: if ((omr & OMR_TR) < OMR_TR) {
1818: omr += 0x4000;
1819: } else {
1820: omr |= OMR_SF;
1821: }
1822: outl(omr | OMR_ST | OMR_SR, DE4X5_OMR);
1823: }
1824:
1825: return 0;
1826: }
1827:
1828: static int
1829: de4x5_rx_ovfc(struct device *dev)
1830: {
1831: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1832: u_long iobase = dev->base_addr;
1833: int omr;
1834:
1835: omr = inl(DE4X5_OMR);
1836: outl(omr & ~OMR_SR, DE4X5_OMR);
1837: while (inl(DE4X5_STS) & STS_RS);
1838:
1839: for (; (s32)le32_to_cpu(lp->rx_ring[lp->rx_new].status)>=0;) {
1840: lp->rx_ring[lp->rx_new].status = cpu_to_le32(R_OWN);
1.1.1.2 ! root 1841: lp->rx_new = (lp->rx_new + 1) % lp->rxRingSize;
1.1 root 1842: }
1843:
1844: outl(omr, DE4X5_OMR);
1845:
1846: return 0;
1847: }
1848:
1849: static int
1850: de4x5_close(struct device *dev)
1851: {
1852: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1853: u_long iobase = dev->base_addr;
1854: s32 imr, omr;
1855:
1856: disable_ast(dev);
1857: dev->start = 0;
1858: dev->tbusy = 1;
1859:
1860: if (de4x5_debug & DEBUG_CLOSE) {
1861: printk("%s: Shutting down ethercard, status was %8.8x.\n",
1862: dev->name, inl(DE4X5_STS));
1863: }
1864:
1865: /*
1866: ** We stop the DE4X5 here... mask interrupts and stop TX & RX
1867: */
1868: DISABLE_IRQs;
1869: STOP_DE4X5;
1870:
1871: /* Free the associated irq */
1872: free_irq(dev->irq, dev);
1873: lp->state = CLOSED;
1874:
1875: /* Free any socket buffers */
1876: de4x5_free_rx_buffs(dev);
1877: de4x5_free_tx_buffs(dev);
1878:
1879: MOD_DEC_USE_COUNT;
1880:
1881: /* Put the adapter to sleep to save power */
1882: yawn(dev, SLEEP);
1883:
1884: return 0;
1885: }
1886:
1887: static struct net_device_stats *
1888: de4x5_get_stats(struct device *dev)
1889: {
1890: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1891: u_long iobase = dev->base_addr;
1892:
1893: lp->stats.rx_missed_errors = (int)(inl(DE4X5_MFC) & (MFC_OVFL | MFC_CNTR));
1894:
1895: return &lp->stats;
1896: }
1897:
1898: static void
1899: de4x5_local_stats(struct device *dev, char *buf, int pkt_len)
1900: {
1901: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1902: int i;
1903:
1904: for (i=1; i<DE4X5_PKT_STAT_SZ-1; i++) {
1905: if (pkt_len < (i*DE4X5_PKT_BIN_SZ)) {
1906: lp->pktStats.bins[i]++;
1907: i = DE4X5_PKT_STAT_SZ;
1908: }
1909: }
1910: if (buf[0] & 0x01) { /* Multicast/Broadcast */
1911: if ((*(s32 *)&buf[0] == -1) && (*(s16 *)&buf[4] == -1)) {
1912: lp->pktStats.broadcast++;
1913: } else {
1914: lp->pktStats.multicast++;
1915: }
1916: } else if ((*(s32 *)&buf[0] == *(s32 *)&dev->dev_addr[0]) &&
1917: (*(s16 *)&buf[4] == *(s16 *)&dev->dev_addr[4])) {
1918: lp->pktStats.unicast++;
1919: }
1920:
1921: lp->pktStats.bins[0]++; /* Duplicates stats.rx_packets */
1922: if (lp->pktStats.bins[0] == 0) { /* Reset counters */
1923: memset((char *)&lp->pktStats, 0, sizeof(lp->pktStats));
1924: }
1925:
1926: return;
1927: }
1928:
1929: static void
1930: load_packet(struct device *dev, char *buf, u32 flags, struct sk_buff *skb)
1931: {
1932: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1933:
1934: lp->tx_ring[lp->tx_new].buf = cpu_to_le32(virt_to_bus(buf));
1935: lp->tx_ring[lp->tx_new].des1 &= cpu_to_le32(TD_TER);
1936: lp->tx_ring[lp->tx_new].des1 |= cpu_to_le32(flags);
1937: lp->tx_skb[lp->tx_new] = skb;
1938: barrier();
1939: lp->tx_ring[lp->tx_new].status = cpu_to_le32(T_OWN);
1940: barrier();
1941:
1942: return;
1943: }
1944:
1945: /*
1946: ** Set or clear the multicast filter for this adaptor.
1947: */
1948: static void
1949: set_multicast_list(struct device *dev)
1950: {
1951: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1952: u_long iobase = dev->base_addr;
1953:
1954: /* First, double check that the adapter is open */
1955: if (lp->state == OPEN) {
1956: if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
1957: u32 omr;
1958: omr = inl(DE4X5_OMR);
1959: omr |= OMR_PR;
1960: outl(omr, DE4X5_OMR);
1961: } else {
1962: SetMulticastFilter(dev);
1963: load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
1964: SETUP_FRAME_LEN, NULL);
1965:
1.1.1.2 ! root 1966: lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
1.1 root 1967: outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
1968: dev->trans_start = jiffies;
1969: }
1970: }
1971:
1972: return;
1973: }
1974:
1975: /*
1976: ** Calculate the hash code and update the logical address filter
1977: ** from a list of ethernet multicast addresses.
1978: ** Little endian crc one liner from Matt Thomas, DEC.
1979: */
1980: static void
1981: SetMulticastFilter(struct device *dev)
1982: {
1983: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1984: struct dev_mc_list *dmi=dev->mc_list;
1985: u_long iobase = dev->base_addr;
1986: int i, j, bit, byte;
1987: u16 hashcode;
1988: u32 omr, crc, poly = CRC_POLYNOMIAL_LE;
1989: char *pa;
1990: unsigned char *addrs;
1991:
1992: omr = inl(DE4X5_OMR);
1993: omr &= ~(OMR_PR | OMR_PM);
1994: pa = build_setup_frame(dev, ALL); /* Build the basic frame */
1995:
1996: if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 14)) {
1997: omr |= OMR_PM; /* Pass all multicasts */
1998: } else if (lp->setup_f == HASH_PERF) { /* Hash Filtering */
1999: for (i=0;i<dev->mc_count;i++) { /* for each address in the list */
2000: addrs=dmi->dmi_addr;
2001: dmi=dmi->next;
2002: if ((*addrs & 0x01) == 1) { /* multicast address? */
2003: crc = 0xffffffff; /* init CRC for each address */
2004: for (byte=0;byte<ETH_ALEN;byte++) {/* for each address byte */
2005: /* process each address bit */
2006: for (bit = *addrs++,j=0;j<8;j++, bit>>=1) {
2007: crc = (crc >> 1) ^ (((crc ^ bit) & 0x01) ? poly : 0);
2008: }
2009: }
2010: hashcode = crc & HASH_BITS; /* hashcode is 9 LSb of CRC */
2011:
2012: byte = hashcode >> 3; /* bit[3-8] -> byte in filter */
2013: bit = 1 << (hashcode & 0x07);/* bit[0-2] -> bit in byte */
2014:
2015: byte <<= 1; /* calc offset into setup frame */
2016: if (byte & 0x02) {
2017: byte -= 1;
2018: }
2019: lp->setup_frame[byte] |= bit;
2020: }
2021: }
2022: } else { /* Perfect filtering */
2023: for (j=0; j<dev->mc_count; j++) {
2024: addrs=dmi->dmi_addr;
2025: dmi=dmi->next;
2026: for (i=0; i<ETH_ALEN; i++) {
2027: *(pa + (i&1)) = *addrs++;
2028: if (i & 0x01) pa += 4;
2029: }
2030: }
2031: }
2032: outl(omr, DE4X5_OMR);
2033:
2034: return;
2035: }
2036:
2037: #if !defined(__sparc_v9__) && !defined(__powerpc__) && !defined(__alpha__)
2038: /*
2039: ** EISA bus I/O device probe. Probe from slot 1 since slot 0 is usually
2040: ** the motherboard. Upto 15 EISA devices are supported.
2041: */
2042: __initfunc(static void
2043: eisa_probe(struct device *dev, u_long ioaddr))
2044: {
2045: int i, maxSlots, status, device;
2046: u_char irq;
2047: u_short vendor;
2048: u32 cfid;
2049: u_long iobase;
2050: struct bus_type *lp = &bus;
2051: char name[DE4X5_STRLEN];
2052:
2053: if (lastEISA == MAX_EISA_SLOTS) return;/* No more EISA devices to search */
2054:
2055: lp->bus = EISA;
2056:
2057: if (ioaddr == 0) { /* Autoprobing */
2058: iobase = EISA_SLOT_INC; /* Get the first slot address */
2059: i = 1;
2060: maxSlots = MAX_EISA_SLOTS;
2061: } else { /* Probe a specific location */
2062: iobase = ioaddr;
2063: i = (ioaddr >> 12);
2064: maxSlots = i + 1;
2065: }
2066:
2067: for (status = -ENODEV; (i<maxSlots) && (dev!=NULL); i++, iobase+=EISA_SLOT_INC) {
2068: if (EISA_signature(name, EISA_ID)) {
2069: cfid = (u32) inl(PCI_CFID);
2070: cfrv = (u_short) inl(PCI_CFRV);
2071: device = (cfid >> 8) & 0x00ffff00;
2072: vendor = (u_short) cfid;
2073:
2074: /* Read the EISA Configuration Registers */
2075: irq = inb(EISA_REG0);
2076: irq = de4x5_irq[(irq >> 1) & 0x03];
2077:
2078: if (is_DC2114x) device |= (cfrv & CFRV_RN);
2079: lp->chipset = device;
2080:
2081: /* Write the PCI Configuration Registers */
2082: outl(PCI_COMMAND_IO | PCI_COMMAND_MASTER, PCI_CFCS);
2083: outl(0x00006000, PCI_CFLT);
2084: outl(iobase, PCI_CBIO);
2085:
2086: DevicePresent(EISA_APROM);
2087: if (check_region(iobase, DE4X5_EISA_TOTAL_SIZE) == 0) {
2088: dev->irq = irq;
2089: if ((status = de4x5_hw_init(dev, iobase)) == 0) {
2090: num_de4x5s++;
2091: if (loading_module) link_modules(lastModule, dev);
2092: lastEISA = i;
2093: return;
2094: }
2095: } else if (ioaddr != 0) {
2096: printk("%s: region already allocated at 0x%04lx.\n", dev->name,iobase);
2097: }
2098: }
2099: }
2100:
2101: if (ioaddr == 0) lastEISA = i;
2102:
2103: return;
2104: }
2105: #endif /* !(__sparc_v9__) && !(__powerpc__) && !defined(__alpha__)*/
2106:
2107: /*
2108: ** PCI bus I/O device probe
2109: ** NB: PCI I/O accesses and Bus Mastering are enabled by the PCI BIOS, not
2110: ** the driver. Some PCI BIOS's, pre V2.1, need the slot + features to be
2111: ** enabled by the user first in the set up utility. Hence we just check for
2112: ** enabled features and silently ignore the card if they're not.
2113: **
2114: ** STOP PRESS: Some BIOS's __require__ the driver to enable the bus mastering
2115: ** bit. Here, check for I/O accesses and then set BM. If you put the card in
2116: ** a non BM slot, you're on your own (and complain to the PC vendor that your
2117: ** PC doesn't conform to the PCI standard)!
2118: */
2119: #define PCI_DEVICE (dev_num << 3)
2120: #define PCI_LAST_DEV 32
2121:
2122: __initfunc(static void
2123: pci_probe(struct device *dev, u_long ioaddr))
2124: {
2125: u_char pb, pbus, dev_num, dnum, dev_fn, timer, tirq;
2126: u_short dev_id, vendor, index, status;
2127: u_int tmp, irq = 0, device, class = DE4X5_CLASS_CODE;
2128: u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2129: struct bus_type *lp = &bus;
2130:
2131: if (lastPCI == NO_MORE_PCI) return;
2132:
2133: if (!pcibios_present()) {
2134: lastPCI = NO_MORE_PCI;
2135: return; /* No PCI bus in this machine! */
2136: }
2137:
2138: lp->bus = PCI;
2139: lp->bus_num = 0;
2140:
2141: if ((ioaddr < 0x1000) && loading_module) {
2142: pbus = (u_short)(ioaddr >> 8);
2143: dnum = (u_short)(ioaddr & 0xff);
2144: } else {
2145: pbus = 0;
2146: dnum = 0;
2147: }
2148:
2149: for (index=lastPCI+1;
1.1.1.2 ! root 2150: (pcibios_find_class(class, index, &pb, &dev_fn)== PCIBIOS_SUCCESSFUL);
1.1 root 2151: index++) {
2152: dev_num = PCI_SLOT(dev_fn);
2153: if ((!pbus && !dnum) || ((pbus == pb) && (dnum == dev_num))) {
2154: #ifdef __sparc_v9__
2155: struct pci_dev *pdev;
2156: for (pdev = pci_devices; pdev; pdev = pdev->next) {
2157: if ((pdev->bus->number==pb) && (pdev->devfn==dev_fn)) break;
2158: }
2159: #endif
2160: device = 0;
2161: pcibios_read_config_word(pb, PCI_DEVICE, PCI_VENDOR_ID, &vendor);
2162: pcibios_read_config_word(pb, PCI_DEVICE, PCI_DEVICE_ID, &dev_id);
2163: device = dev_id;
2164: device <<= 8;
2165: if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x)) {
2166: continue;
2167: }
2168:
2169: /* Search for an SROM on this bus */
2170: if (lp->bus_num != pb) {
2171: lp->bus_num = pb;
2172: srom_search(index);
2173: }
2174:
2175: /* Get the chip configuration revision register */
2176: pcibios_read_config_dword(pb, PCI_DEVICE, PCI_REVISION_ID, &cfrv);
2177:
2178: /* Set the device number information */
2179: lp->device = dev_num;
2180: lp->bus_num = pb;
2181:
2182: /* Set the chipset information */
2183: if (is_DC2114x) device |= (cfrv & CFRV_RN);
2184: lp->chipset = device;
2185:
2186: /* Get the board I/O address (64 bits on sparc64) */
2187: #ifndef __sparc_v9__
2188: pcibios_read_config_dword(pb, PCI_DEVICE, PCI_BASE_ADDRESS_0, &tmp);
2189: iobase = tmp;
2190: #else
2191: iobase = pdev->base_address[0];
2192: #endif
2193: iobase &= CBIO_MASK;
2194:
2195: /* Fetch the IRQ to be used */
2196: #ifndef __sparc_v9__
2197: pcibios_read_config_byte(pb, PCI_DEVICE, PCI_INTERRUPT_LINE, &tirq);
2198: irq = tirq;
2199: #else
2200: irq = pdev->irq;
2201: #endif
2202: if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) continue;
2203:
2204: /* Check if I/O accesses and Bus Mastering are enabled */
2205: pcibios_read_config_word(pb, PCI_DEVICE, PCI_COMMAND, &status);
2206: #ifdef __powerpc__
2207: if (!(status & PCI_COMMAND_IO)) {
2208: status |= PCI_COMMAND_IO;
2209: pcibios_write_config_word(pb, PCI_DEVICE, PCI_COMMAND, status);
2210: pcibios_read_config_word(pb, PCI_DEVICE, PCI_COMMAND, &status);
2211: }
2212: #endif /* __powerpc__ */
2213: if (!(status & PCI_COMMAND_IO)) continue;
2214:
2215: if (!(status & PCI_COMMAND_MASTER)) {
2216: status |= PCI_COMMAND_MASTER;
2217: pcibios_write_config_word(pb, PCI_DEVICE, PCI_COMMAND, status);
2218: pcibios_read_config_word(pb, PCI_DEVICE, PCI_COMMAND, &status);
2219: }
2220: if (!(status & PCI_COMMAND_MASTER)) continue;
2221:
2222: /* Check the latency timer for values >= 0x60 */
2223: pcibios_read_config_byte(pb, PCI_DEVICE, PCI_LATENCY_TIMER, &timer);
2224: if (timer < 0x60) {
2225: pcibios_write_config_byte(pb, PCI_DEVICE, PCI_LATENCY_TIMER, 0x60);
2226: }
2227:
2228: DevicePresent(DE4X5_APROM);
2229: if (check_region(iobase, DE4X5_PCI_TOTAL_SIZE) == 0) {
2230: dev->irq = irq;
2231: if ((status = de4x5_hw_init(dev, iobase)) == 0) {
2232: num_de4x5s++;
2233: lastPCI = index;
2234: if (loading_module) link_modules(lastModule, dev);
2235: return;
2236: }
2237: } else if (ioaddr != 0) {
2238: printk("%s: region already allocated at 0x%04lx.\n", dev->name,
2239: iobase);
2240: }
2241: }
2242: }
2243:
2244: lastPCI = NO_MORE_PCI;
2245:
2246: return;
2247: }
2248:
2249: /*
2250: ** This function searches the current bus (which is >0) for a DECchip with an
2251: ** SROM, so that in multiport cards that have one SROM shared between multiple
2252: ** DECchips, we can find the base SROM irrespective of the BIOS scan direction.
2253: ** For single port cards this is a time waster...
2254: */
2255: __initfunc(static void
2256: srom_search(int index))
2257: {
2258: u_char pb, dev_fn, tirq;
2259: u_short dev_id, dev_num, vendor, status;
2260: u_int tmp, irq = 0, device, class = DE4X5_CLASS_CODE;
2261: u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2262: int i, j;
2263: struct bus_type *lp = &bus;
2264:
2265: for (;
2266: (pcibios_find_class(class, index, &pb, &dev_fn)!= PCIBIOS_DEVICE_NOT_FOUND);
2267: index++) {
2268:
2269: if (lp->bus_num != pb) return;
2270: dev_num = PCI_SLOT(dev_fn);
2271: #ifdef __sparc_v9__
2272: struct pci_dev *pdev;
2273: for (pdev = pci_devices; pdev; pdev = pdev->next) {
2274: if ((pdev->bus->number == pb) && (pdev->devfn == dev_fn)) break;
2275: }
2276: #endif
2277: device = 0;
2278: pcibios_read_config_word(pb, PCI_DEVICE, PCI_VENDOR_ID, &vendor);
2279: pcibios_read_config_word(pb, PCI_DEVICE, PCI_DEVICE_ID, &dev_id);
2280: device = dev_id;
2281: device <<= 8;
2282: if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x)) {
2283: continue;
2284: }
2285:
2286: /* Get the chip configuration revision register */
2287: pcibios_read_config_dword(pb, PCI_DEVICE, PCI_REVISION_ID, &cfrv);
2288:
2289: /* Set the device number information */
2290: lp->device = dev_num;
2291: lp->bus_num = pb;
2292:
2293: /* Set the chipset information */
2294: if (is_DC2114x) device |= (cfrv & CFRV_RN);
2295: lp->chipset = device;
2296:
2297: /* Get the board I/O address (64 bits on sparc64) */
2298: #ifndef __sparc_v9__
2299: pcibios_read_config_dword(pb, PCI_DEVICE, PCI_BASE_ADDRESS_0, &tmp);
2300: iobase = tmp;
2301: #else
2302: iobase = pdev->base_address[0];
2303: #endif
2304: iobase &= CBIO_MASK;
2305:
2306: /* Fetch the IRQ to be used */
2307: #ifndef __sparc_v9__
2308: pcibios_read_config_byte(pb, PCI_DEVICE, PCI_INTERRUPT_LINE, &tirq);
2309: irq = tirq;
2310: #else
2311: irq = pdev->irq;
2312: #endif
2313: if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) continue;
2314:
2315: /* Check if I/O accesses are enabled */
2316: pcibios_read_config_word(pb, PCI_DEVICE, PCI_COMMAND, &status);
2317: if (!(status & PCI_COMMAND_IO)) continue;
2318:
2319: /* Search for a valid SROM attached to this DECchip */
2320: DevicePresent(DE4X5_APROM);
2321: for (j=0, i=0; i<ETH_ALEN; i++) {
2322: j += (u_char) *((u_char *)&lp->srom + SROM_HWADD + i);
2323: }
2324: if ((j != 0) && (j != 0x5fa)) {
2325: last.chipset = device;
2326: last.bus = pb;
2327: last.irq = irq;
2328: for (i=0; i<ETH_ALEN; i++) {
2329: last.addr[i] = (u_char)*((u_char *)&lp->srom + SROM_HWADD + i);
2330: }
2331: return;
2332: }
2333: }
2334:
2335: return;
2336: }
2337:
2338: __initfunc(static void
2339: link_modules(struct device *dev, struct device *tmp))
2340: {
2341: struct device *p=dev;
2342:
2343: if (p) {
2344: while (((struct de4x5_private *)(p->priv))->next_module) {
2345: p = ((struct de4x5_private *)(p->priv))->next_module;
2346: }
2347:
2348: if (dev != tmp) {
2349: ((struct de4x5_private *)(p->priv))->next_module = tmp;
2350: } else {
2351: ((struct de4x5_private *)(p->priv))->next_module = NULL;
2352: }
2353: }
2354:
2355: return;
2356: }
2357:
2358: /*
2359: ** Auto configure the media here rather than setting the port at compile
2360: ** time. This routine is called by de4x5_init() and when a loss of media is
2361: ** detected (excessive collisions, loss of carrier, no carrier or link fail
2362: ** [TP] or no recent receive activity) to check whether the user has been
2363: ** sneaky and changed the port on us.
2364: */
2365: static int
2366: autoconf_media(struct device *dev)
2367: {
2368: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2369: u_long iobase = dev->base_addr;
2370: int next_tick = DE4X5_AUTOSENSE_MS;
2371:
2372: lp->linkOK = 0;
2373: lp->c_media = AUTO; /* Bogus last media */
2374: disable_ast(dev);
2375: inl(DE4X5_MFC); /* Zero the lost frames counter */
2376: lp->media = INIT;
2377: lp->tcount = 0;
2378:
2379: if (lp->useSROM) {
2380: next_tick = srom_autoconf(dev);
2381: } else if (lp->chipset == DC21040) {
2382: next_tick = dc21040_autoconf(dev);
2383: } else if (lp->chipset == DC21041) {
2384: next_tick = dc21041_autoconf(dev);
2385: } else if (lp->chipset == DC21140) {
2386: next_tick = dc21140m_autoconf(dev);
2387: }
2388:
2389: enable_ast(dev, next_tick);
2390:
2391: return (lp->media);
2392: }
2393:
2394: /*
2395: ** Autoconfigure the media when using the DC21040. AUI cannot be distinguished
2396: ** from BNC as the port has a jumper to set thick or thin wire. When set for
2397: ** BNC, the BNC port will indicate activity if it's not terminated correctly.
2398: ** The only way to test for that is to place a loopback packet onto the
2399: ** network and watch for errors. Since we're messing with the interrupt mask
2400: ** register, disable the board interrupts and do not allow any more packets to
2401: ** be queued to the hardware. Re-enable everything only when the media is
2402: ** found.
2403: ** I may have to "age out" locally queued packets so that the higher layer
2404: ** timeouts don't effectively duplicate packets on the network.
2405: */
2406: static int
2407: dc21040_autoconf(struct device *dev)
2408: {
2409: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2410: u_long iobase = dev->base_addr;
2411: int next_tick = DE4X5_AUTOSENSE_MS;
2412: s32 imr;
2413:
2414: switch (lp->media) {
2415: case INIT:
2416: DISABLE_IRQs;
2417: lp->tx_enable = NO;
2418: lp->timeout = -1;
2419: de4x5_save_skbs(dev);
2420: if ((lp->autosense == AUTO) || (lp->autosense == TP)) {
2421: lp->media = TP;
2422: } else if ((lp->autosense == BNC) || (lp->autosense == AUI) || (lp->autosense == BNC_AUI)) {
2423: lp->media = BNC_AUI;
2424: } else if (lp->autosense == EXT_SIA) {
2425: lp->media = EXT_SIA;
2426: } else {
2427: lp->media = NC;
2428: }
2429: lp->local_state = 0;
2430: next_tick = dc21040_autoconf(dev);
2431: break;
2432:
2433: case TP:
2434: next_tick = dc21040_state(dev, 0x8f01, 0xffff, 0x0000, 3000, BNC_AUI,
2435: TP_SUSPECT, test_tp);
2436: break;
2437:
2438: case TP_SUSPECT:
2439: next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21040_autoconf);
2440: break;
2441:
2442: case BNC:
2443: case AUI:
2444: case BNC_AUI:
2445: next_tick = dc21040_state(dev, 0x8f09, 0x0705, 0x0006, 3000, EXT_SIA,
2446: BNC_AUI_SUSPECT, ping_media);
2447: break;
2448:
2449: case BNC_AUI_SUSPECT:
2450: next_tick = de4x5_suspect_state(dev, 1000, BNC_AUI, ping_media, dc21040_autoconf);
2451: break;
2452:
2453: case EXT_SIA:
2454: next_tick = dc21040_state(dev, 0x3041, 0x0000, 0x0006, 3000,
2455: NC, EXT_SIA_SUSPECT, ping_media);
2456: break;
2457:
2458: case EXT_SIA_SUSPECT:
2459: next_tick = de4x5_suspect_state(dev, 1000, EXT_SIA, ping_media, dc21040_autoconf);
2460: break;
2461:
2462: case NC:
2463: /* default to TP for all */
2464: reset_init_sia(dev, 0x8f01, 0xffff, 0x0000);
2465: if (lp->media != lp->c_media) {
2466: de4x5_dbg_media(dev);
2467: lp->c_media = lp->media;
2468: }
2469: lp->media = INIT;
2470: lp->tx_enable = NO;
2471: break;
2472: }
2473:
2474: return next_tick;
2475: }
2476:
2477: static int
2478: dc21040_state(struct device *dev, int csr13, int csr14, int csr15, int timeout,
2479: int next_state, int suspect_state,
2480: int (*fn)(struct device *, int))
2481: {
2482: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2483: int next_tick = DE4X5_AUTOSENSE_MS;
2484: int linkBad;
2485:
2486: switch (lp->local_state) {
2487: case 0:
2488: reset_init_sia(dev, csr13, csr14, csr15);
2489: lp->local_state++;
2490: next_tick = 500;
2491: break;
2492:
2493: case 1:
2494: if (!lp->tx_enable) {
2495: linkBad = fn(dev, timeout);
2496: if (linkBad < 0) {
2497: next_tick = linkBad & ~TIMER_CB;
2498: } else {
2499: if (linkBad && (lp->autosense == AUTO)) {
2500: lp->local_state = 0;
2501: lp->media = next_state;
2502: } else {
2503: de4x5_init_connection(dev);
2504: }
2505: }
2506: } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2507: lp->media = suspect_state;
2508: next_tick = 3000;
2509: }
2510: break;
2511: }
2512:
2513: return next_tick;
2514: }
2515:
2516: static int
2517: de4x5_suspect_state(struct device *dev, int timeout, int prev_state,
2518: int (*fn)(struct device *, int),
2519: int (*asfn)(struct device *))
2520: {
2521: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2522: int next_tick = DE4X5_AUTOSENSE_MS;
2523: int linkBad;
2524:
2525: switch (lp->local_state) {
2526: case 1:
2527: if (lp->linkOK) {
2528: lp->media = prev_state;
2529: } else {
2530: lp->local_state++;
2531: next_tick = asfn(dev);
2532: }
2533: break;
2534:
2535: case 2:
2536: linkBad = fn(dev, timeout);
2537: if (linkBad < 0) {
2538: next_tick = linkBad & ~TIMER_CB;
2539: } else if (!linkBad) {
2540: lp->local_state--;
2541: lp->media = prev_state;
2542: } else {
2543: lp->media = INIT;
2544: lp->tcount++;
2545: }
2546: }
2547:
2548: return next_tick;
2549: }
2550:
2551: /*
2552: ** Autoconfigure the media when using the DC21041. AUI needs to be tested
2553: ** before BNC, because the BNC port will indicate activity if it's not
2554: ** terminated correctly. The only way to test for that is to place a loopback
2555: ** packet onto the network and watch for errors. Since we're messing with
2556: ** the interrupt mask register, disable the board interrupts and do not allow
2557: ** any more packets to be queued to the hardware. Re-enable everything only
2558: ** when the media is found.
2559: */
2560: static int
2561: dc21041_autoconf(struct device *dev)
2562: {
2563: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2564: u_long iobase = dev->base_addr;
2565: s32 sts, irqs, irq_mask, imr, omr;
2566: int next_tick = DE4X5_AUTOSENSE_MS;
2567:
2568: switch (lp->media) {
2569: case INIT:
2570: DISABLE_IRQs;
2571: lp->tx_enable = NO;
2572: lp->timeout = -1;
2573: de4x5_save_skbs(dev); /* Save non transmitted skb's */
2574: if ((lp->autosense == AUTO) || (lp->autosense == TP_NW)) {
2575: lp->media = TP; /* On chip auto negotiation is broken */
2576: } else if (lp->autosense == TP) {
2577: lp->media = TP;
2578: } else if (lp->autosense == BNC) {
2579: lp->media = BNC;
2580: } else if (lp->autosense == AUI) {
2581: lp->media = AUI;
2582: } else {
2583: lp->media = NC;
2584: }
2585: lp->local_state = 0;
2586: next_tick = dc21041_autoconf(dev);
2587: break;
2588:
2589: case TP_NW:
2590: if (lp->timeout < 0) {
2591: omr = inl(DE4X5_OMR);/* Set up full duplex for the autonegotiate */
2592: outl(omr | OMR_FDX, DE4X5_OMR);
2593: }
2594: irqs = STS_LNF | STS_LNP;
2595: irq_mask = IMR_LFM | IMR_LPM;
2596: sts = test_media(dev, irqs, irq_mask, 0xef01, 0xffff, 0x0008, 2400);
2597: if (sts < 0) {
2598: next_tick = sts & ~TIMER_CB;
2599: } else {
2600: if (sts & STS_LNP) {
2601: lp->media = ANS;
2602: } else {
2603: lp->media = AUI;
2604: }
2605: next_tick = dc21041_autoconf(dev);
2606: }
2607: break;
2608:
2609: case ANS:
2610: if (!lp->tx_enable) {
2611: irqs = STS_LNP;
2612: irq_mask = IMR_LPM;
2613: sts = test_ans(dev, irqs, irq_mask, 3000);
2614: if (sts < 0) {
2615: next_tick = sts & ~TIMER_CB;
2616: } else {
2617: if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2618: lp->media = TP;
2619: next_tick = dc21041_autoconf(dev);
2620: } else {
2621: lp->local_state = 1;
2622: de4x5_init_connection(dev);
2623: }
2624: }
2625: } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2626: lp->media = ANS_SUSPECT;
2627: next_tick = 3000;
2628: }
2629: break;
2630:
2631: case ANS_SUSPECT:
2632: next_tick = de4x5_suspect_state(dev, 1000, ANS, test_tp, dc21041_autoconf);
2633: break;
2634:
2635: case TP:
2636: if (!lp->tx_enable) {
2637: if (lp->timeout < 0) {
2638: omr = inl(DE4X5_OMR); /* Set up half duplex for TP */
2639: outl(omr & ~OMR_FDX, DE4X5_OMR);
2640: }
2641: irqs = STS_LNF | STS_LNP;
2642: irq_mask = IMR_LFM | IMR_LPM;
2643: sts = test_media(dev,irqs, irq_mask, 0xef01, 0xff3f, 0x0008, 2400);
2644: if (sts < 0) {
2645: next_tick = sts & ~TIMER_CB;
2646: } else {
2647: if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2648: if (inl(DE4X5_SISR) & SISR_NRA) {
2649: lp->media = AUI; /* Non selected port activity */
2650: } else {
2651: lp->media = BNC;
2652: }
2653: next_tick = dc21041_autoconf(dev);
2654: } else {
2655: lp->local_state = 1;
2656: de4x5_init_connection(dev);
2657: }
2658: }
2659: } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2660: lp->media = TP_SUSPECT;
2661: next_tick = 3000;
2662: }
2663: break;
2664:
2665: case TP_SUSPECT:
2666: next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21041_autoconf);
2667: break;
2668:
2669: case AUI:
2670: if (!lp->tx_enable) {
2671: if (lp->timeout < 0) {
2672: omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
2673: outl(omr & ~OMR_FDX, DE4X5_OMR);
2674: }
2675: irqs = 0;
2676: irq_mask = 0;
2677: sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x000e, 1000);
2678: if (sts < 0) {
2679: next_tick = sts & ~TIMER_CB;
2680: } else {
2681: if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
2682: lp->media = BNC;
2683: next_tick = dc21041_autoconf(dev);
2684: } else {
2685: lp->local_state = 1;
2686: de4x5_init_connection(dev);
2687: }
2688: }
2689: } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2690: lp->media = AUI_SUSPECT;
2691: next_tick = 3000;
2692: }
2693: break;
2694:
2695: case AUI_SUSPECT:
2696: next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc21041_autoconf);
2697: break;
2698:
2699: case BNC:
2700: switch (lp->local_state) {
2701: case 0:
2702: if (lp->timeout < 0) {
2703: omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
2704: outl(omr & ~OMR_FDX, DE4X5_OMR);
2705: }
2706: irqs = 0;
2707: irq_mask = 0;
2708: sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x0006, 1000);
2709: if (sts < 0) {
2710: next_tick = sts & ~TIMER_CB;
2711: } else {
2712: lp->local_state++; /* Ensure media connected */
2713: next_tick = dc21041_autoconf(dev);
2714: }
2715: break;
2716:
2717: case 1:
2718: if (!lp->tx_enable) {
2719: if ((sts = ping_media(dev, 3000)) < 0) {
2720: next_tick = sts & ~TIMER_CB;
2721: } else {
2722: if (sts) {
2723: lp->local_state = 0;
2724: lp->media = NC;
2725: } else {
2726: de4x5_init_connection(dev);
2727: }
2728: }
2729: } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2730: lp->media = BNC_SUSPECT;
2731: next_tick = 3000;
2732: }
2733: break;
2734: }
2735: break;
2736:
2737: case BNC_SUSPECT:
2738: next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc21041_autoconf);
2739: break;
2740:
2741: case NC:
2742: omr = inl(DE4X5_OMR); /* Set up full duplex for the autonegotiate */
2743: outl(omr | OMR_FDX, DE4X5_OMR);
2744: reset_init_sia(dev, 0xef01, 0xffff, 0x0008);/* Initialise the SIA */
2745: if (lp->media != lp->c_media) {
2746: de4x5_dbg_media(dev);
2747: lp->c_media = lp->media;
2748: }
2749: lp->media = INIT;
2750: lp->tx_enable = NO;
2751: break;
2752: }
2753:
2754: return next_tick;
2755: }
2756:
2757: /*
2758: ** Some autonegotiation chips are broken in that they do not return the
2759: ** acknowledge bit (anlpa & MII_ANLPA_ACK) in the link partner advertisement
2760: ** register, except at the first power up negotiation.
2761: */
2762: static int
2763: dc21140m_autoconf(struct device *dev)
2764: {
2765: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2766: int ana, anlpa, cap, cr, slnk, sr;
2767: int next_tick = DE4X5_AUTOSENSE_MS;
2768: u_long imr, omr, iobase = dev->base_addr;
2769:
2770: switch(lp->media) {
2771: case INIT:
2772: if (lp->timeout < 0) {
2773: DISABLE_IRQs;
2774: lp->tx_enable = FALSE;
2775: lp->linkOK = 0;
2776: de4x5_save_skbs(dev); /* Save non transmitted skb's */
2777: }
2778: if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2779: next_tick &= ~TIMER_CB;
2780: } else {
2781: if (lp->useSROM) {
2782: if (srom_map_media(dev) < 0) {
2783: lp->tcount++;
2784: return next_tick;
2785: }
2786: srom_exec(dev, lp->phy[lp->active].gep);
2787: if (lp->infoblock_media == ANS) {
2788: ana = lp->phy[lp->active].ana | MII_ANA_CSMA;
2789: mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2790: }
2791: } else {
2792: lp->tmp = MII_SR_ASSC; /* Fake out the MII speed set */
2793: SET_10Mb;
2794: if (lp->autosense == _100Mb) {
2795: lp->media = _100Mb;
2796: } else if (lp->autosense == _10Mb) {
2797: lp->media = _10Mb;
2798: } else if ((lp->autosense == AUTO) &&
2799: ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2800: ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2801: ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2802: mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2803: lp->media = ANS;
2804: } else if (lp->autosense == AUTO) {
2805: lp->media = SPD_DET;
2806: } else if (is_spd_100(dev) && is_100_up(dev)) {
2807: lp->media = _100Mb;
2808: } else {
2809: lp->media = NC;
2810: }
2811: }
2812: lp->local_state = 0;
2813: next_tick = dc21140m_autoconf(dev);
2814: }
2815: break;
2816:
2817: case ANS:
2818: switch (lp->local_state) {
2819: case 0:
2820: if (lp->timeout < 0) {
2821: mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
2822: }
2823: cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, FALSE, 500);
2824: if (cr < 0) {
2825: next_tick = cr & ~TIMER_CB;
2826: } else {
2827: if (cr) {
2828: lp->local_state = 0;
2829: lp->media = SPD_DET;
2830: } else {
2831: lp->local_state++;
2832: }
2833: next_tick = dc21140m_autoconf(dev);
2834: }
2835: break;
2836:
2837: case 1:
2838: if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, TRUE, 2000)) < 0) {
2839: next_tick = sr & ~TIMER_CB;
2840: } else {
2841: lp->media = SPD_DET;
2842: lp->local_state = 0;
2843: if (sr) { /* Success! */
2844: lp->tmp = MII_SR_ASSC;
2845: anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
2846: ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2847: if (!(anlpa & MII_ANLPA_RF) &&
2848: (cap = anlpa & MII_ANLPA_TAF & ana)) {
2849: if (cap & MII_ANA_100M) {
2850: lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) ? TRUE : FALSE);
2851: lp->media = _100Mb;
2852: } else if (cap & MII_ANA_10M) {
2853: lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) ? TRUE : FALSE);
2854:
2855: lp->media = _10Mb;
2856: }
2857: }
2858: } /* Auto Negotiation failed to finish */
2859: next_tick = dc21140m_autoconf(dev);
2860: } /* Auto Negotiation failed to start */
2861: break;
2862: }
2863: break;
2864:
2865: case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
2866: if (lp->timeout < 0) {
2867: lp->tmp = (lp->phy[lp->active].id ? MII_SR_LKS :
2868: (~gep_rd(dev) & GEP_LNP));
2869: SET_100Mb_PDET;
2870: }
2871: if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
2872: next_tick = slnk & ~TIMER_CB;
2873: } else {
2874: if (is_spd_100(dev) && is_100_up(dev)) {
2875: lp->media = _100Mb;
2876: } else if ((!is_spd_100(dev) && (is_10_up(dev) & lp->tmp))) {
2877: lp->media = _10Mb;
2878: } else {
2879: lp->media = NC;
2880: }
2881: next_tick = dc21140m_autoconf(dev);
2882: }
2883: break;
2884:
2885: case _100Mb: /* Set 100Mb/s */
2886: next_tick = 3000;
2887: if (!lp->tx_enable) {
2888: SET_100Mb;
2889: de4x5_init_connection(dev);
2890: } else {
2891: if (!lp->linkOK && (lp->autosense == AUTO)) {
2892: if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
2893: lp->media = INIT;
2894: lp->tcount++;
2895: next_tick = DE4X5_AUTOSENSE_MS;
2896: }
2897: }
2898: }
2899: break;
2900:
2901: case BNC:
2902: case AUI:
2903: case _10Mb: /* Set 10Mb/s */
2904: next_tick = 3000;
2905: if (!lp->tx_enable) {
2906: SET_10Mb;
2907: de4x5_init_connection(dev);
2908: } else {
2909: if (!lp->linkOK && (lp->autosense == AUTO)) {
2910: if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
2911: lp->media = INIT;
2912: lp->tcount++;
2913: next_tick = DE4X5_AUTOSENSE_MS;
2914: }
2915: }
2916: }
2917: break;
2918:
2919: case NC:
2920: if (lp->media != lp->c_media) {
2921: de4x5_dbg_media(dev);
2922: lp->c_media = lp->media;
2923: }
2924: lp->media = INIT;
2925: lp->tx_enable = FALSE;
2926: break;
2927: }
2928:
2929: return next_tick;
2930: }
2931:
2932: /*
2933: ** This routine may be merged into dc21140m_autoconf() sometime as I'm
2934: ** changing how I figure out the media - but trying to keep it backwards
2935: ** compatible with the de500-xa and de500-aa.
2936: ** Whether it's BNC, AUI, SYM or MII is sorted out in the infoblock
2937: ** functions and set during de4x5_mac_port() and/or de4x5_reset_phy().
2938: ** This routine just has to figure out whether 10Mb/s or 100Mb/s is
2939: ** active.
2940: ** When autonegotiation is working, the ANS part searches the SROM for
2941: ** the highest common speed (TP) link that both can run and if that can
2942: ** be full duplex. That infoblock is executed and then the link speed set.
2943: **
2944: ** Only _10Mb and _100Mb are tested here.
2945: */
2946: static int
2947: dc2114x_autoconf(struct device *dev)
2948: {
2949: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2950: u_long iobase = dev->base_addr;
2951: s32 cr, anlpa, ana, cap, irqs, irq_mask, imr, omr, slnk, sr, sts;
2952: int next_tick = DE4X5_AUTOSENSE_MS;
2953:
2954: switch (lp->media) {
2955: case INIT:
2956: if (lp->timeout < 0) {
2957: DISABLE_IRQs;
2958: lp->tx_enable = FALSE;
2959: lp->linkOK = 0;
2960: lp->timeout = -1;
2961: de4x5_save_skbs(dev); /* Save non transmitted skb's */
2962: if (lp->params.autosense & ~AUTO) {
2963: srom_map_media(dev); /* Fixed media requested */
2964: if (lp->media != lp->params.autosense) {
2965: lp->tcount++;
2966: lp->media = INIT;
2967: return next_tick;
2968: }
2969: lp->media = INIT;
2970: }
2971: }
2972: if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2973: next_tick &= ~TIMER_CB;
2974: } else {
2975: if (lp->autosense == _100Mb) {
2976: lp->media = _100Mb;
2977: } else if (lp->autosense == _10Mb) {
2978: lp->media = _10Mb;
2979: } else if (lp->autosense == TP) {
2980: lp->media = TP;
2981: } else if (lp->autosense == BNC) {
2982: lp->media = BNC;
2983: } else if (lp->autosense == AUI) {
2984: lp->media = AUI;
2985: } else {
2986: lp->media = SPD_DET;
2987: if ((lp->infoblock_media == ANS) &&
2988: ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2989: ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2990: ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2991: mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2992: lp->media = ANS;
2993: }
2994: }
2995: lp->local_state = 0;
2996: next_tick = dc2114x_autoconf(dev);
2997: }
2998: break;
2999:
3000: case ANS:
3001: switch (lp->local_state) {
3002: case 0:
3003: if (lp->timeout < 0) {
3004: mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3005: }
3006: cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, FALSE, 500);
3007: if (cr < 0) {
3008: next_tick = cr & ~TIMER_CB;
3009: } else {
3010: if (cr) {
3011: lp->local_state = 0;
3012: lp->media = SPD_DET;
3013: } else {
3014: lp->local_state++;
3015: }
3016: next_tick = dc2114x_autoconf(dev);
3017: }
3018: break;
3019:
3020: case 1:
3021: if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, TRUE, 2000)) < 0) {
3022: next_tick = sr & ~TIMER_CB;
3023: } else {
3024: lp->media = SPD_DET;
3025: lp->local_state = 0;
3026: if (sr) { /* Success! */
3027: lp->tmp = MII_SR_ASSC;
3028: anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
3029: ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
3030: if (!(anlpa & MII_ANLPA_RF) &&
3031: (cap = anlpa & MII_ANLPA_TAF & ana)) {
3032: if (cap & MII_ANA_100M) {
3033: lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) ? TRUE : FALSE);
3034: lp->media = _100Mb;
3035: } else if (cap & MII_ANA_10M) {
3036: lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) ? TRUE : FALSE);
3037: lp->media = _10Mb;
3038: }
3039: }
3040: } /* Auto Negotiation failed to finish */
3041: next_tick = dc2114x_autoconf(dev);
3042: } /* Auto Negotiation failed to start */
3043: break;
3044: }
3045: break;
3046:
3047: case AUI:
3048: if (!lp->tx_enable) {
3049: if (lp->timeout < 0) {
3050: omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
3051: outl(omr & ~OMR_FDX, DE4X5_OMR);
3052: }
3053: irqs = 0;
3054: irq_mask = 0;
3055: sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3056: if (sts < 0) {
3057: next_tick = sts & ~TIMER_CB;
3058: } else {
3059: if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
3060: lp->media = BNC;
3061: next_tick = dc2114x_autoconf(dev);
3062: } else {
3063: lp->local_state = 1;
3064: de4x5_init_connection(dev);
3065: }
3066: }
3067: } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3068: lp->media = AUI_SUSPECT;
3069: next_tick = 3000;
3070: }
3071: break;
3072:
3073: case AUI_SUSPECT:
3074: next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc2114x_autoconf);
3075: break;
3076:
3077: case BNC:
3078: switch (lp->local_state) {
3079: case 0:
3080: if (lp->timeout < 0) {
3081: omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
3082: outl(omr & ~OMR_FDX, DE4X5_OMR);
3083: }
3084: irqs = 0;
3085: irq_mask = 0;
3086: sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3087: if (sts < 0) {
3088: next_tick = sts & ~TIMER_CB;
3089: } else {
3090: lp->local_state++; /* Ensure media connected */
3091: next_tick = dc2114x_autoconf(dev);
3092: }
3093: break;
3094:
3095: case 1:
3096: if (!lp->tx_enable) {
3097: if ((sts = ping_media(dev, 3000)) < 0) {
3098: next_tick = sts & ~TIMER_CB;
3099: } else {
3100: if (sts) {
3101: lp->local_state = 0;
3102: lp->tcount++;
3103: lp->media = INIT;
3104: } else {
3105: de4x5_init_connection(dev);
3106: }
3107: }
3108: } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3109: lp->media = BNC_SUSPECT;
3110: next_tick = 3000;
3111: }
3112: break;
3113: }
3114: break;
3115:
3116: case BNC_SUSPECT:
3117: next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc2114x_autoconf);
3118: break;
3119:
3120: case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
3121: if (srom_map_media(dev) < 0) {
3122: lp->tcount++;
3123: lp->media = INIT;
3124: return next_tick;
3125: }
3126: if (lp->media == _100Mb) {
3127: if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
3128: lp->media = SPD_DET;
3129: return (slnk & ~TIMER_CB);
3130: }
3131: } else {
3132: if (wait_for_link(dev) < 0) {
3133: lp->media = SPD_DET;
3134: return PDET_LINK_WAIT;
3135: }
3136: }
3137: if (lp->media == ANS) { /* Do MII parallel detection */
3138: if (is_spd_100(dev)) {
3139: lp->media = _100Mb;
3140: } else {
3141: lp->media = _10Mb;
3142: }
3143: next_tick = dc2114x_autoconf(dev);
3144: } else if (((lp->media == _100Mb) && is_100_up(dev)) ||
3145: (((lp->media == _10Mb) || (lp->media == TP) ||
3146: (lp->media == BNC) || (lp->media == AUI)) &&
3147: is_10_up(dev))) {
3148: next_tick = dc2114x_autoconf(dev);
3149: } else {
3150: lp->tcount++;
3151: lp->media = INIT;
3152: }
3153: break;
3154:
3155: case _10Mb:
3156: next_tick = 3000;
3157: if (!lp->tx_enable) {
3158: SET_10Mb;
3159: de4x5_init_connection(dev);
3160: } else {
3161: if (!lp->linkOK && (lp->autosense == AUTO)) {
3162: if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
3163: lp->media = INIT;
3164: lp->tcount++;
3165: next_tick = DE4X5_AUTOSENSE_MS;
3166: }
3167: }
3168: }
3169: break;
3170:
3171: case _100Mb:
3172: next_tick = 3000;
3173: if (!lp->tx_enable) {
3174: SET_100Mb;
3175: de4x5_init_connection(dev);
3176: } else {
3177: if (!lp->linkOK && (lp->autosense == AUTO)) {
3178: if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
3179: lp->media = INIT;
3180: lp->tcount++;
3181: next_tick = DE4X5_AUTOSENSE_MS;
3182: }
3183: }
3184: }
3185: break;
3186:
3187: default:
3188: lp->tcount++;
3189: printk("Huh?: media:%02x\n", lp->media);
3190: lp->media = INIT;
3191: break;
3192: }
3193:
3194: return next_tick;
3195: }
3196:
3197: static int
3198: srom_autoconf(struct device *dev)
3199: {
3200: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3201:
3202: return lp->infoleaf_fn(dev);
3203: }
3204:
3205: /*
3206: ** This mapping keeps the original media codes and FDX flag unchanged.
3207: ** While it isn't strictly necessary, it helps me for the moment...
3208: ** The early return avoids a media state / SROM media space clash.
3209: */
3210: static int
3211: srom_map_media(struct device *dev)
3212: {
3213: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3214:
3215: lp->fdx = 0;
3216: if (lp->infoblock_media == lp->media)
3217: return 0;
3218:
3219: switch(lp->infoblock_media) {
3220: case SROM_10BASETF:
3221: if (!lp->params.fdx) return -1;
3222: lp->fdx = TRUE;
3223: case SROM_10BASET:
3224: if (lp->params.fdx && !lp->fdx) return -1;
3225: if ((lp->chipset == DC21140) || ((lp->chipset & ~0x00ff) == DC2114x)) {
3226: lp->media = _10Mb;
3227: } else {
3228: lp->media = TP;
3229: }
3230: break;
3231:
3232: case SROM_10BASE2:
3233: lp->media = BNC;
3234: break;
3235:
3236: case SROM_10BASE5:
3237: lp->media = AUI;
3238: break;
3239:
3240: case SROM_100BASETF:
3241: if (!lp->params.fdx) return -1;
3242: lp->fdx = TRUE;
3243: case SROM_100BASET:
3244: if (lp->params.fdx && !lp->fdx) return -1;
3245: lp->media = _100Mb;
3246: break;
3247:
3248: case SROM_100BASET4:
3249: lp->media = _100Mb;
3250: break;
3251:
3252: case SROM_100BASEFF:
3253: if (!lp->params.fdx) return -1;
3254: lp->fdx = TRUE;
3255: case SROM_100BASEF:
3256: if (lp->params.fdx && !lp->fdx) return -1;
3257: lp->media = _100Mb;
3258: break;
3259:
3260: case ANS:
3261: lp->media = ANS;
3262: break;
3263:
3264: default:
3265: printk("%s: Bad media code [%d] detected in SROM!\n", dev->name,
3266: lp->infoblock_media);
3267: return -1;
3268: break;
3269: }
3270:
3271: return 0;
3272: }
3273:
3274: static void
3275: de4x5_init_connection(struct device *dev)
3276: {
3277: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3278: u_long iobase = dev->base_addr;
3279:
3280: if (lp->media != lp->c_media) {
3281: de4x5_dbg_media(dev);
3282: lp->c_media = lp->media; /* Stop scrolling media messages */
3283: }
3284:
3285: cli();
3286: de4x5_rst_desc_ring(dev);
3287: de4x5_setup_intr(dev);
3288: lp->tx_enable = YES;
3289: dev->tbusy = 0;
3290: sti();
3291: outl(POLL_DEMAND, DE4X5_TPD);
3292: mark_bh(NET_BH);
3293:
3294: return;
3295: }
3296:
3297: /*
3298: ** General PHY reset function. Some MII devices don't reset correctly
3299: ** since their MII address pins can float at voltages that are dependent
3300: ** on the signal pin use. Do a double reset to ensure a reset.
3301: */
3302: static int
3303: de4x5_reset_phy(struct device *dev)
3304: {
3305: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3306: u_long iobase = dev->base_addr;
3307: int next_tick = 0;
3308:
3309: if ((lp->useSROM) || (lp->phy[lp->active].id)) {
3310: if (lp->timeout < 0) {
3311: if (lp->useSROM) {
3312: if (lp->phy[lp->active].rst) {
3313: srom_exec(dev, lp->phy[lp->active].rst);
3314: srom_exec(dev, lp->phy[lp->active].rst);
3315: } else if (lp->rst) { /* Type 5 infoblock reset */
3316: srom_exec(dev, lp->rst);
3317: srom_exec(dev, lp->rst);
3318: }
3319: } else {
3320: PHY_HARD_RESET;
3321: }
3322: if (lp->useMII) {
3323: mii_wr(MII_CR_RST, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3324: }
3325: }
3326: if (lp->useMII) {
3327: next_tick = test_mii_reg(dev, MII_CR, MII_CR_RST, FALSE, 500);
3328: }
3329: } else if (lp->chipset == DC21140) {
3330: PHY_HARD_RESET;
3331: }
3332:
3333: return next_tick;
3334: }
3335:
3336: static int
3337: test_media(struct device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec)
3338: {
3339: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3340: u_long iobase = dev->base_addr;
3341: s32 sts, csr12;
3342:
3343: if (lp->timeout < 0) {
3344: lp->timeout = msec/100;
3345: if (!lp->useSROM) { /* Already done if by SROM, else dc2104[01] */
3346: reset_init_sia(dev, csr13, csr14, csr15);
3347: }
3348:
3349: /* set up the interrupt mask */
3350: outl(irq_mask, DE4X5_IMR);
3351:
3352: /* clear all pending interrupts */
3353: sts = inl(DE4X5_STS);
3354: outl(sts, DE4X5_STS);
3355:
3356: /* clear csr12 NRA and SRA bits */
3357: if ((lp->chipset == DC21041) || lp->useSROM) {
3358: csr12 = inl(DE4X5_SISR);
3359: outl(csr12, DE4X5_SISR);
3360: }
3361: }
3362:
3363: sts = inl(DE4X5_STS) & ~TIMER_CB;
3364:
3365: if (!(sts & irqs) && --lp->timeout) {
3366: sts = 100 | TIMER_CB;
3367: } else {
3368: lp->timeout = -1;
3369: }
3370:
3371: return sts;
3372: }
3373:
3374: static int
3375: test_tp(struct device *dev, s32 msec)
3376: {
3377: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3378: u_long iobase = dev->base_addr;
3379: int sisr;
3380:
3381: if (lp->timeout < 0) {
3382: lp->timeout = msec/100;
3383: }
3384:
3385: sisr = (inl(DE4X5_SISR) & ~TIMER_CB) & (SISR_LKF | SISR_NCR);
3386:
3387: if (sisr && --lp->timeout) {
3388: sisr = 100 | TIMER_CB;
3389: } else {
3390: lp->timeout = -1;
3391: }
3392:
3393: return sisr;
3394: }
3395:
3396: /*
3397: ** Samples the 100Mb Link State Signal. The sample interval is important
3398: ** because too fast a rate can give erroneous results and confuse the
3399: ** speed sense algorithm.
3400: */
3401: #define SAMPLE_INTERVAL 500 /* ms */
3402: #define SAMPLE_DELAY 2000 /* ms */
3403: static int
3404: test_for_100Mb(struct device *dev, int msec)
3405: {
3406: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3407: int gep = 0, ret = ((lp->chipset & ~0x00ff)==DC2114x? -1 :GEP_SLNK);
3408:
3409: if (lp->timeout < 0) {
3410: if ((msec/SAMPLE_INTERVAL) <= 0) return 0;
3411: if (msec > SAMPLE_DELAY) {
3412: lp->timeout = (msec - SAMPLE_DELAY)/SAMPLE_INTERVAL;
3413: gep = SAMPLE_DELAY | TIMER_CB;
3414: return gep;
3415: } else {
3416: lp->timeout = msec/SAMPLE_INTERVAL;
3417: }
3418: }
3419:
3420: if (lp->phy[lp->active].id || lp->useSROM) {
3421: gep = is_100_up(dev) | is_spd_100(dev);
3422: } else {
3423: gep = (~gep_rd(dev) & (GEP_SLNK | GEP_LNP));
3424: }
3425: if (!(gep & ret) && --lp->timeout) {
3426: gep = SAMPLE_INTERVAL | TIMER_CB;
3427: } else {
3428: lp->timeout = -1;
3429: }
3430:
3431: return gep;
3432: }
3433:
3434: static int
3435: wait_for_link(struct device *dev)
3436: {
3437: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3438:
3439: if (lp->timeout < 0) {
3440: lp->timeout = 1;
3441: }
3442:
3443: if (lp->timeout--) {
3444: return TIMER_CB;
3445: } else {
3446: lp->timeout = -1;
3447: }
3448:
3449: return 0;
3450: }
3451:
3452: /*
3453: **
3454: **
3455: */
3456: static int
3457: test_mii_reg(struct device *dev, int reg, int mask, int pol, long msec)
3458: {
3459: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3460: int test;
3461: u_long iobase = dev->base_addr;
3462:
3463: if (lp->timeout < 0) {
3464: lp->timeout = msec/100;
3465: }
3466:
3467: if (pol) pol = ~0;
3468: reg = mii_rd((u_char)reg, lp->phy[lp->active].addr, DE4X5_MII) & mask;
3469: test = (reg ^ pol) & mask;
3470:
3471: if (test && --lp->timeout) {
3472: reg = 100 | TIMER_CB;
3473: } else {
3474: lp->timeout = -1;
3475: }
3476:
3477: return reg;
3478: }
3479:
3480: static int
3481: is_spd_100(struct device *dev)
3482: {
3483: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3484: u_long iobase = dev->base_addr;
3485: int spd;
3486:
3487: if (lp->useMII) {
3488: spd = mii_rd(lp->phy[lp->active].spd.reg, lp->phy[lp->active].addr, DE4X5_MII);
3489: spd = ~(spd ^ lp->phy[lp->active].spd.value);
3490: spd &= lp->phy[lp->active].spd.mask;
3491: } else if (!lp->useSROM) { /* de500-xa */
3492: spd = ((~gep_rd(dev)) & GEP_SLNK);
3493: } else {
3494: if ((lp->ibn == 2) || !lp->asBitValid)
3495: return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0);
3496:
3497: spd = (lp->asBitValid & (lp->asPolarity ^ (gep_rd(dev) & lp->asBit))) |
3498: (lp->linkOK & ~lp->asBitValid);
3499: }
3500:
3501: return spd;
3502: }
3503:
3504: static int
3505: is_100_up(struct device *dev)
3506: {
3507: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3508: u_long iobase = dev->base_addr;
3509:
3510: if (lp->useMII) {
3511: /* Double read for sticky bits & temporary drops */
3512: mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3513: return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
3514: } else if (!lp->useSROM) { /* de500-xa */
3515: return ((~gep_rd(dev)) & GEP_SLNK);
3516: } else {
3517: if ((lp->ibn == 2) || !lp->asBitValid)
3518: return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0);
3519:
3520: return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3521: (lp->linkOK & ~lp->asBitValid));
3522: }
3523: }
3524:
3525: static int
3526: is_10_up(struct device *dev)
3527: {
3528: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3529: u_long iobase = dev->base_addr;
3530:
3531: if (lp->useMII) {
3532: /* Double read for sticky bits & temporary drops */
3533: mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3534: return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
3535: } else if (!lp->useSROM) { /* de500-xa */
3536: return ((~gep_rd(dev)) & GEP_LNP);
3537: } else {
3538: if ((lp->ibn == 2) || !lp->asBitValid)
3539: return (((lp->chipset & ~0x00ff) == DC2114x) ?
3540: (~inl(DE4X5_SISR)&SISR_LS10):
3541: 0);
3542:
3543: return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3544: (lp->linkOK & ~lp->asBitValid));
3545: }
3546: }
3547:
3548: static int
3549: is_anc_capable(struct device *dev)
3550: {
3551: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3552: u_long iobase = dev->base_addr;
3553:
3554: if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
3555: return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII));
3556: } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3557: return (inl(DE4X5_SISR) & SISR_LPN) >> 12;
3558: } else {
3559: return 0;
3560: }
3561: }
3562:
3563: /*
3564: ** Send a packet onto the media and watch for send errors that indicate the
3565: ** media is bad or unconnected.
3566: */
3567: static int
3568: ping_media(struct device *dev, int msec)
3569: {
3570: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3571: u_long iobase = dev->base_addr;
3572: int sisr;
3573:
3574: if (lp->timeout < 0) {
3575: lp->timeout = msec/100;
3576:
3577: lp->tmp = lp->tx_new; /* Remember the ring position */
3578: load_packet(dev, lp->frame, TD_LS | TD_FS | sizeof(lp->frame), NULL);
1.1.1.2 ! root 3579: lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
1.1 root 3580: outl(POLL_DEMAND, DE4X5_TPD);
3581: }
3582:
3583: sisr = inl(DE4X5_SISR);
3584:
3585: if ((!(sisr & SISR_NCR)) &&
3586: ((s32)le32_to_cpu(lp->tx_ring[lp->tmp].status) < 0) &&
3587: (--lp->timeout)) {
3588: sisr = 100 | TIMER_CB;
3589: } else {
3590: if ((!(sisr & SISR_NCR)) &&
3591: !(le32_to_cpu(lp->tx_ring[lp->tmp].status) & (T_OWN | TD_ES)) &&
3592: lp->timeout) {
3593: sisr = 0;
3594: } else {
3595: sisr = 1;
3596: }
3597: lp->timeout = -1;
3598: }
3599:
3600: return sisr;
3601: }
3602:
3603: /*
3604: ** This function does 2 things: on Intels it kmalloc's another buffer to
3605: ** replace the one about to be passed up. On Alpha's it kmallocs a buffer
3606: ** into which the packet is copied.
3607: */
3608: static struct sk_buff *
3609: de4x5_alloc_rx_buff(struct device *dev, int index, int len)
3610: {
3611: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3612: struct sk_buff *p;
3613:
3614: #if !defined(__alpha__) && !defined(__powerpc__) && !defined(__sparc_v9__) && !defined(DE4X5_DO_MEMCPY)
3615: struct sk_buff *ret;
3616: u_long i=0, tmp;
3617:
3618: p = dev_alloc_skb(IEEE802_3_SZ + ALIGN + 2);
3619: if (!p) return NULL;
3620:
3621: p->dev = dev;
3622: tmp = virt_to_bus(p->data);
3623: i = ((tmp + ALIGN) & ~ALIGN) - tmp;
3624: skb_reserve(p, i);
3625: lp->rx_ring[index].buf = tmp + i;
3626:
3627: ret = lp->rx_skb[index];
3628: lp->rx_skb[index] = p;
3629:
3630: if ((u_long) ret > 1) {
3631: skb_put(ret, len);
3632: }
3633:
3634: return ret;
3635:
3636: #else
3637: if (lp->state != OPEN) return (struct sk_buff *)1; /* Fake out the open */
3638:
3639: p = dev_alloc_skb(len + 2);
3640: if (!p) return NULL;
3641:
3642: p->dev = dev;
3643: skb_reserve(p, 2); /* Align */
3644: if (index < lp->rx_old) { /* Wrapped buffer */
3645: short tlen = (lp->rxRingSize - lp->rx_old) * RX_BUFF_SZ;
3646: memcpy(skb_put(p,tlen),
3647: bus_to_virt(le32_to_cpu(lp->rx_ring[lp->rx_old].buf)),tlen);
3648: memcpy(skb_put(p,len-tlen),
3649: bus_to_virt(le32_to_cpu(lp->rx_ring[0].buf)), len-tlen);
3650: } else { /* Linear buffer */
3651: memcpy(skb_put(p,len),
3652: bus_to_virt(le32_to_cpu(lp->rx_ring[lp->rx_old].buf)),len);
3653: }
3654:
3655: return p;
3656: #endif
3657: }
3658:
3659: static void
3660: de4x5_free_rx_buffs(struct device *dev)
3661: {
3662: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3663: int i;
3664:
3665: for (i=0; i<lp->rxRingSize; i++) {
3666: if ((u_long) lp->rx_skb[i] > 1) {
3667: dev_kfree_skb(lp->rx_skb[i], FREE_WRITE);
3668: }
3669: lp->rx_ring[i].status = 0;
3670: lp->rx_skb[i] = (struct sk_buff *)1; /* Dummy entry */
3671: }
3672:
3673: return;
3674: }
3675:
3676: static void
3677: de4x5_free_tx_buffs(struct device *dev)
3678: {
3679: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3680: int i;
3681:
3682: for (i=0; i<lp->txRingSize; i++) {
3683: if (lp->tx_skb[i]) {
3684: dev_kfree_skb(lp->tx_skb[i], FREE_WRITE);
3685: lp->tx_skb[i] = NULL;
3686: }
3687: lp->tx_ring[i].status = 0;
3688: }
3689:
3690: /* Unload the locally queued packets */
3691: while (lp->cache.skb) {
3692: dev_kfree_skb(de4x5_get_cache(dev), FREE_WRITE);
3693: }
3694:
3695: return;
3696: }
3697:
3698: /*
3699: ** When a user pulls a connection, the DECchip can end up in a
3700: ** 'running - waiting for end of transmission' state. This means that we
3701: ** have to perform a chip soft reset to ensure that we can synchronize
3702: ** the hardware and software and make any media probes using a loopback
3703: ** packet meaningful.
3704: */
3705: static void
3706: de4x5_save_skbs(struct device *dev)
3707: {
3708: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3709: u_long iobase = dev->base_addr;
3710: s32 omr;
3711:
3712: if (!lp->cache.save_cnt) {
3713: STOP_DE4X5;
3714: de4x5_tx(dev); /* Flush any sent skb's */
3715: de4x5_free_tx_buffs(dev);
3716: de4x5_cache_state(dev, DE4X5_SAVE_STATE);
3717: de4x5_sw_reset(dev);
3718: de4x5_cache_state(dev, DE4X5_RESTORE_STATE);
3719: lp->cache.save_cnt++;
3720: START_DE4X5;
3721: }
3722:
3723: return;
3724: }
3725:
3726: static void
3727: de4x5_rst_desc_ring(struct device *dev)
3728: {
3729: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3730: u_long iobase = dev->base_addr;
3731: int i;
3732: s32 omr;
3733:
3734: if (lp->cache.save_cnt) {
3735: STOP_DE4X5;
3736: outl(virt_to_bus(lp->rx_ring), DE4X5_RRBA);
3737: outl(virt_to_bus(lp->tx_ring), DE4X5_TRBA);
3738:
3739: lp->rx_new = lp->rx_old = 0;
3740: lp->tx_new = lp->tx_old = 0;
3741:
3742: for (i = 0; i < lp->rxRingSize; i++) {
3743: lp->rx_ring[i].status = cpu_to_le32(R_OWN);
3744: }
3745:
3746: for (i = 0; i < lp->txRingSize; i++) {
3747: lp->tx_ring[i].status = cpu_to_le32(0);
3748: }
3749:
3750: barrier();
3751: lp->cache.save_cnt--;
3752: START_DE4X5;
3753: }
3754:
3755: return;
3756: }
3757:
3758: static void
3759: de4x5_cache_state(struct device *dev, int flag)
3760: {
3761: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3762: u_long iobase = dev->base_addr;
3763:
3764: switch(flag) {
3765: case DE4X5_SAVE_STATE:
3766: lp->cache.csr0 = inl(DE4X5_BMR);
3767: lp->cache.csr6 = (inl(DE4X5_OMR) & ~(OMR_ST | OMR_SR));
3768: lp->cache.csr7 = inl(DE4X5_IMR);
3769: break;
3770:
3771: case DE4X5_RESTORE_STATE:
3772: outl(lp->cache.csr0, DE4X5_BMR);
3773: outl(lp->cache.csr6, DE4X5_OMR);
3774: outl(lp->cache.csr7, DE4X5_IMR);
3775: if (lp->chipset == DC21140) {
3776: gep_wr(lp->cache.gepc, dev);
3777: gep_wr(lp->cache.gep, dev);
3778: } else {
3779: reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14,
3780: lp->cache.csr15);
3781: }
3782: break;
3783: }
3784:
3785: return;
3786: }
3787:
3788: static void
3789: de4x5_put_cache(struct device *dev, struct sk_buff *skb)
3790: {
3791: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3792: struct sk_buff *p;
3793:
3794: if (lp->cache.skb) {
3795: for (p=lp->cache.skb; p->next; p=p->next);
3796: p->next = skb;
3797: } else {
3798: lp->cache.skb = skb;
3799: }
3800: skb->next = NULL;
3801:
3802: return;
3803: }
3804:
3805: static void
3806: de4x5_putb_cache(struct device *dev, struct sk_buff *skb)
3807: {
3808: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3809: struct sk_buff *p = lp->cache.skb;
3810:
3811: lp->cache.skb = skb;
3812: skb->next = p;
3813:
3814: return;
3815: }
3816:
3817: static struct sk_buff *
3818: de4x5_get_cache(struct device *dev)
3819: {
3820: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3821: struct sk_buff *p = lp->cache.skb;
3822:
3823: if (p) {
3824: lp->cache.skb = p->next;
3825: p->next = NULL;
3826: }
3827:
3828: return p;
3829: }
3830:
3831: /*
3832: ** Check the Auto Negotiation State. Return OK when a link pass interrupt
3833: ** is received and the auto-negotiation status is NWAY OK.
3834: */
3835: static int
3836: test_ans(struct device *dev, s32 irqs, s32 irq_mask, s32 msec)
3837: {
3838: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3839: u_long iobase = dev->base_addr;
3840: s32 sts, ans;
3841:
3842: if (lp->timeout < 0) {
3843: lp->timeout = msec/100;
3844: outl(irq_mask, DE4X5_IMR);
3845:
3846: /* clear all pending interrupts */
3847: sts = inl(DE4X5_STS);
3848: outl(sts, DE4X5_STS);
3849: }
3850:
3851: ans = inl(DE4X5_SISR) & SISR_ANS;
3852: sts = inl(DE4X5_STS) & ~TIMER_CB;
3853:
3854: if (!(sts & irqs) && (ans ^ ANS_NWOK) && --lp->timeout) {
3855: sts = 100 | TIMER_CB;
3856: } else {
3857: lp->timeout = -1;
3858: }
3859:
3860: return sts;
3861: }
3862:
3863: static void
3864: de4x5_setup_intr(struct device *dev)
3865: {
3866: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3867: u_long iobase = dev->base_addr;
3868: s32 imr, sts;
3869:
3870: if (inl(DE4X5_OMR) & OMR_SR) { /* Only unmask if TX/RX is enabled */
3871: imr = 0;
3872: UNMASK_IRQs;
3873: sts = inl(DE4X5_STS); /* Reset any pending (stale) interrupts */
3874: outl(sts, DE4X5_STS);
3875: ENABLE_IRQs;
3876: }
3877:
3878: return;
3879: }
3880:
3881: /*
3882: **
3883: */
3884: static void
3885: reset_init_sia(struct device *dev, s32 csr13, s32 csr14, s32 csr15)
3886: {
3887: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3888: u_long iobase = dev->base_addr;
3889:
3890: RESET_SIA;
3891: if (lp->useSROM) {
3892: if (lp->ibn == 3) {
3893: srom_exec(dev, lp->phy[lp->active].rst);
3894: srom_exec(dev, lp->phy[lp->active].gep);
3895: outl(1, DE4X5_SICR);
3896: return;
3897: } else {
3898: csr15 = lp->cache.csr15;
3899: csr14 = lp->cache.csr14;
3900: csr13 = lp->cache.csr13;
3901: outl(csr15 | lp->cache.gepc, DE4X5_SIGR);
3902: outl(csr15 | lp->cache.gep, DE4X5_SIGR);
3903: }
3904: } else {
3905: outl(csr15, DE4X5_SIGR);
3906: }
3907: outl(csr14, DE4X5_STRR);
3908: outl(csr13, DE4X5_SICR);
3909:
3910: de4x5_ms_delay(10);
3911:
3912: return;
3913: }
3914:
3915: /*
3916: ** Create a loopback ethernet packet
3917: */
3918: static void
3919: create_packet(struct device *dev, char *frame, int len)
3920: {
3921: int i;
3922: char *buf = frame;
3923:
3924: for (i=0; i<ETH_ALEN; i++) { /* Use this source address */
3925: *buf++ = dev->dev_addr[i];
3926: }
3927: for (i=0; i<ETH_ALEN; i++) { /* Use this destination address */
3928: *buf++ = dev->dev_addr[i];
3929: }
3930:
3931: *buf++ = 0; /* Packet length (2 bytes) */
3932: *buf++ = 1;
3933:
3934: return;
3935: }
3936:
3937: /*
3938: ** Known delay in microseconds
3939: */
3940: static void
3941: de4x5_us_delay(u32 usec)
3942: {
3943: udelay(usec);
3944:
3945: return;
3946: }
3947:
3948: /*
3949: ** Known delay in milliseconds, in millisecond steps.
3950: */
3951: static void
3952: de4x5_ms_delay(u32 msec)
3953: {
3954: u_int i;
3955:
3956: for (i=0; i<msec; i++) {
3957: de4x5_us_delay(1000);
3958: }
3959:
3960: return;
3961: }
3962:
3963:
3964: /*
3965: ** Look for a particular board name in the EISA configuration space
3966: */
3967: static int
3968: EISA_signature(char *name, s32 eisa_id)
3969: {
3970: static c_char *signatures[] = DE4X5_SIGNATURE;
3971: char ManCode[DE4X5_STRLEN];
3972: union {
3973: s32 ID;
3974: char Id[4];
3975: } Eisa;
3976: int i, status = 0, siglen = sizeof(signatures)/sizeof(c_char *);
3977:
3978: *name = '\0';
3979: Eisa.ID = inl(eisa_id);
3980:
3981: ManCode[0]=(((Eisa.Id[0]>>2)&0x1f)+0x40);
3982: ManCode[1]=(((Eisa.Id[1]&0xe0)>>5)+((Eisa.Id[0]&0x03)<<3)+0x40);
3983: ManCode[2]=(((Eisa.Id[2]>>4)&0x0f)+0x30);
3984: ManCode[3]=((Eisa.Id[2]&0x0f)+0x30);
3985: ManCode[4]=(((Eisa.Id[3]>>4)&0x0f)+0x30);
3986: ManCode[5]='\0';
3987:
3988: for (i=0;i<siglen;i++) {
3989: if (strstr(ManCode, signatures[i]) != NULL) {
3990: strcpy(name,ManCode);
3991: status = 1;
3992: break;
3993: }
3994: }
3995:
3996: return status; /* return the device name string */
3997: }
3998:
3999: /*
4000: ** Look for a particular board name in the PCI configuration space
4001: */
4002: static int
4003: PCI_signature(char *name, struct bus_type *lp)
4004: {
4005: static c_char *de4x5_signatures[] = DE4X5_SIGNATURE;
4006: int i, status = 0, siglen = sizeof(de4x5_signatures)/sizeof(c_char *);
4007:
4008: if (lp->chipset == DC21040) {
4009: strcpy(name, "DE434/5");
4010: return status;
4011: } else { /* Search for a DEC name in the SROM */
4012: int i = *((char *)&lp->srom + 19) * 3;
4013: strncpy(name, (char *)&lp->srom + 26 + i, 8);
4014: }
4015: name[8] = '\0';
4016: for (i=0; i<siglen; i++) {
4017: if (strstr(name,de4x5_signatures[i])!=NULL) break;
4018: }
4019: if (i == siglen) {
4020: if (dec_only) {
4021: *name = '\0';
4022: } else { /* Use chip name to avoid confusion */
4023: strcpy(name, (((lp->chipset == DC21040) ? "DC21040" :
4024: ((lp->chipset == DC21041) ? "DC21041" :
4025: ((lp->chipset == DC21140) ? "DC21140" :
4026: ((lp->chipset == DC21142) ? "DC21142" :
4027: ((lp->chipset == DC21143) ? "DC21143" : "UNKNOWN"
4028: )))))));
4029: }
4030: if (lp->chipset != DC21041) {
4031: useSROM = TRUE; /* card is not recognisably DEC */
4032: }
4033: } else if ((lp->chipset & ~0x00ff) == DC2114x) {
4034: useSROM = TRUE;
4035: }
4036:
4037: return status;
4038: }
4039:
4040: /*
4041: ** Set up the Ethernet PROM counter to the start of the Ethernet address on
4042: ** the DC21040, else read the SROM for the other chips.
4043: ** The SROM may not be present in a multi-MAC card, so first read the
4044: ** MAC address and check for a bad address. If there is a bad one then exit
4045: ** immediately with the prior srom contents intact (the h/w address will
4046: ** be fixed up later).
4047: */
4048: static void
4049: DevicePresent(u_long aprom_addr)
4050: {
4051: int i, j=0;
4052: struct bus_type *lp = &bus;
4053:
4054: if (lp->chipset == DC21040) {
4055: if (lp->bus == EISA) {
4056: enet_addr_rst(aprom_addr); /* Reset Ethernet Address ROM Pointer */
4057: } else {
4058: outl(0, aprom_addr); /* Reset Ethernet Address ROM Pointer */
4059: }
4060: } else { /* Read new srom */
4061: u_short tmp, *p = (short *)((char *)&lp->srom + SROM_HWADD);
4062: for (i=0; i<(ETH_ALEN>>1); i++) {
4063: tmp = srom_rd(aprom_addr, (SROM_HWADD>>1) + i);
4064: *p = le16_to_cpu(tmp);
4065: j += *p++;
4066: }
4067: if ((j == 0) || (j == 0x2fffd)) {
4068: return;
4069: }
4070:
4071: p=(short *)&lp->srom;
4072: for (i=0; i<(sizeof(struct de4x5_srom)>>1); i++) {
4073: tmp = srom_rd(aprom_addr, i);
4074: *p++ = le16_to_cpu(tmp);
4075: }
4076: de4x5_dbg_srom((struct de4x5_srom *)&lp->srom);
4077: }
4078:
4079: return;
4080: }
4081:
4082: /*
4083: ** Since the write on the Enet PROM register doesn't seem to reset the PROM
4084: ** pointer correctly (at least on my DE425 EISA card), this routine should do
4085: ** it...from depca.c.
4086: */
4087: static void
4088: enet_addr_rst(u_long aprom_addr)
4089: {
4090: union {
4091: struct {
4092: u32 a;
4093: u32 b;
4094: } llsig;
4095: char Sig[sizeof(u32) << 1];
4096: } dev;
4097: short sigLength=0;
4098: s8 data;
4099: int i, j;
4100:
4101: dev.llsig.a = ETH_PROM_SIG;
4102: dev.llsig.b = ETH_PROM_SIG;
4103: sigLength = sizeof(u32) << 1;
4104:
4105: for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) {
4106: data = inb(aprom_addr);
4107: if (dev.Sig[j] == data) { /* track signature */
4108: j++;
4109: } else { /* lost signature; begin search again */
4110: if (data == dev.Sig[0]) { /* rare case.... */
4111: j=1;
4112: } else {
4113: j=0;
4114: }
4115: }
4116: }
4117:
4118: return;
4119: }
4120:
4121: /*
4122: ** For the bad status case and no SROM, then add one to the previous
4123: ** address. However, need to add one backwards in case we have 0xff
4124: ** as one or more of the bytes. Only the last 3 bytes should be checked
4125: ** as the first three are invariant - assigned to an organisation.
4126: */
4127: static int
4128: get_hw_addr(struct device *dev)
4129: {
4130: u_long iobase = dev->base_addr;
4131: int broken, i, k, tmp, status = 0;
4132: u_short j,chksum;
4133: struct bus_type *lp = &bus;
4134:
4135: broken = de4x5_bad_srom(lp);
4136:
4137: for (i=0,k=0,j=0;j<3;j++) {
4138: k <<= 1;
4139: if (k > 0xffff) k-=0xffff;
4140:
4141: if (lp->bus == PCI) {
4142: if (lp->chipset == DC21040) {
4143: while ((tmp = inl(DE4X5_APROM)) < 0);
4144: k += (u_char) tmp;
4145: dev->dev_addr[i++] = (u_char) tmp;
4146: while ((tmp = inl(DE4X5_APROM)) < 0);
4147: k += (u_short) (tmp << 8);
4148: dev->dev_addr[i++] = (u_char) tmp;
4149: } else if (!broken) {
4150: dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4151: dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4152: } else if ((broken == SMC) || (broken == ACCTON)) {
4153: dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4154: dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4155: }
4156: } else {
4157: k += (u_char) (tmp = inb(EISA_APROM));
4158: dev->dev_addr[i++] = (u_char) tmp;
4159: k += (u_short) ((tmp = inb(EISA_APROM)) << 8);
4160: dev->dev_addr[i++] = (u_char) tmp;
4161: }
4162:
4163: if (k > 0xffff) k-=0xffff;
4164: }
4165: if (k == 0xffff) k=0;
4166:
4167: if (lp->bus == PCI) {
4168: if (lp->chipset == DC21040) {
4169: while ((tmp = inl(DE4X5_APROM)) < 0);
4170: chksum = (u_char) tmp;
4171: while ((tmp = inl(DE4X5_APROM)) < 0);
4172: chksum |= (u_short) (tmp << 8);
4173: if ((k != chksum) && (dec_only)) status = -1;
4174: }
4175: } else {
4176: chksum = (u_char) inb(EISA_APROM);
4177: chksum |= (u_short) (inb(EISA_APROM) << 8);
4178: if ((k != chksum) && (dec_only)) status = -1;
4179: }
4180:
4181: /* If possible, try to fix a broken card - SMC only so far */
4182: srom_repair(dev, broken);
4183:
4184: #ifdef CONFIG_PMAC
4185: /*
4186: ** If the address starts with 00 a0, we have to bit-reverse
4187: ** each byte of the address.
4188: */
4189: if (dev->dev_addr[0] == 0 && dev->dev_addr[1] == 0xa0) {
4190: for (i = 0; i < ETH_ALEN; ++i) {
4191: int x = dev->dev_addr[i];
4192: x = ((x & 0xf) << 4) + ((x & 0xf0) >> 4);
4193: x = ((x & 0x33) << 2) + ((x & 0xcc) >> 2);
4194: dev->dev_addr[i] = ((x & 0x55) << 1) + ((x & 0xaa) >> 1);
4195: }
4196: }
4197: #endif /* CONFIG_PMAC */
4198:
4199: /* Test for a bad enet address */
4200: status = test_bad_enet(dev, status);
4201:
4202: return status;
4203: }
4204:
4205: /*
4206: ** Test for enet addresses in the first 32 bytes. The built-in strncmp
4207: ** didn't seem to work here...?
4208: */
4209: static int
4210: de4x5_bad_srom(struct bus_type *lp)
4211: {
4212: int i, status = 0;
4213:
4214: for (i=0; i<sizeof(enet_det)/ETH_ALEN; i++) {
4215: if (!de4x5_strncmp((char *)&lp->srom, (char *)&enet_det[i], 3) &&
4216: !de4x5_strncmp((char *)&lp->srom+0x10, (char *)&enet_det[i], 3)) {
4217: if (i == 0) {
4218: status = SMC;
4219: } else if (i == 1) {
4220: status = ACCTON;
4221: }
4222: break;
4223: }
4224: }
4225:
4226: return status;
4227: }
4228:
4229: static int
4230: de4x5_strncmp(char *a, char *b, int n)
4231: {
4232: int ret=0;
4233:
4234: for (;n && !ret;n--) {
4235: ret = *a++ - *b++;
4236: }
4237:
4238: return ret;
4239: }
4240:
4241: static void
4242: srom_repair(struct device *dev, int card)
4243: {
4244: struct bus_type *lp = &bus;
4245:
4246: switch(card) {
4247: case SMC:
4248: memset((char *)&bus.srom, 0, sizeof(struct de4x5_srom));
4249: memcpy(lp->srom.ieee_addr, (char *)dev->dev_addr, ETH_ALEN);
4250: memcpy(lp->srom.info, (char *)&srom_repair_info[SMC-1], 100);
4251: useSROM = TRUE;
4252: break;
4253: }
4254:
4255: return;
4256: }
4257:
4258: /*
4259: ** Assume that the irq's do not follow the PCI spec - this is seems
4260: ** to be true so far (2 for 2).
4261: */
4262: static int
4263: test_bad_enet(struct device *dev, int status)
4264: {
4265: struct bus_type *lp = &bus;
4266: int i, tmp;
4267:
4268: for (tmp=0,i=0; i<ETH_ALEN; i++) tmp += (u_char)dev->dev_addr[i];
4269: if ((tmp == 0) || (tmp == 0x5fa)) {
4270: if ((lp->chipset == last.chipset) &&
4271: (lp->bus_num == last.bus) && (lp->bus_num > 0)) {
4272: for (i=0; i<ETH_ALEN; i++) dev->dev_addr[i] = last.addr[i];
4273: for (i=ETH_ALEN-1; i>2; --i) {
4274: dev->dev_addr[i] += 1;
4275: if (dev->dev_addr[i] != 0) break;
4276: }
4277: for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4278: if (!an_exception(lp)) {
4279: dev->irq = last.irq;
4280: }
4281:
4282: status = 0;
4283: }
4284: } else if (!status) {
4285: last.chipset = lp->chipset;
4286: last.bus = lp->bus_num;
4287: last.irq = dev->irq;
4288: for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4289: }
4290:
4291: return status;
4292: }
4293:
4294: /*
4295: ** List of board exceptions with correctly wired IRQs
4296: */
4297: static int
4298: an_exception(struct bus_type *lp)
4299: {
4300: if ((*(u_short *)lp->srom.sub_vendor_id == 0x00c0) &&
4301: (*(u_short *)lp->srom.sub_system_id == 0x95e0)) {
4302: return -1;
4303: }
4304:
4305: return 0;
4306: }
4307:
4308: /*
4309: ** SROM Read
4310: */
4311: static short
4312: srom_rd(u_long addr, u_char offset)
4313: {
4314: sendto_srom(SROM_RD | SROM_SR, addr);
4315:
4316: srom_latch(SROM_RD | SROM_SR | DT_CS, addr);
4317: srom_command(SROM_RD | SROM_SR | DT_IN | DT_CS, addr);
4318: srom_address(SROM_RD | SROM_SR | DT_CS, addr, offset);
4319:
4320: return srom_data(SROM_RD | SROM_SR | DT_CS, addr);
4321: }
4322:
4323: static void
4324: srom_latch(u_int command, u_long addr)
4325: {
4326: sendto_srom(command, addr);
4327: sendto_srom(command | DT_CLK, addr);
4328: sendto_srom(command, addr);
4329:
4330: return;
4331: }
4332:
4333: static void
4334: srom_command(u_int command, u_long addr)
4335: {
4336: srom_latch(command, addr);
4337: srom_latch(command, addr);
4338: srom_latch((command & 0x0000ff00) | DT_CS, addr);
4339:
4340: return;
4341: }
4342:
4343: static void
4344: srom_address(u_int command, u_long addr, u_char offset)
4345: {
4346: int i;
4347: char a;
4348:
4349: a = (char)(offset << 2);
4350: for (i=0; i<6; i++, a <<= 1) {
4351: srom_latch(command | ((a < 0) ? DT_IN : 0), addr);
4352: }
4353: de4x5_us_delay(1);
4354:
4355: i = (getfrom_srom(addr) >> 3) & 0x01;
4356:
4357: return;
4358: }
4359:
4360: static short
4361: srom_data(u_int command, u_long addr)
4362: {
4363: int i;
4364: short word = 0;
4365: s32 tmp;
4366:
4367: for (i=0; i<16; i++) {
4368: sendto_srom(command | DT_CLK, addr);
4369: tmp = getfrom_srom(addr);
4370: sendto_srom(command, addr);
4371:
4372: word = (word << 1) | ((tmp >> 3) & 0x01);
4373: }
4374:
4375: sendto_srom(command & 0x0000ff00, addr);
4376:
4377: return word;
4378: }
4379:
4380: /*
4381: static void
4382: srom_busy(u_int command, u_long addr)
4383: {
4384: sendto_srom((command & 0x0000ff00) | DT_CS, addr);
4385:
4386: while (!((getfrom_srom(addr) >> 3) & 0x01)) {
4387: de4x5_ms_delay(1);
4388: }
4389:
4390: sendto_srom(command & 0x0000ff00, addr);
4391:
4392: return;
4393: }
4394: */
4395:
4396: static void
4397: sendto_srom(u_int command, u_long addr)
4398: {
4399: outl(command, addr);
4400: udelay(1);
4401:
4402: return;
4403: }
4404:
4405: static int
4406: getfrom_srom(u_long addr)
4407: {
4408: s32 tmp;
4409:
4410: tmp = inl(addr);
4411: udelay(1);
4412:
4413: return tmp;
4414: }
4415:
4416: static int
4417: srom_infoleaf_info(struct device *dev)
4418: {
4419: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4420: int i, count;
4421: u_char *p;
4422:
4423: /* Find the infoleaf decoder function that matches this chipset */
4424: for (i=0; i<INFOLEAF_SIZE; i++) {
4425: if (lp->chipset == infoleaf_array[i].chipset) break;
4426: }
4427: if (i == INFOLEAF_SIZE) {
4428: lp->useSROM = FALSE;
4429: printk("%s: Cannot find correct chipset for SROM decoding!\n",
4430: dev->name);
4431: return -ENXIO;
4432: }
4433:
4434: lp->infoleaf_fn = infoleaf_array[i].fn;
4435:
4436: /* Find the information offset that this function should use */
4437: count = *((u_char *)&lp->srom + 19);
4438: p = (u_char *)&lp->srom + 26;
4439:
4440: if (count > 1) {
4441: for (i=count; i; --i, p+=3) {
4442: if (lp->device == *p) break;
4443: }
4444: if (i == 0) {
4445: lp->useSROM = FALSE;
4446: printk("%s: Cannot find correct PCI device [%d] for SROM decoding!\n",
4447: dev->name, lp->device);
4448: return -ENXIO;
4449: }
4450: }
4451:
4452: lp->infoleaf_offset = TWIDDLE(p+1);
4453:
4454: return 0;
4455: }
4456:
4457: /*
4458: ** This routine loads any type 1 or 3 MII info into the mii device
4459: ** struct and executes any type 5 code to reset PHY devices for this
4460: ** controller.
4461: ** The info for the MII devices will be valid since the index used
4462: ** will follow the discovery process from MII address 1-31 then 0.
4463: */
4464: static void
4465: srom_init(struct device *dev)
4466: {
4467: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4468: u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4469: u_char count;
4470:
4471: p+=2;
4472: if (lp->chipset == DC21140) {
4473: lp->cache.gepc = (*p++ | GEP_CTRL);
4474: gep_wr(lp->cache.gepc, dev);
4475: }
4476:
4477: /* Block count */
4478: count = *p++;
4479:
4480: /* Jump the infoblocks to find types */
4481: for (;count; --count) {
4482: if (*p < 128) {
4483: p += COMPACT_LEN;
4484: } else if (*(p+1) == 5) {
4485: type5_infoblock(dev, 1, p);
4486: p += ((*p & BLOCK_LEN) + 1);
4487: } else if (*(p+1) == 4) {
4488: p += ((*p & BLOCK_LEN) + 1);
4489: } else if (*(p+1) == 3) {
4490: type3_infoblock(dev, 1, p);
4491: p += ((*p & BLOCK_LEN) + 1);
4492: } else if (*(p+1) == 2) {
4493: p += ((*p & BLOCK_LEN) + 1);
4494: } else if (*(p+1) == 1) {
4495: type1_infoblock(dev, 1, p);
4496: p += ((*p & BLOCK_LEN) + 1);
4497: } else {
4498: p += ((*p & BLOCK_LEN) + 1);
4499: }
4500: }
4501:
4502: return;
4503: }
4504:
4505: /*
4506: ** A generic routine that writes GEP control, data and reset information
4507: ** to the GEP register (21140) or csr15 GEP portion (2114[23]).
4508: */
4509: static void
4510: srom_exec(struct device *dev, u_char *p)
4511: {
4512: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4513: u_long iobase = dev->base_addr;
4514: u_char count = (p ? *p++ : 0);
4515: u_short *w = (u_short *)p;
4516:
4517: if (((lp->ibn != 1) && (lp->ibn != 3) && (lp->ibn != 5)) || !count) return;
4518:
4519: if (lp->chipset != DC21140) RESET_SIA;
4520:
4521: while (count--) {
4522: gep_wr(((lp->chipset==DC21140) && (lp->ibn!=5) ?
4523: *p++ : TWIDDLE(w++)), dev);
4524: udelay(2000); /* 2ms per action */
4525: }
4526:
4527: if (lp->chipset != DC21140) {
4528: outl(lp->cache.csr14, DE4X5_STRR);
4529: outl(lp->cache.csr13, DE4X5_SICR);
4530: }
4531:
4532: return;
4533: }
4534:
4535: /*
4536: ** Basically this function is a NOP since it will never be called,
4537: ** unless I implement the DC21041 SROM functions. There's no need
4538: ** since the existing code will be satisfactory for all boards.
4539: */
4540: static int
4541: dc21041_infoleaf(struct device *dev)
4542: {
4543: return DE4X5_AUTOSENSE_MS;
4544: }
4545:
4546: static int
4547: dc21140_infoleaf(struct device *dev)
4548: {
4549: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4550: u_char count = 0;
4551: u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4552: int next_tick = DE4X5_AUTOSENSE_MS;
4553:
4554: /* Read the connection type */
4555: p+=2;
4556:
4557: /* GEP control */
4558: lp->cache.gepc = (*p++ | GEP_CTRL);
4559:
4560: /* Block count */
4561: count = *p++;
4562:
4563: /* Recursively figure out the info blocks */
4564: if (*p < 128) {
4565: next_tick = dc_infoblock[COMPACT](dev, count, p);
4566: } else {
4567: next_tick = dc_infoblock[*(p+1)](dev, count, p);
4568: }
4569:
4570: if (lp->tcount == count) {
4571: lp->media = NC;
4572: if (lp->media != lp->c_media) {
4573: de4x5_dbg_media(dev);
4574: lp->c_media = lp->media;
4575: }
4576: lp->media = INIT;
4577: lp->tcount = 0;
4578: lp->tx_enable = FALSE;
4579: }
4580:
4581: return next_tick & ~TIMER_CB;
4582: }
4583:
4584: static int
4585: dc21142_infoleaf(struct device *dev)
4586: {
4587: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4588: u_char count = 0;
4589: u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4590: int next_tick = DE4X5_AUTOSENSE_MS;
4591:
4592: /* Read the connection type */
4593: p+=2;
4594:
4595: /* Block count */
4596: count = *p++;
4597:
4598: /* Recursively figure out the info blocks */
4599: if (*p < 128) {
4600: next_tick = dc_infoblock[COMPACT](dev, count, p);
4601: } else {
4602: next_tick = dc_infoblock[*(p+1)](dev, count, p);
4603: }
4604:
4605: if (lp->tcount == count) {
4606: lp->media = NC;
4607: if (lp->media != lp->c_media) {
4608: de4x5_dbg_media(dev);
4609: lp->c_media = lp->media;
4610: }
4611: lp->media = INIT;
4612: lp->tcount = 0;
4613: lp->tx_enable = FALSE;
4614: }
4615:
4616: return next_tick & ~TIMER_CB;
4617: }
4618:
4619: static int
4620: dc21143_infoleaf(struct device *dev)
4621: {
4622: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4623: u_char count = 0;
4624: u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4625: int next_tick = DE4X5_AUTOSENSE_MS;
4626:
4627: /* Read the connection type */
4628: p+=2;
4629:
4630: /* Block count */
4631: count = *p++;
4632:
4633: /* Recursively figure out the info blocks */
4634: if (*p < 128) {
4635: next_tick = dc_infoblock[COMPACT](dev, count, p);
4636: } else {
4637: next_tick = dc_infoblock[*(p+1)](dev, count, p);
4638: }
4639: if (lp->tcount == count) {
4640: lp->media = NC;
4641: if (lp->media != lp->c_media) {
4642: de4x5_dbg_media(dev);
4643: lp->c_media = lp->media;
4644: }
4645: lp->media = INIT;
4646: lp->tcount = 0;
4647: lp->tx_enable = FALSE;
4648: }
4649:
4650: return next_tick & ~TIMER_CB;
4651: }
4652:
4653: /*
4654: ** The compact infoblock is only designed for DC21140[A] chips, so
4655: ** we'll reuse the dc21140m_autoconf function. Non MII media only.
4656: */
4657: static int
4658: compact_infoblock(struct device *dev, u_char count, u_char *p)
4659: {
4660: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4661: u_char flags, csr6;
4662:
4663: /* Recursively figure out the info blocks */
4664: if (--count > lp->tcount) {
4665: if (*(p+COMPACT_LEN) < 128) {
4666: return dc_infoblock[COMPACT](dev, count, p+COMPACT_LEN);
4667: } else {
4668: return dc_infoblock[*(p+COMPACT_LEN+1)](dev, count, p+COMPACT_LEN);
4669: }
4670: }
4671:
4672: if ((lp->media == INIT) && (lp->timeout < 0)) {
4673: lp->ibn = COMPACT;
4674: lp->active = 0;
4675: gep_wr(lp->cache.gepc, dev);
4676: lp->infoblock_media = (*p++) & COMPACT_MC;
4677: lp->cache.gep = *p++;
4678: csr6 = *p++;
4679: flags = *p++;
4680:
4681: lp->asBitValid = (flags & 0x80) ? 0 : -1;
4682: lp->defMedium = (flags & 0x40) ? -1 : 0;
4683: lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4684: lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4685: lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4686: lp->useMII = FALSE;
4687:
4688: de4x5_switch_mac_port(dev);
4689: }
4690:
4691: return dc21140m_autoconf(dev);
4692: }
4693:
4694: /*
4695: ** This block describes non MII media for the DC21140[A] only.
4696: */
4697: static int
4698: type0_infoblock(struct device *dev, u_char count, u_char *p)
4699: {
4700: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4701: u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4702:
4703: /* Recursively figure out the info blocks */
4704: if (--count > lp->tcount) {
4705: if (*(p+len) < 128) {
4706: return dc_infoblock[COMPACT](dev, count, p+len);
4707: } else {
4708: return dc_infoblock[*(p+len+1)](dev, count, p+len);
4709: }
4710: }
4711:
4712: if ((lp->media == INIT) && (lp->timeout < 0)) {
4713: lp->ibn = 0;
4714: lp->active = 0;
4715: gep_wr(lp->cache.gepc, dev);
4716: p+=2;
4717: lp->infoblock_media = (*p++) & BLOCK0_MC;
4718: lp->cache.gep = *p++;
4719: csr6 = *p++;
4720: flags = *p++;
4721:
4722: lp->asBitValid = (flags & 0x80) ? 0 : -1;
4723: lp->defMedium = (flags & 0x40) ? -1 : 0;
4724: lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4725: lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4726: lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4727: lp->useMII = FALSE;
4728:
4729: de4x5_switch_mac_port(dev);
4730: }
4731:
4732: return dc21140m_autoconf(dev);
4733: }
4734:
4735: /* These functions are under construction! */
4736:
4737: static int
4738: type1_infoblock(struct device *dev, u_char count, u_char *p)
4739: {
4740: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4741: u_char len = (*p & BLOCK_LEN)+1;
4742:
4743: /* Recursively figure out the info blocks */
4744: if (--count > lp->tcount) {
4745: if (*(p+len) < 128) {
4746: return dc_infoblock[COMPACT](dev, count, p+len);
4747: } else {
4748: return dc_infoblock[*(p+len+1)](dev, count, p+len);
4749: }
4750: }
4751:
4752: p += 2;
4753: if (lp->state == INITIALISED) {
4754: lp->ibn = 1;
4755: lp->active = *p++;
4756: lp->phy[lp->active].gep = (*p ? p : 0); p += (*p + 1);
4757: lp->phy[lp->active].rst = (*p ? p : 0); p += (*p + 1);
4758: lp->phy[lp->active].mc = TWIDDLE(p); p += 2;
4759: lp->phy[lp->active].ana = TWIDDLE(p); p += 2;
4760: lp->phy[lp->active].fdx = TWIDDLE(p); p += 2;
4761: lp->phy[lp->active].ttm = TWIDDLE(p);
4762: return 0;
4763: } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4764: lp->ibn = 1;
4765: lp->active = *p;
4766: lp->infoblock_csr6 = OMR_MII_100;
4767: lp->useMII = TRUE;
4768: lp->infoblock_media = ANS;
4769:
4770: de4x5_switch_mac_port(dev);
4771: }
4772:
4773: return dc21140m_autoconf(dev);
4774: }
4775:
4776: static int
4777: type2_infoblock(struct device *dev, u_char count, u_char *p)
4778: {
4779: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4780: u_char len = (*p & BLOCK_LEN)+1;
4781:
4782: /* Recursively figure out the info blocks */
4783: if (--count > lp->tcount) {
4784: if (*(p+len) < 128) {
4785: return dc_infoblock[COMPACT](dev, count, p+len);
4786: } else {
4787: return dc_infoblock[*(p+len+1)](dev, count, p+len);
4788: }
4789: }
4790:
4791: if ((lp->media == INIT) && (lp->timeout < 0)) {
4792: lp->ibn = 2;
4793: lp->active = 0;
4794: p += 2;
4795: lp->infoblock_media = (*p) & MEDIA_CODE;
4796:
4797: if ((*p++) & EXT_FIELD) {
4798: lp->cache.csr13 = TWIDDLE(p); p += 2;
4799: lp->cache.csr14 = TWIDDLE(p); p += 2;
4800: lp->cache.csr15 = TWIDDLE(p); p += 2;
4801: } else {
4802: lp->cache.csr13 = CSR13;
4803: lp->cache.csr14 = CSR14;
4804: lp->cache.csr15 = CSR15;
4805: }
4806: lp->cache.gepc = ((s32)(TWIDDLE(p)) << 16); p += 2;
4807: lp->cache.gep = ((s32)(TWIDDLE(p)) << 16);
4808: lp->infoblock_csr6 = OMR_SIA;
4809: lp->useMII = FALSE;
4810:
4811: de4x5_switch_mac_port(dev);
4812: }
4813:
4814: return dc2114x_autoconf(dev);
4815: }
4816:
4817: static int
4818: type3_infoblock(struct device *dev, u_char count, u_char *p)
4819: {
4820: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4821: u_char len = (*p & BLOCK_LEN)+1;
4822:
4823: /* Recursively figure out the info blocks */
4824: if (--count > lp->tcount) {
4825: if (*(p+len) < 128) {
4826: return dc_infoblock[COMPACT](dev, count, p+len);
4827: } else {
4828: return dc_infoblock[*(p+len+1)](dev, count, p+len);
4829: }
4830: }
4831:
4832: p += 2;
4833: if (lp->state == INITIALISED) {
4834: lp->ibn = 3;
4835: lp->active = *p++;
4836: lp->phy[lp->active].gep = (*p ? p : 0); p += (2 * (*p) + 1);
4837: lp->phy[lp->active].rst = (*p ? p : 0); p += (2 * (*p) + 1);
4838: lp->phy[lp->active].mc = TWIDDLE(p); p += 2;
4839: lp->phy[lp->active].ana = TWIDDLE(p); p += 2;
4840: lp->phy[lp->active].fdx = TWIDDLE(p); p += 2;
4841: lp->phy[lp->active].ttm = TWIDDLE(p); p += 2;
4842: lp->phy[lp->active].mci = *p;
4843: return 0;
4844: } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4845: lp->ibn = 3;
4846: lp->active = *p;
4847: lp->infoblock_csr6 = OMR_MII_100;
4848: lp->useMII = TRUE;
4849: lp->infoblock_media = ANS;
4850:
4851: de4x5_switch_mac_port(dev);
4852: }
4853:
4854: return dc2114x_autoconf(dev);
4855: }
4856:
4857: static int
4858: type4_infoblock(struct device *dev, u_char count, u_char *p)
4859: {
4860: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4861: u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4862:
4863: /* Recursively figure out the info blocks */
4864: if (--count > lp->tcount) {
4865: if (*(p+len) < 128) {
4866: return dc_infoblock[COMPACT](dev, count, p+len);
4867: } else {
4868: return dc_infoblock[*(p+len+1)](dev, count, p+len);
4869: }
4870: }
4871:
4872: if ((lp->media == INIT) && (lp->timeout < 0)) {
4873: lp->ibn = 4;
4874: lp->active = 0;
4875: p+=2;
4876: lp->infoblock_media = (*p++) & MEDIA_CODE;
4877: lp->cache.csr13 = CSR13; /* Hard coded defaults */
4878: lp->cache.csr14 = CSR14;
4879: lp->cache.csr15 = CSR15;
4880: lp->cache.gepc = ((s32)(TWIDDLE(p)) << 16); p += 2;
4881: lp->cache.gep = ((s32)(TWIDDLE(p)) << 16); p += 2;
4882: csr6 = *p++;
4883: flags = *p++;
4884:
4885: lp->asBitValid = (flags & 0x80) ? 0 : -1;
4886: lp->defMedium = (flags & 0x40) ? -1 : 0;
4887: lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4888: lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4889: lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4890: lp->useMII = FALSE;
4891:
4892: de4x5_switch_mac_port(dev);
4893: }
4894:
4895: return dc2114x_autoconf(dev);
4896: }
4897:
4898: /*
4899: ** This block type provides information for resetting external devices
4900: ** (chips) through the General Purpose Register.
4901: */
4902: static int
4903: type5_infoblock(struct device *dev, u_char count, u_char *p)
4904: {
4905: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4906: u_char len = (*p & BLOCK_LEN)+1;
4907:
4908: /* Recursively figure out the info blocks */
4909: if (--count > lp->tcount) {
4910: if (*(p+len) < 128) {
4911: return dc_infoblock[COMPACT](dev, count, p+len);
4912: } else {
4913: return dc_infoblock[*(p+len+1)](dev, count, p+len);
4914: }
4915: }
4916:
4917: /* Must be initializing to run this code */
4918: if ((lp->state == INITIALISED) || (lp->media == INIT)) {
4919: p+=2;
4920: lp->rst = p;
4921: srom_exec(dev, lp->rst);
4922: }
4923:
4924: return DE4X5_AUTOSENSE_MS;
4925: }
4926:
4927: /*
4928: ** MII Read/Write
4929: */
4930:
4931: static int
4932: mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr)
4933: {
4934: mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4935: mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4936: mii_wdata(MII_STRD, 4, ioaddr); /* SFD and Read operation */
4937: mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4938: mii_address(phyreg, ioaddr); /* PHY Register to read */
4939: mii_ta(MII_STRD, ioaddr); /* Turn around time - 2 MDC */
4940:
4941: return mii_rdata(ioaddr); /* Read data */
4942: }
4943:
4944: static void
4945: mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr)
4946: {
4947: mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4948: mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4949: mii_wdata(MII_STWR, 4, ioaddr); /* SFD and Write operation */
4950: mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4951: mii_address(phyreg, ioaddr); /* PHY Register to write */
4952: mii_ta(MII_STWR, ioaddr); /* Turn around time - 2 MDC */
4953: data = mii_swap(data, 16); /* Swap data bit ordering */
4954: mii_wdata(data, 16, ioaddr); /* Write data */
4955:
4956: return;
4957: }
4958:
4959: static int
4960: mii_rdata(u_long ioaddr)
4961: {
4962: int i;
4963: s32 tmp = 0;
4964:
4965: for (i=0; i<16; i++) {
4966: tmp <<= 1;
4967: tmp |= getfrom_mii(MII_MRD | MII_RD, ioaddr);
4968: }
4969:
4970: return tmp;
4971: }
4972:
4973: static void
4974: mii_wdata(int data, int len, u_long ioaddr)
4975: {
4976: int i;
4977:
4978: for (i=0; i<len; i++) {
4979: sendto_mii(MII_MWR | MII_WR, data, ioaddr);
4980: data >>= 1;
4981: }
4982:
4983: return;
4984: }
4985:
4986: static void
4987: mii_address(u_char addr, u_long ioaddr)
4988: {
4989: int i;
4990:
4991: addr = mii_swap(addr, 5);
4992: for (i=0; i<5; i++) {
4993: sendto_mii(MII_MWR | MII_WR, addr, ioaddr);
4994: addr >>= 1;
4995: }
4996:
4997: return;
4998: }
4999:
5000: static void
5001: mii_ta(u_long rw, u_long ioaddr)
5002: {
5003: if (rw == MII_STWR) {
5004: sendto_mii(MII_MWR | MII_WR, 1, ioaddr);
5005: sendto_mii(MII_MWR | MII_WR, 0, ioaddr);
5006: } else {
5007: getfrom_mii(MII_MRD | MII_RD, ioaddr); /* Tri-state MDIO */
5008: }
5009:
5010: return;
5011: }
5012:
5013: static int
5014: mii_swap(int data, int len)
5015: {
5016: int i, tmp = 0;
5017:
5018: for (i=0; i<len; i++) {
5019: tmp <<= 1;
5020: tmp |= (data & 1);
5021: data >>= 1;
5022: }
5023:
5024: return tmp;
5025: }
5026:
5027: static void
5028: sendto_mii(u32 command, int data, u_long ioaddr)
5029: {
5030: u32 j;
5031:
5032: j = (data & 1) << 17;
5033: outl(command | j, ioaddr);
5034: udelay(1);
5035: outl(command | MII_MDC | j, ioaddr);
5036: udelay(1);
5037:
5038: return;
5039: }
5040:
5041: static int
5042: getfrom_mii(u32 command, u_long ioaddr)
5043: {
5044: outl(command, ioaddr);
5045: udelay(1);
5046: outl(command | MII_MDC, ioaddr);
5047: udelay(1);
5048:
5049: return ((inl(ioaddr) >> 19) & 1);
5050: }
5051:
5052: /*
5053: ** Here's 3 ways to calculate the OUI from the ID registers.
5054: */
5055: static int
5056: mii_get_oui(u_char phyaddr, u_long ioaddr)
5057: {
5058: /*
5059: union {
5060: u_short reg;
5061: u_char breg[2];
5062: } a;
5063: int i, r2, r3, ret=0;*/
5064: int r2, r3;
5065:
5066: /* Read r2 and r3 */
5067: r2 = mii_rd(MII_ID0, phyaddr, ioaddr);
5068: r3 = mii_rd(MII_ID1, phyaddr, ioaddr);
5069: /* SEEQ and Cypress way * /
5070: / * Shuffle r2 and r3 * /
5071: a.reg=0;
5072: r3 = ((r3>>10)|(r2<<6))&0x0ff;
5073: r2 = ((r2>>2)&0x3fff);
5074:
5075: / * Bit reverse r3 * /
5076: for (i=0;i<8;i++) {
5077: ret<<=1;
5078: ret |= (r3&1);
5079: r3>>=1;
5080: }
5081:
5082: / * Bit reverse r2 * /
5083: for (i=0;i<16;i++) {
5084: a.reg<<=1;
5085: a.reg |= (r2&1);
5086: r2>>=1;
5087: }
5088:
5089: / * Swap r2 bytes * /
5090: i=a.breg[0];
5091: a.breg[0]=a.breg[1];
5092: a.breg[1]=i;
5093:
5094: return ((a.reg<<8)|ret); */ /* SEEQ and Cypress way */
5095: /* return ((r2<<6)|(u_int)(r3>>10)); */ /* NATIONAL and BROADCOM way */
5096: return r2; /* (I did it) My way */
5097: }
5098:
5099: /*
5100: ** The SROM spec forces us to search addresses [1-31 0]. Bummer.
5101: */
5102: static int
5103: mii_get_phy(struct device *dev)
5104: {
5105: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5106: u_long iobase = dev->base_addr;
5107: int i, j, k, n, limit=sizeof(phy_info)/sizeof(struct phy_table);
5108: int id;
5109:
5110: lp->active = 0;
5111: lp->useMII = TRUE;
5112:
5113: /* Search the MII address space for possible PHY devices */
1.1.1.2 ! root 5114: for (n=0, lp->mii_cnt=0, i=1; !((i==1) && (n==1)); i=(i+1)%DE4X5_MAX_MII) {
1.1 root 5115: lp->phy[lp->active].addr = i;
5116: if (i==0) n++; /* Count cycles */
5117: while (de4x5_reset_phy(dev)<0) udelay(100);/* Wait for reset */
5118: id = mii_get_oui(i, DE4X5_MII);
5119: if ((id == 0) || (id == 65535)) continue; /* Valid ID? */
5120: for (j=0; j<limit; j++) { /* Search PHY table */
5121: if (id != phy_info[j].id) continue; /* ID match? */
5122: for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++);
5123: if (k < DE4X5_MAX_PHY) {
5124: memcpy((char *)&lp->phy[k],
5125: (char *)&phy_info[j], sizeof(struct phy_table));
5126: lp->phy[k].addr = i;
5127: lp->mii_cnt++;
5128: lp->active++;
5129: } else {
5130: goto purgatory; /* Stop the search */
5131: }
5132: break;
5133: }
5134: if ((j == limit) && (i < DE4X5_MAX_MII)) {
5135: for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++);
5136: lp->phy[k].addr = i;
5137: lp->phy[k].id = id;
5138: lp->phy[k].spd.reg = GENERIC_REG; /* ANLPA register */
5139: lp->phy[k].spd.mask = GENERIC_MASK; /* 100Mb/s technologies */
5140: lp->phy[k].spd.value = GENERIC_VALUE; /* TX & T4, H/F Duplex */
5141: lp->mii_cnt++;
5142: lp->active++;
5143: printk("%s: Using generic MII device control. If the board doesn't operate, \nplease mail the following dump to the author:\n", dev->name);
5144: j = de4x5_debug;
5145: de4x5_debug |= DEBUG_MII;
5146: de4x5_dbg_mii(dev, k);
5147: de4x5_debug = j;
5148: printk("\n");
5149: }
5150: }
5151: purgatory:
5152: lp->active = 0;
5153: if (lp->phy[0].id) { /* Reset the PHY devices */
5154: for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++) { /*For each PHY*/
5155: mii_wr(MII_CR_RST, MII_CR, lp->phy[k].addr, DE4X5_MII);
5156: while (mii_rd(MII_CR, lp->phy[k].addr, DE4X5_MII) & MII_CR_RST);
5157:
5158: de4x5_dbg_mii(dev, k);
5159: }
5160: }
5161: if (!lp->mii_cnt) lp->useMII = FALSE;
5162:
5163: return lp->mii_cnt;
5164: }
5165:
5166: static char *
5167: build_setup_frame(struct device *dev, int mode)
5168: {
5169: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5170: int i;
5171: char *pa = lp->setup_frame;
5172:
5173: /* Initialise the setup frame */
5174: if (mode == ALL) {
5175: memset(lp->setup_frame, 0, SETUP_FRAME_LEN);
5176: }
5177:
5178: if (lp->setup_f == HASH_PERF) {
5179: for (pa=lp->setup_frame+IMPERF_PA_OFFSET, i=0; i<ETH_ALEN; i++) {
5180: *(pa + i) = dev->dev_addr[i]; /* Host address */
5181: if (i & 0x01) pa += 2;
5182: }
5183: *(lp->setup_frame + (HASH_TABLE_LEN >> 3) - 3) = 0x80;
5184: } else {
5185: for (i=0; i<ETH_ALEN; i++) { /* Host address */
5186: *(pa + (i&1)) = dev->dev_addr[i];
5187: if (i & 0x01) pa += 4;
5188: }
5189: for (i=0; i<ETH_ALEN; i++) { /* Broadcast address */
5190: *(pa + (i&1)) = (char) 0xff;
5191: if (i & 0x01) pa += 4;
5192: }
5193: }
5194:
5195: return pa; /* Points to the next entry */
5196: }
5197:
5198: static void
5199: enable_ast(struct device *dev, u32 time_out)
5200: {
5201: timeout(dev, (void *)&de4x5_ast, (u_long)dev, time_out);
5202:
5203: return;
5204: }
5205:
5206: static void
5207: disable_ast(struct device *dev)
5208: {
5209: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5210:
5211: del_timer(&lp->timer);
5212:
5213: return;
5214: }
5215:
5216: static long
5217: de4x5_switch_mac_port(struct device *dev)
5218: {
5219: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5220: u_long iobase = dev->base_addr;
5221: s32 omr;
5222:
5223: STOP_DE4X5;
5224:
5225: /* Assert the OMR_PS bit in CSR6 */
5226: omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR |
5227: OMR_FDX));
5228: omr |= lp->infoblock_csr6;
5229: if (omr & OMR_PS) omr |= OMR_HBD;
5230: outl(omr, DE4X5_OMR);
5231:
5232: /* Soft Reset */
5233: RESET_DE4X5;
5234:
5235: /* Restore the GEP - especially for COMPACT and Type 0 Infoblocks */
5236: if (lp->chipset == DC21140) {
5237: gep_wr(lp->cache.gepc, dev);
5238: gep_wr(lp->cache.gep, dev);
5239: } else if ((lp->chipset & ~0x0ff) == DC2114x) {
5240: reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14, lp->cache.csr15);
5241: }
5242:
5243: /* Restore CSR6 */
5244: outl(omr, DE4X5_OMR);
5245:
5246: /* Reset CSR8 */
5247: inl(DE4X5_MFC);
5248:
5249: return omr;
5250: }
5251:
5252: static void
5253: gep_wr(s32 data, struct device *dev)
5254: {
5255: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5256: u_long iobase = dev->base_addr;
5257:
5258: if (lp->chipset == DC21140) {
5259: outl(data, DE4X5_GEP);
5260: } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5261: outl((data<<16) | lp->cache.csr15, DE4X5_SIGR);
5262: }
5263:
5264: return;
5265: }
5266:
5267: static int
5268: gep_rd(struct device *dev)
5269: {
5270: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5271: u_long iobase = dev->base_addr;
5272:
5273: if (lp->chipset == DC21140) {
5274: return inl(DE4X5_GEP);
5275: } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5276: return (inl(DE4X5_SIGR) & 0x000fffff);
5277: }
5278:
5279: return 0;
5280: }
5281:
5282: static void
5283: timeout(struct device *dev, void (*fn)(u_long data), u_long data, u_long msec)
5284: {
5285: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5286: int dt;
5287:
5288: /* First, cancel any pending timer events */
5289: del_timer(&lp->timer);
5290:
5291: /* Convert msec to ticks */
5292: dt = (msec * HZ) / 1000;
5293: if (dt==0) dt=1;
5294:
5295: /* Set up timer */
5296: lp->timer.expires = jiffies + dt;
5297: lp->timer.function = fn;
5298: lp->timer.data = data;
5299: add_timer(&lp->timer);
5300:
5301: return;
5302: }
5303:
5304: static void
5305: yawn(struct device *dev, int state)
5306: {
5307: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5308: u_long iobase = dev->base_addr;
5309:
5310: if ((lp->chipset == DC21040) || (lp->chipset == DC21140)) return;
5311:
5312: if(lp->bus == EISA) {
5313: switch(state) {
5314: case WAKEUP:
5315: outb(WAKEUP, PCI_CFPM);
5316: de4x5_ms_delay(10);
5317: break;
5318:
5319: case SNOOZE:
5320: outb(SNOOZE, PCI_CFPM);
5321: break;
5322:
5323: case SLEEP:
5324: outl(0, DE4X5_SICR);
5325: outb(SLEEP, PCI_CFPM);
5326: break;
5327: }
5328: } else {
5329: switch(state) {
5330: case WAKEUP:
5331: pcibios_write_config_byte(lp->bus_num, lp->device << 3,
5332: PCI_CFDA_PSM, WAKEUP);
5333: de4x5_ms_delay(10);
5334: break;
5335:
5336: case SNOOZE:
5337: pcibios_write_config_byte(lp->bus_num, lp->device << 3,
5338: PCI_CFDA_PSM, SNOOZE);
5339: break;
5340:
5341: case SLEEP:
5342: outl(0, DE4X5_SICR);
5343: pcibios_write_config_byte(lp->bus_num, lp->device << 3,
5344: PCI_CFDA_PSM, SLEEP);
5345: break;
5346: }
5347: }
5348:
5349: return;
5350: }
5351:
5352: static void
5353: de4x5_parse_params(struct device *dev)
5354: {
5355: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5356: char *p, *q, t;
5357:
5358: lp->params.fdx = 0;
5359: lp->params.autosense = AUTO;
5360:
5361: if (args == NULL) return;
5362:
5363: if ((p = strstr(args, dev->name))) {
5364: if (!(q = strstr(p+strlen(dev->name), "eth"))) q = p + strlen(p);
5365: t = *q;
5366: *q = '\0';
5367:
5368: if (strstr(p, "fdx") || strstr(p, "FDX")) lp->params.fdx = 1;
5369:
5370: if (strstr(p, "autosense") || strstr(p, "AUTOSENSE")) {
5371: if (strstr(p, "TP")) {
5372: lp->params.autosense = TP;
5373: } else if (strstr(p, "TP_NW")) {
5374: lp->params.autosense = TP_NW;
5375: } else if (strstr(p, "BNC")) {
5376: lp->params.autosense = BNC;
5377: } else if (strstr(p, "AUI")) {
5378: lp->params.autosense = AUI;
5379: } else if (strstr(p, "BNC_AUI")) {
5380: lp->params.autosense = BNC;
5381: } else if (strstr(p, "10Mb")) {
5382: lp->params.autosense = _10Mb;
5383: } else if (strstr(p, "100Mb")) {
5384: lp->params.autosense = _100Mb;
5385: } else if (strstr(p, "AUTO")) {
5386: lp->params.autosense = AUTO;
5387: }
5388: }
5389: *q = t;
5390: }
5391:
5392: return;
5393: }
5394:
5395: static void
5396: de4x5_dbg_open(struct device *dev)
5397: {
5398: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5399: int i;
5400:
5401: if (de4x5_debug & DEBUG_OPEN) {
5402: printk("%s: de4x5 opening with irq %d\n",dev->name,dev->irq);
5403: printk("\tphysical address: ");
5404: for (i=0;i<6;i++) {
5405: printk("%2.2x:",(short)dev->dev_addr[i]);
5406: }
5407: printk("\n");
5408: printk("Descriptor head addresses:\n");
5409: printk("\t0x%8.8lx 0x%8.8lx\n",(u_long)lp->rx_ring,(u_long)lp->tx_ring);
5410: printk("Descriptor addresses:\nRX: ");
5411: for (i=0;i<lp->rxRingSize-1;i++){
5412: if (i < 3) {
5413: printk("0x%8.8lx ",(u_long)&lp->rx_ring[i].status);
5414: }
5415: }
5416: printk("...0x%8.8lx\n",(u_long)&lp->rx_ring[i].status);
5417: printk("TX: ");
5418: for (i=0;i<lp->txRingSize-1;i++){
5419: if (i < 3) {
5420: printk("0x%8.8lx ", (u_long)&lp->tx_ring[i].status);
5421: }
5422: }
5423: printk("...0x%8.8lx\n", (u_long)&lp->tx_ring[i].status);
5424: printk("Descriptor buffers:\nRX: ");
5425: for (i=0;i<lp->rxRingSize-1;i++){
5426: if (i < 3) {
5427: printk("0x%8.8x ",le32_to_cpu(lp->rx_ring[i].buf));
5428: }
5429: }
5430: printk("...0x%8.8x\n",le32_to_cpu(lp->rx_ring[i].buf));
5431: printk("TX: ");
5432: for (i=0;i<lp->txRingSize-1;i++){
5433: if (i < 3) {
5434: printk("0x%8.8x ", le32_to_cpu(lp->tx_ring[i].buf));
5435: }
5436: }
5437: printk("...0x%8.8x\n", le32_to_cpu(lp->tx_ring[i].buf));
5438: printk("Ring size: \nRX: %d\nTX: %d\n",
5439: (short)lp->rxRingSize,
5440: (short)lp->txRingSize);
5441: }
5442:
5443: return;
5444: }
5445:
5446: static void
5447: de4x5_dbg_mii(struct device *dev, int k)
5448: {
5449: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5450: u_long iobase = dev->base_addr;
5451:
5452: if (de4x5_debug & DEBUG_MII) {
5453: printk("\nMII device address: %d\n", lp->phy[k].addr);
5454: printk("MII CR: %x\n",mii_rd(MII_CR,lp->phy[k].addr,DE4X5_MII));
5455: printk("MII SR: %x\n",mii_rd(MII_SR,lp->phy[k].addr,DE4X5_MII));
5456: printk("MII ID0: %x\n",mii_rd(MII_ID0,lp->phy[k].addr,DE4X5_MII));
5457: printk("MII ID1: %x\n",mii_rd(MII_ID1,lp->phy[k].addr,DE4X5_MII));
5458: if (lp->phy[k].id != BROADCOM_T4) {
5459: printk("MII ANA: %x\n",mii_rd(0x04,lp->phy[k].addr,DE4X5_MII));
5460: printk("MII ANC: %x\n",mii_rd(0x05,lp->phy[k].addr,DE4X5_MII));
5461: }
5462: printk("MII 16: %x\n",mii_rd(0x10,lp->phy[k].addr,DE4X5_MII));
5463: if (lp->phy[k].id != BROADCOM_T4) {
5464: printk("MII 17: %x\n",mii_rd(0x11,lp->phy[k].addr,DE4X5_MII));
5465: printk("MII 18: %x\n",mii_rd(0x12,lp->phy[k].addr,DE4X5_MII));
5466: } else {
5467: printk("MII 20: %x\n",mii_rd(0x14,lp->phy[k].addr,DE4X5_MII));
5468: }
5469: }
5470:
5471: return;
5472: }
5473:
5474: static void
5475: de4x5_dbg_media(struct device *dev)
5476: {
5477: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5478:
5479: if (lp->media != lp->c_media) {
5480: if (de4x5_debug & DEBUG_MEDIA) {
5481: printk("%s: media is %s%s\n", dev->name,
5482: (lp->media == NC ? "unconnected, link down or incompatible connection" :
5483: (lp->media == TP ? "TP" :
5484: (lp->media == ANS ? "TP/Nway" :
5485: (lp->media == BNC ? "BNC" :
5486: (lp->media == AUI ? "AUI" :
5487: (lp->media == BNC_AUI ? "BNC/AUI" :
5488: (lp->media == EXT_SIA ? "EXT SIA" :
5489: (lp->media == _100Mb ? "100Mb/s" :
5490: (lp->media == _10Mb ? "10Mb/s" :
5491: "???"
5492: ))))))))), (lp->fdx?" full duplex.":"."));
5493: }
5494: lp->c_media = lp->media;
5495: }
5496:
5497: return;
5498: }
5499:
5500: static void
5501: de4x5_dbg_srom(struct de4x5_srom *p)
5502: {
5503: int i;
5504:
5505: if (de4x5_debug & DEBUG_SROM) {
5506: printk("Sub-system Vendor ID: %04x\n", *((u_short *)p->sub_vendor_id));
5507: printk("Sub-system ID: %04x\n", *((u_short *)p->sub_system_id));
5508: printk("ID Block CRC: %02x\n", (u_char)(p->id_block_crc));
5509: printk("SROM version: %02x\n", (u_char)(p->version));
5510: printk("# controllers: %02x\n", (u_char)(p->num_controllers));
5511:
5512: printk("Hardware Address: ");
5513: for (i=0;i<ETH_ALEN-1;i++) {
5514: printk("%02x:", (u_char)*(p->ieee_addr+i));
5515: }
5516: printk("%02x\n", (u_char)*(p->ieee_addr+i));
5517: printk("CRC checksum: %04x\n", (u_short)(p->chksum));
5518: for (i=0; i<64; i++) {
5519: printk("%3d %04x\n", i<<1, (u_short)*((u_short *)p+i));
5520: }
5521: }
5522:
5523: return;
5524: }
5525:
5526: static void
5527: de4x5_dbg_rx(struct sk_buff *skb, int len)
5528: {
5529: int i, j;
5530:
5531: if (de4x5_debug & DEBUG_RX) {
5532: printk("R: %02x:%02x:%02x:%02x:%02x:%02x <- %02x:%02x:%02x:%02x:%02x:%02x len/SAP:%02x%02x [%d]\n",
5533: (u_char)skb->data[0],
5534: (u_char)skb->data[1],
5535: (u_char)skb->data[2],
5536: (u_char)skb->data[3],
5537: (u_char)skb->data[4],
5538: (u_char)skb->data[5],
5539: (u_char)skb->data[6],
5540: (u_char)skb->data[7],
5541: (u_char)skb->data[8],
5542: (u_char)skb->data[9],
5543: (u_char)skb->data[10],
5544: (u_char)skb->data[11],
5545: (u_char)skb->data[12],
5546: (u_char)skb->data[13],
5547: len);
5548: if (de4x5_debug & DEBUG_RX) {
5549: for (j=0; len>0;j+=16, len-=16) {
5550: printk(" %03x: ",j);
5551: for (i=0; i<16 && i<len; i++) {
5552: printk("%02x ",(u_char)skb->data[i+j]);
5553: }
5554: printk("\n");
5555: }
5556: }
5557: }
5558:
5559: return;
5560: }
5561:
5562: /*
5563: ** Perform IOCTL call functions here. Some are privileged operations and the
5564: ** effective uid is checked in those cases. In the normal course of events
5565: ** this function is only used for my testing.
5566: */
5567: static int
5568: de4x5_ioctl(struct device *dev, struct ifreq *rq, int cmd)
5569: {
5570: struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5571: struct de4x5_ioctl *ioc = (struct de4x5_ioctl *) &rq->ifr_data;
5572: u_long iobase = dev->base_addr;
5573: int i, j, status = 0;
5574: s32 omr;
5575: union {
5576: u8 addr[144];
5577: u16 sval[72];
5578: u32 lval[36];
5579: } tmp;
5580:
5581: switch(ioc->cmd) {
5582: case DE4X5_GET_HWADDR: /* Get the hardware address */
5583: ioc->len = ETH_ALEN;
5584: status = verify_area(VERIFY_WRITE, (void *)ioc->data, ioc->len);
5585: if (status)
5586: break;
5587: for (i=0; i<ETH_ALEN; i++) {
5588: tmp.addr[i] = dev->dev_addr[i];
5589: }
5590: copy_to_user(ioc->data, tmp.addr, ioc->len);
5591:
5592: break;
5593: case DE4X5_SET_HWADDR: /* Set the hardware address */
5594: status = verify_area(VERIFY_READ, (void *)ioc->data, ETH_ALEN);
5595: if (status)
5596: break;
5597: status = -EPERM;
5598: if (!suser())
5599: break;
5600: status = 0;
5601: copy_from_user(tmp.addr, ioc->data, ETH_ALEN);
5602: for (i=0; i<ETH_ALEN; i++) {
5603: dev->dev_addr[i] = tmp.addr[i];
5604: }
5605: build_setup_frame(dev, PHYS_ADDR_ONLY);
5606: /* Set up the descriptor and give ownership to the card */
5607: while (test_and_set_bit(0, (void *)&dev->tbusy) != 0);
5608: load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
5609: SETUP_FRAME_LEN, NULL);
1.1.1.2 ! root 5610: lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
1.1 root 5611: outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
5612: dev->tbusy = 0; /* Unlock the TX ring */
5613:
5614: break;
5615: case DE4X5_SET_PROM: /* Set Promiscuous Mode */
5616: if (suser()) {
5617: omr = inl(DE4X5_OMR);
5618: omr |= OMR_PR;
5619: outl(omr, DE4X5_OMR);
5620: dev->flags |= IFF_PROMISC;
5621: } else {
5622: status = -EPERM;
5623: }
5624:
5625: break;
5626: case DE4X5_CLR_PROM: /* Clear Promiscuous Mode */
5627: if (suser()) {
5628: omr = inl(DE4X5_OMR);
5629: omr &= ~OMR_PR;
5630: outb(omr, DE4X5_OMR);
5631: dev->flags &= ~IFF_PROMISC;
5632: } else {
5633: status = -EPERM;
5634: }
5635:
5636: break;
5637: case DE4X5_SAY_BOO: /* Say "Boo!" to the kernel log file */
5638: printk("%s: Boo!\n", dev->name);
5639:
5640: break;
5641: case DE4X5_MCA_EN: /* Enable pass all multicast addressing */
5642: if (suser()) {
5643: omr = inl(DE4X5_OMR);
5644: omr |= OMR_PM;
5645: outl(omr, DE4X5_OMR);
5646: } else {
5647: status = -EPERM;
5648: }
5649:
5650: break;
5651: case DE4X5_GET_STATS: /* Get the driver statistics */
5652: ioc->len = sizeof(lp->pktStats);
5653: status = verify_area(VERIFY_WRITE, (void *)ioc->data, ioc->len);
5654: if (status)
5655: break;
5656:
5657: cli();
5658: copy_to_user(ioc->data, &lp->pktStats, ioc->len);
5659: sti();
5660:
5661: break;
5662: case DE4X5_CLR_STATS: /* Zero out the driver statistics */
5663: if (suser()) {
5664: cli();
5665: memset(&lp->pktStats, 0, sizeof(lp->pktStats));
5666: sti();
5667: } else {
5668: status = -EPERM;
5669: }
5670:
5671: break;
5672: case DE4X5_GET_OMR: /* Get the OMR Register contents */
5673: tmp.addr[0] = inl(DE4X5_OMR);
5674: if (!(status = verify_area(VERIFY_WRITE, (void *)ioc->data, 1))) {
5675: copy_to_user(ioc->data, tmp.addr, 1);
5676: }
5677:
5678: break;
5679: case DE4X5_SET_OMR: /* Set the OMR Register contents */
5680: if (suser()) {
5681: if (!(status = verify_area(VERIFY_READ, (void *)ioc->data, 1))) {
5682: copy_from_user(tmp.addr, ioc->data, 1);
5683: outl(tmp.addr[0], DE4X5_OMR);
5684: }
5685: } else {
5686: status = -EPERM;
5687: }
5688:
5689: break;
5690: case DE4X5_GET_REG: /* Get the DE4X5 Registers */
5691: j = 0;
5692: tmp.lval[0] = inl(DE4X5_STS); j+=4;
5693: tmp.lval[1] = inl(DE4X5_BMR); j+=4;
5694: tmp.lval[2] = inl(DE4X5_IMR); j+=4;
5695: tmp.lval[3] = inl(DE4X5_OMR); j+=4;
5696: tmp.lval[4] = inl(DE4X5_SISR); j+=4;
5697: tmp.lval[5] = inl(DE4X5_SICR); j+=4;
5698: tmp.lval[6] = inl(DE4X5_STRR); j+=4;
5699: tmp.lval[7] = inl(DE4X5_SIGR); j+=4;
5700: ioc->len = j;
5701: if (!(status = verify_area(VERIFY_WRITE, (void *)ioc->data, ioc->len))) {
5702: copy_to_user(ioc->data, tmp.addr, ioc->len);
5703: }
5704: break;
5705:
5706: #define DE4X5_DUMP 0x0f /* Dump the DE4X5 Status */
5707: /*
5708: case DE4X5_DUMP:
5709: j = 0;
5710: tmp.addr[j++] = dev->irq;
5711: for (i=0; i<ETH_ALEN; i++) {
5712: tmp.addr[j++] = dev->dev_addr[i];
5713: }
5714: tmp.addr[j++] = lp->rxRingSize;
5715: tmp.lval[j>>2] = (long)lp->rx_ring; j+=4;
5716: tmp.lval[j>>2] = (long)lp->tx_ring; j+=4;
5717:
5718: for (i=0;i<lp->rxRingSize-1;i++){
5719: if (i < 3) {
5720: tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5721: }
5722: }
5723: tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5724: for (i=0;i<lp->txRingSize-1;i++){
5725: if (i < 3) {
5726: tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5727: }
5728: }
5729: tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5730:
5731: for (i=0;i<lp->rxRingSize-1;i++){
5732: if (i < 3) {
5733: tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5734: }
5735: }
5736: tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5737: for (i=0;i<lp->txRingSize-1;i++){
5738: if (i < 3) {
5739: tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5740: }
5741: }
5742: tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5743:
5744: for (i=0;i<lp->rxRingSize;i++){
5745: tmp.lval[j>>2] = le32_to_cpu(lp->rx_ring[i].status); j+=4;
5746: }
5747: for (i=0;i<lp->txRingSize;i++){
5748: tmp.lval[j>>2] = le32_to_cpu(lp->tx_ring[i].status); j+=4;
5749: }
5750:
5751: tmp.lval[j>>2] = inl(DE4X5_BMR); j+=4;
5752: tmp.lval[j>>2] = inl(DE4X5_TPD); j+=4;
5753: tmp.lval[j>>2] = inl(DE4X5_RPD); j+=4;
5754: tmp.lval[j>>2] = inl(DE4X5_RRBA); j+=4;
5755: tmp.lval[j>>2] = inl(DE4X5_TRBA); j+=4;
5756: tmp.lval[j>>2] = inl(DE4X5_STS); j+=4;
5757: tmp.lval[j>>2] = inl(DE4X5_OMR); j+=4;
5758: tmp.lval[j>>2] = inl(DE4X5_IMR); j+=4;
5759: tmp.lval[j>>2] = lp->chipset; j+=4;
5760: if (lp->chipset == DC21140) {
5761: tmp.lval[j>>2] = gep_rd(dev); j+=4;
5762: } else {
5763: tmp.lval[j>>2] = inl(DE4X5_SISR); j+=4;
5764: tmp.lval[j>>2] = inl(DE4X5_SICR); j+=4;
5765: tmp.lval[j>>2] = inl(DE4X5_STRR); j+=4;
5766: tmp.lval[j>>2] = inl(DE4X5_SIGR); j+=4;
5767: }
5768: tmp.lval[j>>2] = lp->phy[lp->active].id; j+=4;
5769: if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
5770: tmp.lval[j>>2] = lp->active; j+=4;
5771: tmp.lval[j>>2]=mii_rd(MII_CR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5772: tmp.lval[j>>2]=mii_rd(MII_SR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5773: tmp.lval[j>>2]=mii_rd(MII_ID0,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5774: tmp.lval[j>>2]=mii_rd(MII_ID1,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5775: if (lp->phy[lp->active].id != BROADCOM_T4) {
5776: tmp.lval[j>>2]=mii_rd(MII_ANA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5777: tmp.lval[j>>2]=mii_rd(MII_ANLPA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5778: }
5779: tmp.lval[j>>2]=mii_rd(0x10,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5780: if (lp->phy[lp->active].id != BROADCOM_T4) {
5781: tmp.lval[j>>2]=mii_rd(0x11,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5782: tmp.lval[j>>2]=mii_rd(0x12,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5783: } else {
5784: tmp.lval[j>>2]=mii_rd(0x14,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5785: }
5786: }
5787:
5788: tmp.addr[j++] = lp->txRingSize;
5789: tmp.addr[j++] = dev->tbusy;
5790:
5791: ioc->len = j;
5792: if (!(status = verify_area(VERIFY_WRITE, (void *)ioc->data, ioc->len))) {
5793: copy_to_user(ioc->data, tmp.addr, ioc->len);
5794: }
5795:
5796: break;
5797: */
5798: default:
5799: status = -EOPNOTSUPP;
5800: }
5801:
5802: return status;
5803: }
5804:
5805: #ifdef MODULE
5806: /*
5807: ** Note now that module autoprobing is allowed under EISA and PCI. The
5808: ** IRQ lines will not be auto-detected; instead I'll rely on the BIOSes
5809: ** to "do the right thing".
5810: */
5811: #define LP(a) ((struct de4x5_private *)(a))
5812: static struct device *mdev = NULL;
5813: static int io=0x0;/* EDIT THIS LINE FOR YOUR CONFIGURATION IF NEEDED */
5814: #if LINUX_VERSION_CODE >= LinuxVersionCode(2,1,0)
5815: MODULE_PARM(io, "i");
5816: #endif /* LINUX_VERSION_CODE */
5817:
5818: int
5819: init_module(void)
5820: {
5821: int i, num, status = -EIO;
5822: struct device *p;
5823:
5824: num = count_adapters();
5825:
5826: for (i=0; i<num; i++) {
5827: if ((p = insert_device(NULL, io, de4x5_probe)) == NULL)
5828: return -ENOMEM;
5829:
5830: if (!mdev) mdev = p;
5831:
5832: if (register_netdev(p) != 0) {
5833: kfree(p);
5834: } else {
5835: status = 0; /* At least one adapter will work */
5836: lastModule = p;
5837: }
5838: }
5839:
5840: return status;
5841: }
5842:
5843: void
5844: cleanup_module(void)
5845: {
5846: while (mdev != NULL) {
5847: mdev = unlink_modules(mdev);
5848: }
5849:
5850: return;
5851: }
5852:
5853: static struct device *
5854: unlink_modules(struct device *p)
5855: {
5856: struct device *next = NULL;
5857:
5858: if (p->priv) { /* Private areas allocated? */
5859: struct de4x5_private *lp = (struct de4x5_private *)p->priv;
5860:
5861: next = lp->next_module;
5862: if (lp->cache.buf) { /* MAC buffers allocated? */
5863: kfree(lp->cache.buf); /* Free the MAC buffers */
5864: }
5865: kfree(lp->cache.priv); /* Free the private area */
5866: release_region(p->base_addr, (lp->bus == PCI ?
5867: DE4X5_PCI_TOTAL_SIZE :
5868: DE4X5_EISA_TOTAL_SIZE));
5869: }
5870: unregister_netdev(p);
5871: kfree(p); /* Free the device structure */
5872:
5873: return next;
5874: }
5875:
5876: static int
5877: count_adapters(void)
5878: {
5879: int i, j=0;
5880: u_char pb, dev_fn, dev_num;
5881: u_short dev_id, vendor;
5882: u_int class = DE4X5_CLASS_CODE;
5883: u_int device;
5884:
5885: #if !defined(__sparc_v9__) && !defined(__powerpc__) && !defined(__alpha__)
5886: char name[DE4X5_STRLEN];
5887: u_long iobase = 0x1000;
5888:
5889: for (i=1; i<MAX_EISA_SLOTS; i++, iobase+=EISA_SLOT_INC) {
5890: if (EISA_signature(name, EISA_ID)) j++;
5891: }
5892: #endif
5893: if (!pcibios_present()) return j;
5894:
5895: for (i=0;
5896: (pcibios_find_class(class, i, &pb, &dev_fn)!= PCIBIOS_DEVICE_NOT_FOUND);
5897: i++) {
5898: dev_num = PCI_SLOT(dev_fn);
5899: device = 0;
5900: pcibios_read_config_word(pb, PCI_DEVICE, PCI_VENDOR_ID, &vendor);
5901: pcibios_read_config_word(pb, PCI_DEVICE, PCI_DEVICE_ID, &dev_id);
5902: device = dev_id;
5903: device <<= 8;
5904: if (is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x) j++;
5905: }
5906:
5907: return j;
5908: }
5909:
5910: /*
5911: ** If at end of eth device list and can't use current entry, malloc
5912: ** one up. If memory could not be allocated, print an error message.
5913: */
5914: __initfunc(static struct device *
5915: insert_device(struct device *dev, u_long iobase, int (*init)(struct device *)))
5916: {
5917: struct device *new;
5918:
5919: new = (struct device *)kmalloc(sizeof(struct device)+8, GFP_KERNEL);
5920: if (new == NULL) {
5921: printk("de4x5.c: Device not initialised, insufficient memory\n");
5922: return NULL;
5923: } else {
5924: memset((char *)new, 0, sizeof(struct device)+8);
5925: new->name = (char *)(new + 1);
5926: new->base_addr = iobase; /* assign the io address */
5927: new->init = init; /* initialisation routine */
5928: }
5929:
5930: return new;
5931: }
5932:
5933: #endif /* MODULE */
5934:
5935:
5936: /*
5937: * Local variables:
5938: * compile-command: "gcc -D__KERNEL__ -I/linux/include -Wall -Wstrict-prototypes -fomit-frame-pointer -fno-strength-reduce -malign-loops=2 -malign-jumps=2 -malign-functions=2 -O2 -m486 -c de4x5.c"
5939: *
5940: * compile-command: "gcc -D__KERNEL__ -DMODULE -I/linux/include -Wall -Wstrict-prototypes -fomit-frame-pointer -fno-strength-reduce -malign-loops=2 -malign-jumps=2 -malign-functions=2 -O2 -m486 -c de4x5.c"
5941: * End:
5942: */
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