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1.1 ! root 1: /* ! 2: Copyright 1994 Digital Equipment Corporation. ! 3: ! 4: This software may be used and distributed according to the terms of the ! 5: GNU Public License, incorporated herein by reference. ! 6: ! 7: The author may be reached as [email protected] or Digital ! 8: Equipment Corporation, 550 King Street, Littleton MA 01460. ! 9: ! 10: ========================================================================= ! 11: */ ! 12: ! 13: /* ! 14: ** DC21040 CSR<1..15> Register Address Map ! 15: */ ! 16: #define DE4X5_BMR iobase+(0x000 << lp->bus) /* Bus Mode Register */ ! 17: #define DE4X5_TPD iobase+(0x008 << lp->bus) /* Transmit Poll Demand Reg */ ! 18: #define DE4X5_RPD iobase+(0x010 << lp->bus) /* Receive Poll Demand Reg */ ! 19: #define DE4X5_RRBA iobase+(0x018 << lp->bus) /* RX Ring Base Address Reg */ ! 20: #define DE4X5_TRBA iobase+(0x020 << lp->bus) /* TX Ring Base Address Reg */ ! 21: #define DE4X5_STS iobase+(0x028 << lp->bus) /* Status Register */ ! 22: #define DE4X5_OMR iobase+(0x030 << lp->bus) /* Operation Mode Register */ ! 23: #define DE4X5_IMR iobase+(0x038 << lp->bus) /* Interrupt Mask Register */ ! 24: #define DE4X5_MFC iobase+(0x040 << lp->bus) /* Missed Frame Counter */ ! 25: #define DE4X5_APROM iobase+(0x048 << lp->bus) /* Ethernet Address PROM */ ! 26: #define DE4X5_BROM iobase+(0x048 << lp->bus) /* Boot ROM Register */ ! 27: #define DE4X5_SROM iobase+(0x048 << lp->bus) /* Serial ROM Register */ ! 28: #define DE4X5_MII iobase+(0x048 << lp->bus) /* MII Interface Register */ ! 29: #define DE4X5_DDR iobase+(0x050 << lp->bus) /* Data Diagnostic Register */ ! 30: #define DE4X5_FDR iobase+(0x058 << lp->bus) /* Full Duplex Register */ ! 31: #define DE4X5_GPT iobase+(0x058 << lp->bus) /* General Purpose Timer Reg.*/ ! 32: #define DE4X5_GEP iobase+(0x060 << lp->bus) /* General Purpose Register */ ! 33: #define DE4X5_SISR iobase+(0x060 << lp->bus) /* SIA Status Register */ ! 34: #define DE4X5_SICR iobase+(0x068 << lp->bus) /* SIA Connectivity Register */ ! 35: #define DE4X5_STRR iobase+(0x070 << lp->bus) /* SIA TX/RX Register */ ! 36: #define DE4X5_SIGR iobase+(0x078 << lp->bus) /* SIA General Register */ ! 37: ! 38: /* ! 39: ** EISA Register Address Map ! 40: */ ! 41: #define EISA_ID iobase+0x0c80 /* EISA ID Registers */ ! 42: #define EISA_ID0 iobase+0x0c80 /* EISA ID Register 0 */ ! 43: #define EISA_ID1 iobase+0x0c81 /* EISA ID Register 1 */ ! 44: #define EISA_ID2 iobase+0x0c82 /* EISA ID Register 2 */ ! 45: #define EISA_ID3 iobase+0x0c83 /* EISA ID Register 3 */ ! 46: #define EISA_CR iobase+0x0c84 /* EISA Control Register */ ! 47: #define EISA_REG0 iobase+0x0c88 /* EISA Configuration Register 0 */ ! 48: #define EISA_REG1 iobase+0x0c89 /* EISA Configuration Register 1 */ ! 49: #define EISA_REG2 iobase+0x0c8a /* EISA Configuration Register 2 */ ! 50: #define EISA_REG3 iobase+0x0c8f /* EISA Configuration Register 3 */ ! 51: #define EISA_APROM iobase+0x0c90 /* Ethernet Address PROM */ ! 52: ! 53: /* ! 54: ** PCI/EISA Configuration Registers Address Map ! 55: */ ! 56: #define PCI_CFID iobase+0x0008 /* PCI Configuration ID Register */ ! 57: #define PCI_CFCS iobase+0x000c /* PCI Command/Status Register */ ! 58: #define PCI_CFRV iobase+0x0018 /* PCI Revision Register */ ! 59: #define PCI_CFLT iobase+0x001c /* PCI Latency Timer Register */ ! 60: #define PCI_CBIO iobase+0x0028 /* PCI Base I/O Register */ ! 61: #define PCI_CBMA iobase+0x002c /* PCI Base Memory Address Register */ ! 62: #define PCI_CBER iobase+0x0030 /* PCI Expansion ROM Base Address Reg. */ ! 63: #define PCI_CFIT iobase+0x003c /* PCI Configuration Interrupt Register */ ! 64: #define PCI_CFDA iobase+0x0040 /* PCI Driver Area Register */ ! 65: #define PCI_CFDD iobase+0x0041 /* PCI Driver Dependent Area Register */ ! 66: #define PCI_CFPM iobase+0x0043 /* PCI Power Management Area Register */ ! 67: ! 68: /* ! 69: ** EISA Configuration Register 0 bit definitions ! 70: */ ! 71: #define ER0_BSW 0x80 /* EISA Bus Slave Width, 1: 32 bits */ ! 72: #define ER0_BMW 0x40 /* EISA Bus Master Width, 1: 32 bits */ ! 73: #define ER0_EPT 0x20 /* EISA PREEMPT Time, 0: 23 BCLKs */ ! 74: #define ER0_ISTS 0x10 /* Interrupt Status (X) */ ! 75: #define ER0_LI 0x08 /* Latch Interrupts */ ! 76: #define ER0_INTL 0x06 /* INTerrupt Level */ ! 77: #define ER0_INTT 0x01 /* INTerrupt Type, 0: Level, 1: Edge */ ! 78: ! 79: /* ! 80: ** EISA Configuration Register 1 bit definitions ! 81: */ ! 82: #define ER1_IAM 0xe0 /* ISA Address Mode */ ! 83: #define ER1_IAE 0x10 /* ISA Addressing Enable */ ! 84: #define ER1_UPIN 0x0f /* User Pins */ ! 85: ! 86: /* ! 87: ** EISA Configuration Register 2 bit definitions ! 88: */ ! 89: #define ER2_BRS 0xc0 /* Boot ROM Size */ ! 90: #define ER2_BRA 0x3c /* Boot ROM Address <16:13> */ ! 91: ! 92: /* ! 93: ** EISA Configuration Register 3 bit definitions ! 94: */ ! 95: #define ER3_BWE 0x40 /* Burst Write Enable */ ! 96: #define ER3_BRE 0x04 /* Burst Read Enable */ ! 97: #define ER3_LSR 0x02 /* Local Software Reset */ ! 98: ! 99: /* ! 100: ** PCI Configuration ID Register (PCI_CFID). The Device IDs are left ! 101: ** shifted 8 bits to allow detection of DC21142 and DC21143 variants with ! 102: ** the configuration revision register step number. ! 103: */ ! 104: #define CFID_DID 0xff00 /* Device ID */ ! 105: #define CFID_VID 0x00ff /* Vendor ID */ ! 106: #define DC21040_DID 0x0200 /* Unique Device ID # */ ! 107: #define DC21040_VID 0x1011 /* DC21040 Manufacturer */ ! 108: #define DC21041_DID 0x1400 /* Unique Device ID # */ ! 109: #define DC21041_VID 0x1011 /* DC21041 Manufacturer */ ! 110: #define DC21140_DID 0x0900 /* Unique Device ID # */ ! 111: #define DC21140_VID 0x1011 /* DC21140 Manufacturer */ ! 112: #define DC2114x_DID 0x1900 /* Unique Device ID # */ ! 113: #define DC2114x_VID 0x1011 /* DC2114[23] Manufacturer */ ! 114: ! 115: /* ! 116: ** Chipset defines ! 117: */ ! 118: #define DC21040 DC21040_DID ! 119: #define DC21041 DC21041_DID ! 120: #define DC21140 DC21140_DID ! 121: #define DC2114x DC2114x_DID ! 122: #define DC21142 (DC2114x_DID | 0x0010) ! 123: #define DC21143 (DC2114x_DID | 0x0030) ! 124: ! 125: #define is_DC21040 ((vendor == DC21040_VID) && (device == DC21040_DID)) ! 126: #define is_DC21041 ((vendor == DC21041_VID) && (device == DC21041_DID)) ! 127: #define is_DC21140 ((vendor == DC21140_VID) && (device == DC21140_DID)) ! 128: #define is_DC2114x ((vendor == DC2114x_VID) && (device == DC2114x_DID)) ! 129: #define is_DC21142 ((vendor == DC2114x_VID) && (device == DC21142)) ! 130: #define is_DC21143 ((vendor == DC2114x_VID) && (device == DC21143)) ! 131: ! 132: /* ! 133: ** PCI Configuration Command/Status Register (PCI_CFCS) ! 134: */ ! 135: #define CFCS_DPE 0x80000000 /* Detected Parity Error (S) */ ! 136: #define CFCS_SSE 0x40000000 /* Signal System Error (S) */ ! 137: #define CFCS_RMA 0x20000000 /* Receive Master Abort (S) */ ! 138: #define CFCS_RTA 0x10000000 /* Receive Target Abort (S) */ ! 139: #define CFCS_DST 0x06000000 /* DEVSEL Timing (S) */ ! 140: #define CFCS_DPR 0x01000000 /* Data Parity Report (S) */ ! 141: #define CFCS_FBB 0x00800000 /* Fast Back-To-Back (S) */ ! 142: #define CFCS_SEE 0x00000100 /* System Error Enable (C) */ ! 143: #define CFCS_PER 0x00000040 /* Parity Error Response (C) */ ! 144: #define CFCS_MO 0x00000004 /* Master Operation (C) */ ! 145: #define CFCS_MSA 0x00000002 /* Memory Space Access (C) */ ! 146: #define CFCS_IOSA 0x00000001 /* I/O Space Access (C) */ ! 147: ! 148: /* ! 149: ** PCI Configuration Revision Register (PCI_CFRV) ! 150: */ ! 151: #define CFRV_BC 0xff000000 /* Base Class */ ! 152: #define CFRV_SC 0x00ff0000 /* Subclass */ ! 153: #define CFRV_RN 0x000000f0 /* Revision Number */ ! 154: #define CFRV_SN 0x0000000f /* Step Number */ ! 155: #define BASE_CLASS 0x02000000 /* Indicates Network Controller */ ! 156: #define SUB_CLASS 0x00000000 /* Indicates Ethernet Controller */ ! 157: #define STEP_NUMBER 0x00000020 /* Increments for future chips */ ! 158: #define REV_NUMBER 0x00000003 /* 0x00, 0x01, 0x02, 0x03: Rev in Step */ ! 159: #define CFRV_MASK 0xffff0000 /* Register mask */ ! 160: ! 161: /* ! 162: ** PCI Configuration Latency Timer Register (PCI_CFLT) ! 163: */ ! 164: #define CFLT_BC 0x0000ff00 /* Latency Timer bits */ ! 165: ! 166: /* ! 167: ** PCI Configuration Base I/O Address Register (PCI_CBIO) ! 168: */ ! 169: #define CBIO_MASK -128 /* Base I/O Address Mask */ ! 170: #define CBIO_IOSI 0x00000001 /* I/O Space Indicator (RO, value is 1) */ ! 171: ! 172: /* ! 173: ** PCI Configuration Card Information Structure Register (PCI_CCIS) ! 174: */ ! 175: #define CCIS_ROMI 0xf0000000 /* ROM Image */ ! 176: #define CCIS_ASO 0x0ffffff8 /* Address Space Offset */ ! 177: #define CCIS_ASI 0x00000007 /* Address Space Indicator */ ! 178: ! 179: /* ! 180: ** PCI Configuration Subsystem ID Register (PCI_SSID) ! 181: */ ! 182: #define SSID_SSID 0xffff0000 /* Subsystem ID */ ! 183: #define SSID_SVID 0x0000ffff /* Subsystem Vendor ID */ ! 184: ! 185: /* ! 186: ** PCI Configuration Expansion ROM Base Address Register (PCI_CBER) ! 187: */ ! 188: #define CBER_MASK 0xfffffc00 /* Expansion ROM Base Address Mask */ ! 189: #define CBER_ROME 0x00000001 /* ROM Enable */ ! 190: ! 191: /* ! 192: ** PCI Configuration Interrupt Register (PCI_CFIT) ! 193: */ ! 194: #define CFIT_MXLT 0xff000000 /* MAX_LAT Value (0.25us periods) */ ! 195: #define CFIT_MNGT 0x00ff0000 /* MIN_GNT Value (0.25us periods) */ ! 196: #define CFIT_IRQP 0x0000ff00 /* Interrupt Pin */ ! 197: #define CFIT_IRQL 0x000000ff /* Interrupt Line */ ! 198: ! 199: /* ! 200: ** PCI Configuration Power Management Area Register (PCI_CFPM) ! 201: */ ! 202: #define SLEEP 0x80 /* Power Saving Sleep Mode */ ! 203: #define SNOOZE 0x40 /* Power Saving Snooze Mode */ ! 204: #define WAKEUP 0x00 /* Power Saving Wakeup */ ! 205: ! 206: #define PCI_CFDA_DSU 0x41 /* 8 bit Configuration Space Address */ ! 207: #define PCI_CFDA_PSM 0x43 /* 8 bit Configuration Space Address */ ! 208: ! 209: /* ! 210: ** DC21040 Bus Mode Register (DE4X5_BMR) ! 211: */ ! 212: #define BMR_RML 0x00200000 /* [Memory] Read Multiple */ ! 213: #define BMR_DBO 0x00100000 /* Descriptor Byte Ordering (Endian) */ ! 214: #define BMR_TAP 0x000e0000 /* Transmit Automatic Polling */ ! 215: #define BMR_DAS 0x00010000 /* Diagnostic Address Space */ ! 216: #define BMR_CAL 0x0000c000 /* Cache Alignment */ ! 217: #define BMR_PBL 0x00003f00 /* Programmable Burst Length */ ! 218: #define BMR_BLE 0x00000080 /* Big/Little Endian */ ! 219: #define BMR_DSL 0x0000007c /* Descriptor Skip Length */ ! 220: #define BMR_BAR 0x00000002 /* Bus ARbitration */ ! 221: #define BMR_SWR 0x00000001 /* Software Reset */ ! 222: ! 223: /* Timings here are for 10BASE-T/AUI only*/ ! 224: #define TAP_NOPOLL 0x00000000 /* No automatic polling */ ! 225: #define TAP_200US 0x00020000 /* TX automatic polling every 200us */ ! 226: #define TAP_800US 0x00040000 /* TX automatic polling every 800us */ ! 227: #define TAP_1_6MS 0x00060000 /* TX automatic polling every 1.6ms */ ! 228: #define TAP_12_8US 0x00080000 /* TX automatic polling every 12.8us */ ! 229: #define TAP_25_6US 0x000a0000 /* TX automatic polling every 25.6us */ ! 230: #define TAP_51_2US 0x000c0000 /* TX automatic polling every 51.2us */ ! 231: #define TAP_102_4US 0x000e0000 /* TX automatic polling every 102.4us */ ! 232: ! 233: #define CAL_NOUSE 0x00000000 /* Not used */ ! 234: #define CAL_8LONG 0x00004000 /* 8-longword alignment */ ! 235: #define CAL_16LONG 0x00008000 /* 16-longword alignment */ ! 236: #define CAL_32LONG 0x0000c000 /* 32-longword alignment */ ! 237: ! 238: #define PBL_0 0x00000000 /* DMA burst length = amount in RX FIFO */ ! 239: #define PBL_1 0x00000100 /* 1 longword DMA burst length */ ! 240: #define PBL_2 0x00000200 /* 2 longwords DMA burst length */ ! 241: #define PBL_4 0x00000400 /* 4 longwords DMA burst length */ ! 242: #define PBL_8 0x00000800 /* 8 longwords DMA burst length */ ! 243: #define PBL_16 0x00001000 /* 16 longwords DMA burst length */ ! 244: #define PBL_32 0x00002000 /* 32 longwords DMA burst length */ ! 245: ! 246: #define DSL_0 0x00000000 /* 0 longword / descriptor */ ! 247: #define DSL_1 0x00000004 /* 1 longword / descriptor */ ! 248: #define DSL_2 0x00000008 /* 2 longwords / descriptor */ ! 249: #define DSL_4 0x00000010 /* 4 longwords / descriptor */ ! 250: #define DSL_8 0x00000020 /* 8 longwords / descriptor */ ! 251: #define DSL_16 0x00000040 /* 16 longwords / descriptor */ ! 252: #define DSL_32 0x00000080 /* 32 longwords / descriptor */ ! 253: ! 254: /* ! 255: ** DC21040 Transmit Poll Demand Register (DE4X5_TPD) ! 256: */ ! 257: #define TPD 0x00000001 /* Transmit Poll Demand */ ! 258: ! 259: /* ! 260: ** DC21040 Receive Poll Demand Register (DE4X5_RPD) ! 261: */ ! 262: #define RPD 0x00000001 /* Receive Poll Demand */ ! 263: ! 264: /* ! 265: ** DC21040 Receive Ring Base Address Register (DE4X5_RRBA) ! 266: */ ! 267: #define RRBA 0xfffffffc /* RX Descriptor List Start Address */ ! 268: ! 269: /* ! 270: ** DC21040 Transmit Ring Base Address Register (DE4X5_TRBA) ! 271: */ ! 272: #define TRBA 0xfffffffc /* TX Descriptor List Start Address */ ! 273: ! 274: /* ! 275: ** Status Register (DE4X5_STS) ! 276: */ ! 277: #define STS_GPI 0x04000000 /* General Purpose Port Interrupt */ ! 278: #define STS_BE 0x03800000 /* Bus Error Bits */ ! 279: #define STS_TS 0x00700000 /* Transmit Process State */ ! 280: #define STS_RS 0x000e0000 /* Receive Process State */ ! 281: #define STS_NIS 0x00010000 /* Normal Interrupt Summary */ ! 282: #define STS_AIS 0x00008000 /* Abnormal Interrupt Summary */ ! 283: #define STS_ER 0x00004000 /* Early Receive */ ! 284: #define STS_FBE 0x00002000 /* Fatal Bus Error */ ! 285: #define STS_SE 0x00002000 /* System Error */ ! 286: #define STS_LNF 0x00001000 /* Link Fail */ ! 287: #define STS_FD 0x00000800 /* Full-Duplex Short Frame Received */ ! 288: #define STS_TM 0x00000800 /* Timer Expired (DC21041) */ ! 289: #define STS_ETI 0x00000400 /* Early Transmit Interupt */ ! 290: #define STS_AT 0x00000400 /* AUI/TP Pin */ ! 291: #define STS_RWT 0x00000200 /* Receive Watchdog Time-Out */ ! 292: #define STS_RPS 0x00000100 /* Receive Process Stopped */ ! 293: #define STS_RU 0x00000080 /* Receive Buffer Unavailable */ ! 294: #define STS_RI 0x00000040 /* Receive Interrupt */ ! 295: #define STS_UNF 0x00000020 /* Transmit Underflow */ ! 296: #define STS_LNP 0x00000010 /* Link Pass */ ! 297: #define STS_ANC 0x00000010 /* Autonegotiation Complete */ ! 298: #define STS_TJT 0x00000008 /* Transmit Jabber Time-Out */ ! 299: #define STS_TU 0x00000004 /* Transmit Buffer Unavailable */ ! 300: #define STS_TPS 0x00000002 /* Transmit Process Stopped */ ! 301: #define STS_TI 0x00000001 /* Transmit Interrupt */ ! 302: ! 303: #define EB_PAR 0x00000000 /* Parity Error */ ! 304: #define EB_MA 0x00800000 /* Master Abort */ ! 305: #define EB_TA 0x01000000 /* Target Abort */ ! 306: #define EB_RES0 0x01800000 /* Reserved */ ! 307: #define EB_RES1 0x02000000 /* Reserved */ ! 308: ! 309: #define TS_STOP 0x00000000 /* Stopped */ ! 310: #define TS_FTD 0x00100000 /* Fetch Transmit Descriptor */ ! 311: #define TS_WEOT 0x00200000 /* Wait for End Of Transmission */ ! 312: #define TS_QDAT 0x00300000 /* Queue skb data into TX FIFO */ ! 313: #define TS_RES 0x00400000 /* Reserved */ ! 314: #define TS_SPKT 0x00500000 /* Setup Packet */ ! 315: #define TS_SUSP 0x00600000 /* Suspended */ ! 316: #define TS_CLTD 0x00700000 /* Close Transmit Descriptor */ ! 317: ! 318: #define RS_STOP 0x00000000 /* Stopped */ ! 319: #define RS_FRD 0x00020000 /* Fetch Receive Descriptor */ ! 320: #define RS_CEOR 0x00040000 /* Check for End of Receive Packet */ ! 321: #define RS_WFRP 0x00060000 /* Wait for Receive Packet */ ! 322: #define RS_SUSP 0x00080000 /* Suspended */ ! 323: #define RS_CLRD 0x000a0000 /* Close Receive Descriptor */ ! 324: #define RS_FLUSH 0x000c0000 /* Flush RX FIFO */ ! 325: #define RS_QRFS 0x000e0000 /* Queue RX FIFO into RX Skb */ ! 326: ! 327: #define INT_CANCEL 0x0001ffff /* For zeroing all interrupt sources */ ! 328: ! 329: /* ! 330: ** Operation Mode Register (DE4X5_OMR) ! 331: */ ! 332: #define OMR_SC 0x80000000 /* Special Capture Effect Enable */ ! 333: #define OMR_RA 0x40000000 /* Receive All */ ! 334: #define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */ ! 335: #define OMR_SCR 0x01000000 /* Scrambler Mode */ ! 336: #define OMR_PCS 0x00800000 /* PCS Function */ ! 337: #define OMR_TTM 0x00400000 /* Transmit Threshold Mode */ ! 338: #define OMR_SF 0x00200000 /* Store and Forward */ ! 339: #define OMR_HBD 0x00080000 /* HeartBeat Disable */ ! 340: #define OMR_PS 0x00040000 /* Port Select */ ! 341: #define OMR_CA 0x00020000 /* Capture Effect Enable */ ! 342: #define OMR_BP 0x00010000 /* Back Pressure */ ! 343: #define OMR_TR 0x0000c000 /* Threshold Control Bits */ ! 344: #define OMR_ST 0x00002000 /* Start/Stop Transmission Command */ ! 345: #define OMR_FC 0x00001000 /* Force Collision Mode */ ! 346: #define OMR_OM 0x00000c00 /* Operating Mode */ ! 347: #define OMR_FDX 0x00000200 /* Full Duplex Mode */ ! 348: #define OMR_FKD 0x00000100 /* Flaky Oscillator Disable */ ! 349: #define OMR_PM 0x00000080 /* Pass All Multicast */ ! 350: #define OMR_PR 0x00000040 /* Promiscuous Mode */ ! 351: #define OMR_SB 0x00000020 /* Start/Stop Backoff Counter */ ! 352: #define OMR_IF 0x00000010 /* Inverse Filtering */ ! 353: #define OMR_PB 0x00000008 /* Pass Bad Frames */ ! 354: #define OMR_HO 0x00000004 /* Hash Only Filtering Mode */ ! 355: #define OMR_SR 0x00000002 /* Start/Stop Receive */ ! 356: #define OMR_HP 0x00000001 /* Hash/Perfect Receive Filtering Mode */ ! 357: ! 358: #define TR_72 0x00000000 /* Threshold set to 72 (128) bytes */ ! 359: #define TR_96 0x00004000 /* Threshold set to 96 (256) bytes */ ! 360: #define TR_128 0x00008000 /* Threshold set to 128 (512) bytes */ ! 361: #define TR_160 0x0000c000 /* Threshold set to 160 (1024) bytes */ ! 362: ! 363: #define OMR_DEF (OMR_SDP) ! 364: #define OMR_SIA (OMR_SDP | OMR_TTM) ! 365: #define OMR_SYM (OMR_SDP | OMR_SCR | OMR_PCS | OMR_HBD | OMR_PS) ! 366: #define OMR_MII_10 (OMR_SDP | OMR_TTM | OMR_PS) ! 367: #define OMR_MII_100 (OMR_SDP | OMR_HBD | OMR_PS) ! 368: ! 369: /* ! 370: ** DC21040 Interrupt Mask Register (DE4X5_IMR) ! 371: */ ! 372: #define IMR_GPM 0x04000000 /* General Purpose Port Mask */ ! 373: #define IMR_NIM 0x00010000 /* Normal Interrupt Summary Mask */ ! 374: #define IMR_AIM 0x00008000 /* Abnormal Interrupt Summary Mask */ ! 375: #define IMR_ERM 0x00004000 /* Early Receive Mask */ ! 376: #define IMR_FBM 0x00002000 /* Fatal Bus Error Mask */ ! 377: #define IMR_SEM 0x00002000 /* System Error Mask */ ! 378: #define IMR_LFM 0x00001000 /* Link Fail Mask */ ! 379: #define IMR_FDM 0x00000800 /* Full-Duplex (Short Frame) Mask */ ! 380: #define IMR_TMM 0x00000800 /* Timer Expired Mask (DC21041) */ ! 381: #define IMR_ETM 0x00000400 /* Early Transmit Interrupt Mask */ ! 382: #define IMR_ATM 0x00000400 /* AUI/TP Switch Mask */ ! 383: #define IMR_RWM 0x00000200 /* Receive Watchdog Time-Out Mask */ ! 384: #define IMR_RSM 0x00000100 /* Receive Stopped Mask */ ! 385: #define IMR_RUM 0x00000080 /* Receive Buffer Unavailable Mask */ ! 386: #define IMR_RIM 0x00000040 /* Receive Interrupt Mask */ ! 387: #define IMR_UNM 0x00000020 /* Underflow Interrupt Mask */ ! 388: #define IMR_ANM 0x00000010 /* Autonegotiation Complete Mask */ ! 389: #define IMR_LPM 0x00000010 /* Link Pass */ ! 390: #define IMR_TJM 0x00000008 /* Transmit Time-Out Jabber Mask */ ! 391: #define IMR_TUM 0x00000004 /* Transmit Buffer Unavailable Mask */ ! 392: #define IMR_TSM 0x00000002 /* Transmission Stopped Mask */ ! 393: #define IMR_TIM 0x00000001 /* Transmit Interrupt Mask */ ! 394: ! 395: /* ! 396: ** Missed Frames and FIFO Overflow Counters (DE4X5_MFC) ! 397: */ ! 398: #define MFC_FOCO 0x10000000 /* FIFO Overflow Counter Overflow Bit */ ! 399: #define MFC_FOC 0x0ffe0000 /* FIFO Overflow Counter Bits */ ! 400: #define MFC_OVFL 0x00010000 /* Missed Frames Counter Overflow Bit */ ! 401: #define MFC_CNTR 0x0000ffff /* Missed Frames Counter Bits */ ! 402: #define MFC_FOCM 0x1ffe0000 /* FIFO Overflow Counter Mask */ ! 403: ! 404: /* ! 405: ** DC21040 Ethernet Address PROM (DE4X5_APROM) ! 406: */ ! 407: #define APROM_DN 0x80000000 /* Data Not Valid */ ! 408: #define APROM_DT 0x000000ff /* Address Byte */ ! 409: ! 410: /* ! 411: ** DC21041 Boot/Ethernet Address ROM (DE4X5_BROM) ! 412: */ ! 413: #define BROM_MODE 0x00008000 /* MODE_1: 0, MODE_0: 1 (read only) */ ! 414: #define BROM_RD 0x00004000 /* Read from Boot ROM */ ! 415: #define BROM_WR 0x00002000 /* Write to Boot ROM */ ! 416: #define BROM_BR 0x00001000 /* Select Boot ROM when set */ ! 417: #define BROM_SR 0x00000800 /* Select Serial ROM when set */ ! 418: #define BROM_REG 0x00000400 /* External Register Select */ ! 419: #define BROM_DT 0x000000ff /* Data Byte */ ! 420: ! 421: /* ! 422: ** DC21041 Serial/Ethernet Address ROM (DE4X5_SROM, DE4X5_MII) ! 423: */ ! 424: #define MII_MDI 0x00080000 /* MII Management Data In */ ! 425: #define MII_MDO 0x00060000 /* MII Management Mode/Data Out */ ! 426: #define MII_MRD 0x00040000 /* MII Management Define Read Mode */ ! 427: #define MII_MWR 0x00000000 /* MII Management Define Write Mode */ ! 428: #define MII_MDT 0x00020000 /* MII Management Data Out */ ! 429: #define MII_MDC 0x00010000 /* MII Management Clock */ ! 430: #define MII_RD 0x00004000 /* Read from MII */ ! 431: #define MII_WR 0x00002000 /* Write to MII */ ! 432: #define MII_SEL 0x00000800 /* Select MII when RESET */ ! 433: ! 434: #define SROM_MODE 0x00008000 /* MODE_1: 0, MODE_0: 1 (read only) */ ! 435: #define SROM_RD 0x00004000 /* Read from Boot ROM */ ! 436: #define SROM_WR 0x00002000 /* Write to Boot ROM */ ! 437: #define SROM_BR 0x00001000 /* Select Boot ROM when set */ ! 438: #define SROM_SR 0x00000800 /* Select Serial ROM when set */ ! 439: #define SROM_REG 0x00000400 /* External Register Select */ ! 440: #define SROM_DT 0x000000ff /* Data Byte */ ! 441: ! 442: #define DT_OUT 0x00000008 /* Serial Data Out */ ! 443: #define DT_IN 0x00000004 /* Serial Data In */ ! 444: #define DT_CLK 0x00000002 /* Serial ROM Clock */ ! 445: #define DT_CS 0x00000001 /* Serial ROM Chip Select */ ! 446: ! 447: #define MII_PREAMBLE 0xffffffff /* MII Management Preamble */ ! 448: #define MII_TEST 0xaaaaaaaa /* MII Test Signal */ ! 449: #define MII_STRD 0x06 /* Start of Frame+Op Code: use low nibble */ ! 450: #define MII_STWR 0x0a /* Start of Frame+Op Code: use low nibble */ ! 451: ! 452: #define MII_CR 0x00 /* MII Management Control Register */ ! 453: #define MII_SR 0x01 /* MII Management Status Register */ ! 454: #define MII_ID0 0x02 /* PHY Identifier Register 0 */ ! 455: #define MII_ID1 0x03 /* PHY Identifier Register 1 */ ! 456: #define MII_ANA 0x04 /* Auto Negotiation Advertisement */ ! 457: #define MII_ANLPA 0x05 /* Auto Negotiation Link Partner Ability */ ! 458: #define MII_ANE 0x06 /* Auto Negotiation Expansion */ ! 459: #define MII_ANP 0x07 /* Auto Negotiation Next Page TX */ ! 460: ! 461: #define DE4X5_MAX_MII 32 /* Maximum address of MII PHY devices */ ! 462: ! 463: /* ! 464: ** MII Management Control Register ! 465: */ ! 466: #define MII_CR_RST 0x8000 /* RESET the PHY chip */ ! 467: #define MII_CR_LPBK 0x4000 /* Loopback enable */ ! 468: #define MII_CR_SPD 0x2000 /* 0: 10Mb/s; 1: 100Mb/s */ ! 469: #define MII_CR_10 0x0000 /* Set 10Mb/s */ ! 470: #define MII_CR_100 0x2000 /* Set 100Mb/s */ ! 471: #define MII_CR_ASSE 0x1000 /* Auto Speed Select Enable */ ! 472: #define MII_CR_PD 0x0800 /* Power Down */ ! 473: #define MII_CR_ISOL 0x0400 /* Isolate Mode */ ! 474: #define MII_CR_RAN 0x0200 /* Restart Auto Negotiation */ ! 475: #define MII_CR_FDM 0x0100 /* Full Duplex Mode */ ! 476: #define MII_CR_CTE 0x0080 /* Collision Test Enable */ ! 477: ! 478: /* ! 479: ** MII Management Status Register ! 480: */ ! 481: #define MII_SR_T4C 0x8000 /* 100BASE-T4 capable */ ! 482: #define MII_SR_TXFD 0x4000 /* 100BASE-TX Full Duplex capable */ ! 483: #define MII_SR_TXHD 0x2000 /* 100BASE-TX Half Duplex capable */ ! 484: #define MII_SR_TFD 0x1000 /* 10BASE-T Full Duplex capable */ ! 485: #define MII_SR_THD 0x0800 /* 10BASE-T Half Duplex capable */ ! 486: #define MII_SR_ASSC 0x0020 /* Auto Speed Selection Complete*/ ! 487: #define MII_SR_RFD 0x0010 /* Remote Fault Detected */ ! 488: #define MII_SR_ANC 0x0008 /* Auto Negotiation capable */ ! 489: #define MII_SR_LKS 0x0004 /* Link Status */ ! 490: #define MII_SR_JABD 0x0002 /* Jabber Detect */ ! 491: #define MII_SR_XC 0x0001 /* Extended Capabilities */ ! 492: ! 493: /* ! 494: ** MII Management Auto Negotiation Advertisement Register ! 495: */ ! 496: #define MII_ANA_TAF 0x03e0 /* Technology Ability Field */ ! 497: #define MII_ANA_T4AM 0x0200 /* T4 Technology Ability Mask */ ! 498: #define MII_ANA_TXAM 0x0180 /* TX Technology Ability Mask */ ! 499: #define MII_ANA_FDAM 0x0140 /* Full Duplex Technology Ability Mask */ ! 500: #define MII_ANA_HDAM 0x02a0 /* Half Duplex Technology Ability Mask */ ! 501: #define MII_ANA_100M 0x0380 /* 100Mb Technology Ability Mask */ ! 502: #define MII_ANA_10M 0x0060 /* 10Mb Technology Ability Mask */ ! 503: #define MII_ANA_CSMA 0x0001 /* CSMA-CD Capable */ ! 504: ! 505: /* ! 506: ** MII Management Auto Negotiation Remote End Register ! 507: */ ! 508: #define MII_ANLPA_NP 0x8000 /* Next Page (Enable) */ ! 509: #define MII_ANLPA_ACK 0x4000 /* Remote Acknowledge */ ! 510: #define MII_ANLPA_RF 0x2000 /* Remote Fault */ ! 511: #define MII_ANLPA_TAF 0x03e0 /* Technology Ability Field */ ! 512: #define MII_ANLPA_T4AM 0x0200 /* T4 Technology Ability Mask */ ! 513: #define MII_ANLPA_TXAM 0x0180 /* TX Technology Ability Mask */ ! 514: #define MII_ANLPA_FDAM 0x0140 /* Full Duplex Technology Ability Mask */ ! 515: #define MII_ANLPA_HDAM 0x02a0 /* Half Duplex Technology Ability Mask */ ! 516: #define MII_ANLPA_100M 0x0380 /* 100Mb Technology Ability Mask */ ! 517: #define MII_ANLPA_10M 0x0060 /* 10Mb Technology Ability Mask */ ! 518: #define MII_ANLPA_CSMA 0x0001 /* CSMA-CD Capable */ ! 519: ! 520: /* ! 521: ** SROM Media Definitions (ABG SROM Section) ! 522: */ ! 523: #define MEDIA_NWAY 0x0080 /* Nway (Auto Negotiation) on PHY */ ! 524: #define MEDIA_MII 0x0040 /* MII Present on the adapter */ ! 525: #define MEDIA_FIBRE 0x0008 /* Fibre Media present */ ! 526: #define MEDIA_AUI 0x0004 /* AUI Media present */ ! 527: #define MEDIA_TP 0x0002 /* TP Media present */ ! 528: #define MEDIA_BNC 0x0001 /* BNC Media present */ ! 529: ! 530: /* ! 531: ** SROM Definitions (Digital Semiconductor Format) ! 532: */ ! 533: #define SROM_SSVID 0x0000 /* Sub-system Vendor ID offset */ ! 534: #define SROM_SSID 0x0002 /* Sub-system ID offset */ ! 535: #define SROM_CISPL 0x0004 /* CardBus CIS Pointer low offset */ ! 536: #define SROM_CISPH 0x0006 /* CardBus CIS Pointer high offset */ ! 537: #define SROM_IDCRC 0x0010 /* ID Block CRC offset*/ ! 538: #define SROM_RSVD2 0x0011 /* ID Reserved 2 offset */ ! 539: #define SROM_SFV 0x0012 /* SROM Format Version offset */ ! 540: #define SROM_CCNT 0x0013 /* Controller Count offset */ ! 541: #define SROM_HWADD 0x0014 /* Hardware Address offset */ ! 542: #define SROM_MRSVD 0x007c /* Manufacturer Reserved offset*/ ! 543: #define SROM_CRC 0x007e /* SROM CRC offset */ ! 544: ! 545: /* ! 546: ** SROM Media Connection Definitions ! 547: */ ! 548: #define SROM_10BT 0x0000 /* 10BASE-T half duplex */ ! 549: #define SROM_10BTN 0x0100 /* 10BASE-T with Nway */ ! 550: #define SROM_10BTF 0x0204 /* 10BASE-T full duplex */ ! 551: #define SROM_10BTNLP 0x0400 /* 10BASE-T without Link Pass test */ ! 552: #define SROM_10B2 0x0001 /* 10BASE-2 (BNC) */ ! 553: #define SROM_10B5 0x0002 /* 10BASE-5 (AUI) */ ! 554: #define SROM_100BTH 0x0003 /* 100BASE-T half duplex */ ! 555: #define SROM_100BTF 0x0205 /* 100BASE-T full duplex */ ! 556: #define SROM_100BT4 0x0006 /* 100BASE-T4 */ ! 557: #define SROM_100BFX 0x0007 /* 100BASE-FX half duplex (Fiber) */ ! 558: #define SROM_M10BT 0x0009 /* MII 10BASE-T half duplex */ ! 559: #define SROM_M10BTF 0x020a /* MII 10BASE-T full duplex */ ! 560: #define SROM_M100BT 0x000d /* MII 100BASE-T half duplex */ ! 561: #define SROM_M100BTF 0x020e /* MII 100BASE-T full duplex */ ! 562: #define SROM_M100BT4 0x000f /* MII 100BASE-T4 */ ! 563: #define SROM_M100BF 0x0010 /* MII 100BASE-FX half duplex */ ! 564: #define SROM_M100BFF 0x0211 /* MII 100BASE-FX full duplex */ ! 565: #define SROM_PDA 0x0800 /* Powerup & Dynamic Autosense */ ! 566: #define SROM_PAO 0x8800 /* Powerup Autosense Only */ ! 567: #define SROM_NSMI 0xffff /* No Selected Media Information */ ! 568: ! 569: /* ! 570: ** SROM Media Definitions ! 571: */ ! 572: #define SROM_10BASET 0x0000 /* 10BASE-T half duplex */ ! 573: #define SROM_10BASE2 0x0001 /* 10BASE-2 (BNC) */ ! 574: #define SROM_10BASE5 0x0002 /* 10BASE-5 (AUI) */ ! 575: #define SROM_100BASET 0x0003 /* 100BASE-T half duplex */ ! 576: #define SROM_10BASETF 0x0004 /* 10BASE-T full duplex */ ! 577: #define SROM_100BASETF 0x0005 /* 100BASE-T full duplex */ ! 578: #define SROM_100BASET4 0x0006 /* 100BASE-T4 */ ! 579: #define SROM_100BASEF 0x0007 /* 100BASE-FX half duplex */ ! 580: #define SROM_100BASEFF 0x0008 /* 100BASE-FX full duplex */ ! 581: ! 582: #define BLOCK_LEN 0x7f /* Extended blocks length mask */ ! 583: #define EXT_FIELD 0x40 /* Extended blocks extension field bit */ ! 584: #define MEDIA_CODE 0x3f /* Extended blocks media code mask */ ! 585: ! 586: /* ! 587: ** SROM Compact Format Block Masks ! 588: */ ! 589: #define COMPACT_FI 0x80 /* Format Indicator */ ! 590: #define COMPACT_LEN 0x04 /* Length */ ! 591: #define COMPACT_MC 0x3f /* Media Code */ ! 592: ! 593: /* ! 594: ** SROM Extended Format Block Type 0 Masks ! 595: */ ! 596: #define BLOCK0_FI 0x80 /* Format Indicator */ ! 597: #define BLOCK0_MCS 0x80 /* Media Code byte Sign */ ! 598: #define BLOCK0_MC 0x3f /* Media Code */ ! 599: ! 600: /* ! 601: ** DC21040 Full Duplex Register (DE4X5_FDR) ! 602: */ ! 603: #define FDR_FDACV 0x0000ffff /* Full Duplex Auto Configuration Value */ ! 604: ! 605: /* ! 606: ** DC21041 General Purpose Timer Register (DE4X5_GPT) ! 607: */ ! 608: #define GPT_CON 0x00010000 /* One shot: 0, Continuous: 1 */ ! 609: #define GPT_VAL 0x0000ffff /* Timer Value */ ! 610: ! 611: /* ! 612: ** DC21140 General Purpose Register (DE4X5_GEP) (hardware dependent bits) ! 613: */ ! 614: /* Valid ONLY for DE500 hardware */ ! 615: #define GEP_LNP 0x00000080 /* Link Pass (input) */ ! 616: #define GEP_SLNK 0x00000040 /* SYM LINK (input) */ ! 617: #define GEP_SDET 0x00000020 /* Signal Detect (input) */ ! 618: #define GEP_HRST 0x00000010 /* Hard RESET (to PHY) (output) */ ! 619: #define GEP_FDXD 0x00000008 /* Full Duplex Disable (output) */ ! 620: #define GEP_PHYL 0x00000004 /* PHY Loopback (output) */ ! 621: #define GEP_FLED 0x00000002 /* Force Activity LED on (output) */ ! 622: #define GEP_MODE 0x00000001 /* 0: 10Mb/s, 1: 100Mb/s */ ! 623: #define GEP_INIT 0x0000011f /* Setup inputs (0) and outputs (1) */ ! 624: #define GEP_CTRL 0x00000100 /* GEP control bit */ ! 625: ! 626: /* ! 627: ** SIA Register Defaults ! 628: */ ! 629: #define CSR13 0x00000001 ! 630: #define CSR14 0x0003ff7f /* Autonegotiation disabled */ ! 631: #define CSR15 0x00000008 ! 632: ! 633: /* ! 634: ** SIA Status Register (DE4X5_SISR) ! 635: */ ! 636: #define SISR_LPC 0xffff0000 /* Link Partner's Code Word */ ! 637: #define SISR_LPN 0x00008000 /* Link Partner Negotiable */ ! 638: #define SISR_ANS 0x00007000 /* Auto Negotiation Arbitration State */ ! 639: #define SISR_NSN 0x00000800 /* Non Stable NLPs Detected (DC21041) */ ! 640: #define SISR_TRF 0x00000800 /* Transmit Remote Fault */ ! 641: #define SISR_NSND 0x00000400 /* Non Stable NLPs Detected (DC21142) */ ! 642: #define SISR_ANR_FDS 0x00000400 /* Auto Negotiate Restart/Full Duplex Sel.*/ ! 643: #define SISR_TRA 0x00000200 /* 10BASE-T Receive Port Activity */ ! 644: #define SISR_NRA 0x00000200 /* Non Selected Port Receive Activity */ ! 645: #define SISR_ARA 0x00000100 /* AUI Receive Port Activity */ ! 646: #define SISR_SRA 0x00000100 /* Selected Port Receive Activity */ ! 647: #define SISR_DAO 0x00000080 /* PLL All One */ ! 648: #define SISR_DAZ 0x00000040 /* PLL All Zero */ ! 649: #define SISR_DSP 0x00000020 /* PLL Self-Test Pass */ ! 650: #define SISR_DSD 0x00000010 /* PLL Self-Test Done */ ! 651: #define SISR_APS 0x00000008 /* Auto Polarity State */ ! 652: #define SISR_LKF 0x00000004 /* Link Fail Status */ ! 653: #define SISR_LS10 0x00000004 /* 10Mb/s Link Fail Status */ ! 654: #define SISR_NCR 0x00000002 /* Network Connection Error */ ! 655: #define SISR_LS100 0x00000002 /* 100Mb/s Link Fail Status */ ! 656: #define SISR_PAUI 0x00000001 /* AUI_TP Indication */ ! 657: #define SISR_MRA 0x00000001 /* MII Receive Port Activity */ ! 658: ! 659: #define ANS_NDIS 0x00000000 /* Nway disable */ ! 660: #define ANS_TDIS 0x00001000 /* Transmit Disable */ ! 661: #define ANS_ADET 0x00002000 /* Ability Detect */ ! 662: #define ANS_ACK 0x00003000 /* Acknowledge */ ! 663: #define ANS_CACK 0x00004000 /* Complete Acknowledge */ ! 664: #define ANS_NWOK 0x00005000 /* Nway OK - FLP Link Good */ ! 665: #define ANS_LCHK 0x00006000 /* Link Check */ ! 666: ! 667: #define SISR_RST 0x00000301 /* CSR12 reset */ ! 668: #define SISR_ANR 0x00001301 /* Autonegotiation restart */ ! 669: ! 670: /* ! 671: ** SIA Connectivity Register (DE4X5_SICR) ! 672: */ ! 673: #define SICR_SDM 0xffff0000 /* SIA Diagnostics Mode */ ! 674: #define SICR_OE57 0x00008000 /* Output Enable 5 6 7 */ ! 675: #define SICR_OE24 0x00004000 /* Output Enable 2 4 */ ! 676: #define SICR_OE13 0x00002000 /* Output Enable 1 3 */ ! 677: #define SICR_IE 0x00001000 /* Input Enable */ ! 678: #define SICR_EXT 0x00000000 /* SIA MUX Select External SIA Mode */ ! 679: #define SICR_D_SIA 0x00000400 /* SIA MUX Select Diagnostics - SIA Sigs */ ! 680: #define SICR_DPLL 0x00000800 /* SIA MUX Select Diagnostics - DPLL Sigs*/ ! 681: #define SICR_APLL 0x00000a00 /* SIA MUX Select Diagnostics - DPLL Sigs*/ ! 682: #define SICR_D_RxM 0x00000c00 /* SIA MUX Select Diagnostics - RxM Sigs */ ! 683: #define SICR_M_RxM 0x00000d00 /* SIA MUX Select Diagnostics - RxM Sigs */ ! 684: #define SICR_LNKT 0x00000e00 /* SIA MUX Select Diagnostics - Link Test*/ ! 685: #define SICR_SEL 0x00000f00 /* SIA MUX Select AUI or TP with LEDs */ ! 686: #define SICR_ASE 0x00000080 /* APLL Start Enable*/ ! 687: #define SICR_SIM 0x00000040 /* Serial Interface Input Multiplexer */ ! 688: #define SICR_ENI 0x00000020 /* Encoder Input Multiplexer */ ! 689: #define SICR_EDP 0x00000010 /* SIA PLL External Input Enable */ ! 690: #define SICR_AUI 0x00000008 /* 10Base-T (0) or AUI (1) */ ! 691: #define SICR_CAC 0x00000004 /* CSR Auto Configuration */ ! 692: #define SICR_PS 0x00000002 /* Pin AUI/TP Selection */ ! 693: #define SICR_SRL 0x00000001 /* SIA Reset */ ! 694: #define SIA_RESET 0x00000000 /* SIA Reset Value */ ! 695: ! 696: /* ! 697: ** SIA Transmit and Receive Register (DE4X5_STRR) ! 698: */ ! 699: #define STRR_TAS 0x00008000 /* 10Base-T/AUI Autosensing Enable */ ! 700: #define STRR_SPP 0x00004000 /* Set Polarity Plus */ ! 701: #define STRR_APE 0x00002000 /* Auto Polarity Enable */ ! 702: #define STRR_LTE 0x00001000 /* Link Test Enable */ ! 703: #define STRR_SQE 0x00000800 /* Signal Quality Enable */ ! 704: #define STRR_CLD 0x00000400 /* Collision Detect Enable */ ! 705: #define STRR_CSQ 0x00000200 /* Collision Squelch Enable */ ! 706: #define STRR_RSQ 0x00000100 /* Receive Squelch Enable */ ! 707: #define STRR_ANE 0x00000080 /* Auto Negotiate Enable */ ! 708: #define STRR_HDE 0x00000040 /* Half Duplex Enable */ ! 709: #define STRR_CPEN 0x00000030 /* Compensation Enable */ ! 710: #define STRR_LSE 0x00000008 /* Link Pulse Send Enable */ ! 711: #define STRR_DREN 0x00000004 /* Driver Enable */ ! 712: #define STRR_LBK 0x00000002 /* Loopback Enable */ ! 713: #define STRR_ECEN 0x00000001 /* Encoder Enable */ ! 714: #define STRR_RESET 0xffffffff /* Reset value for STRR */ ! 715: ! 716: /* ! 717: ** SIA General Register (DE4X5_SIGR) ! 718: */ ! 719: #define SIGR_RMI 0x40000000 /* Receive Match Interrupt */ ! 720: #define SIGR_GI1 0x20000000 /* General Port Interrupt 1 */ ! 721: #define SIGR_GI0 0x10000000 /* General Port Interrupt 0 */ ! 722: #define SIGR_CWE 0x08000000 /* Control Write Enable */ ! 723: #define SIGR_RME 0x04000000 /* Receive Match Enable */ ! 724: #define SIGR_GEI1 0x02000000 /* GEP Interrupt Enable on Port 1 */ ! 725: #define SIGR_GEI0 0x01000000 /* GEP Interrupt Enable on Port 0 */ ! 726: #define SIGR_LGS3 0x00800000 /* LED/GEP3 Select */ ! 727: #define SIGR_LGS2 0x00400000 /* LED/GEP2 Select */ ! 728: #define SIGR_LGS1 0x00200000 /* LED/GEP1 Select */ ! 729: #define SIGR_LGS0 0x00100000 /* LED/GEP0 Select */ ! 730: #define SIGR_MD 0x000f0000 /* General Purpose Mode and Data */ ! 731: #define SIGR_LV2 0x00008000 /* General Purpose LED2 value */ ! 732: #define SIGR_LE2 0x00004000 /* General Purpose LED2 enable */ ! 733: #define SIGR_FRL 0x00002000 /* Force Receiver Low */ ! 734: #define SIGR_DPST 0x00001000 /* PLL Self Test Start */ ! 735: #define SIGR_LSD 0x00000800 /* LED Stretch Disable */ ! 736: #define SIGR_FLF 0x00000400 /* Force Link Fail */ ! 737: #define SIGR_FUSQ 0x00000200 /* Force Unsquelch */ ! 738: #define SIGR_TSCK 0x00000100 /* Test Clock */ ! 739: #define SIGR_LV1 0x00000080 /* General Purpose LED1 value */ ! 740: #define SIGR_LE1 0x00000040 /* General Purpose LED1 enable */ ! 741: #define SIGR_RWR 0x00000020 /* Receive Watchdog Release */ ! 742: #define SIGR_RWD 0x00000010 /* Receive Watchdog Disable */ ! 743: #define SIGR_ABM 0x00000008 /* BNC: 0, AUI:1 */ ! 744: #define SIGR_JCK 0x00000004 /* Jabber Clock */ ! 745: #define SIGR_HUJ 0x00000002 /* Host Unjab */ ! 746: #define SIGR_JBD 0x00000001 /* Jabber Disable */ ! 747: #define SIGR_RESET 0xffff0000 /* Reset value for SIGR */ ! 748: ! 749: /* ! 750: ** Receive Descriptor Bit Summary ! 751: */ ! 752: #define R_OWN 0x80000000 /* Own Bit */ ! 753: #define RD_FF 0x40000000 /* Filtering Fail */ ! 754: #define RD_FL 0x3fff0000 /* Frame Length */ ! 755: #define RD_ES 0x00008000 /* Error Summary */ ! 756: #define RD_LE 0x00004000 /* Length Error */ ! 757: #define RD_DT 0x00003000 /* Data Type */ ! 758: #define RD_RF 0x00000800 /* Runt Frame */ ! 759: #define RD_MF 0x00000400 /* Multicast Frame */ ! 760: #define RD_FS 0x00000200 /* First Descriptor */ ! 761: #define RD_LS 0x00000100 /* Last Descriptor */ ! 762: #define RD_TL 0x00000080 /* Frame Too Long */ ! 763: #define RD_CS 0x00000040 /* Collision Seen */ ! 764: #define RD_FT 0x00000020 /* Frame Type */ ! 765: #define RD_RJ 0x00000010 /* Receive Watchdog */ ! 766: #define RD_RE 0x00000008 /* Report on MII Error */ ! 767: #define RD_DB 0x00000004 /* Dribbling Bit */ ! 768: #define RD_CE 0x00000002 /* CRC Error */ ! 769: #define RD_OF 0x00000001 /* Overflow */ ! 770: ! 771: #define RD_RER 0x02000000 /* Receive End Of Ring */ ! 772: #define RD_RCH 0x01000000 /* Second Address Chained */ ! 773: #define RD_RBS2 0x003ff800 /* Buffer 2 Size */ ! 774: #define RD_RBS1 0x000007ff /* Buffer 1 Size */ ! 775: ! 776: /* ! 777: ** Transmit Descriptor Bit Summary ! 778: */ ! 779: #define T_OWN 0x80000000 /* Own Bit */ ! 780: #define TD_ES 0x00008000 /* Error Summary */ ! 781: #define TD_TO 0x00004000 /* Transmit Jabber Time-Out */ ! 782: #define TD_LO 0x00000800 /* Loss Of Carrier */ ! 783: #define TD_NC 0x00000400 /* No Carrier */ ! 784: #define TD_LC 0x00000200 /* Late Collision */ ! 785: #define TD_EC 0x00000100 /* Excessive Collisions */ ! 786: #define TD_HF 0x00000080 /* Heartbeat Fail */ ! 787: #define TD_CC 0x00000078 /* Collision Counter */ ! 788: #define TD_LF 0x00000004 /* Link Fail */ ! 789: #define TD_UF 0x00000002 /* Underflow Error */ ! 790: #define TD_DE 0x00000001 /* Deferred */ ! 791: ! 792: #define TD_IC 0x80000000 /* Interrupt On Completion */ ! 793: #define TD_LS 0x40000000 /* Last Segment */ ! 794: #define TD_FS 0x20000000 /* First Segment */ ! 795: #define TD_FT1 0x10000000 /* Filtering Type */ ! 796: #define TD_SET 0x08000000 /* Setup Packet */ ! 797: #define TD_AC 0x04000000 /* Add CRC Disable */ ! 798: #define TD_TER 0x02000000 /* Transmit End Of Ring */ ! 799: #define TD_TCH 0x01000000 /* Second Address Chained */ ! 800: #define TD_DPD 0x00800000 /* Disabled Padding */ ! 801: #define TD_FT0 0x00400000 /* Filtering Type */ ! 802: #define TD_TBS2 0x003ff800 /* Buffer 2 Size */ ! 803: #define TD_TBS1 0x000007ff /* Buffer 1 Size */ ! 804: ! 805: #define PERFECT_F 0x00000000 ! 806: #define HASH_F TD_FT0 ! 807: #define INVERSE_F TD_FT1 ! 808: #define HASH_O_F (TD_FT1 | TD_F0) ! 809: ! 810: /* ! 811: ** Media / mode state machine definitions ! 812: ** User selectable: ! 813: */ ! 814: #define TP 0x0001 /* 10Base-T */ ! 815: #define TP_NW 0x0002 /* 10Base-T with Nway */ ! 816: #define BNC 0x0004 /* Thinwire */ ! 817: #define AUI 0x0008 /* Thickwire */ ! 818: #define BNC_AUI 0x0010 /* BNC/AUI on DC21040 indistinguishable */ ! 819: #define _10Mb 0x0040 /* 10Mb/s Ethernet */ ! 820: #define _100Mb 0x0080 /* 100Mb/s Ethernet */ ! 821: #define AUTO 0x4000 /* Auto sense the media or speed */ ! 822: ! 823: /* ! 824: ** Internal states ! 825: */ ! 826: #define NC 0x0000 /* No Connection */ ! 827: #define ANS 0x0020 /* Intermediate AutoNegotiation State */ ! 828: #define SPD_DET 0x0100 /* Parallel speed detection */ ! 829: #define INIT 0x0200 /* Initial state */ ! 830: #define EXT_SIA 0x0400 /* External SIA for motherboard chip */ ! 831: #define ANS_SUSPECT 0x0802 /* Suspect the ANS (TP) port is down */ ! 832: #define TP_SUSPECT 0x0803 /* Suspect the TP port is down */ ! 833: #define BNC_AUI_SUSPECT 0x0804 /* Suspect the BNC or AUI port is down */ ! 834: #define EXT_SIA_SUSPECT 0x0805 /* Suspect the EXT SIA port is down */ ! 835: #define BNC_SUSPECT 0x0806 /* Suspect the BNC port is down */ ! 836: #define AUI_SUSPECT 0x0807 /* Suspect the AUI port is down */ ! 837: #define MII 0x1000 /* MII on the 21143 */ ! 838: ! 839: #define TIMER_CB 0x80000000 /* Timer callback detection */ ! 840: ! 841: /* ! 842: ** DE4X5 DEBUG Options ! 843: */ ! 844: #define DEBUG_NONE 0x0000 /* No DEBUG messages */ ! 845: #define DEBUG_VERSION 0x0001 /* Print version message */ ! 846: #define DEBUG_MEDIA 0x0002 /* Print media messages */ ! 847: #define DEBUG_TX 0x0004 /* Print TX (queue_pkt) messages */ ! 848: #define DEBUG_RX 0x0008 /* Print RX (de4x5_rx) messages */ ! 849: #define DEBUG_SROM 0x0010 /* Print SROM messages */ ! 850: #define DEBUG_MII 0x0020 /* Print MII messages */ ! 851: #define DEBUG_OPEN 0x0040 /* Print de4x5_open() messages */ ! 852: #define DEBUG_CLOSE 0x0080 /* Print de4x5_close() messages */ ! 853: #define DEBUG_PCICFG 0x0100 ! 854: #define DEBUG_ALL 0x01ff ! 855: ! 856: /* ! 857: ** Miscellaneous ! 858: */ ! 859: #define PCI 0 ! 860: #define EISA 1 ! 861: ! 862: #define HASH_TABLE_LEN 512 /* Bits */ ! 863: #define HASH_BITS 0x01ff /* 9 LS bits */ ! 864: ! 865: #define SETUP_FRAME_LEN 192 /* Bytes */ ! 866: #define IMPERF_PA_OFFSET 156 /* Bytes */ ! 867: ! 868: #define POLL_DEMAND 1 ! 869: ! 870: #define LOST_MEDIA_THRESHOLD 3 ! 871: ! 872: #define MASK_INTERRUPTS 1 ! 873: #define UNMASK_INTERRUPTS 0 ! 874: ! 875: #define DE4X5_STRLEN 8 ! 876: ! 877: #define DE4X5_INIT 0 /* Initialisation time */ ! 878: #define DE4X5_RUN 1 /* Run time */ ! 879: ! 880: #define DE4X5_SAVE_STATE 0 ! 881: #define DE4X5_RESTORE_STATE 1 ! 882: ! 883: /* ! 884: ** Address Filtering Modes ! 885: */ ! 886: #define PERFECT 0 /* 16 perfect physical addresses */ ! 887: #define HASH_PERF 1 /* 1 perfect, 512 multicast addresses */ ! 888: #define PERFECT_REJ 2 /* Reject 16 perfect physical addresses */ ! 889: #define ALL_HASH 3 /* Hashes all physical & multicast addrs */ ! 890: ! 891: #define ALL 0 /* Clear out all the setup frame */ ! 892: #define PHYS_ADDR_ONLY 1 /* Update the physical address only */ ! 893: ! 894: /* ! 895: ** Booleans ! 896: */ ! 897: #define NO 0 ! 898: #define FALSE 0 ! 899: ! 900: #define YES ~0 ! 901: #define TRUE ~0 ! 902: ! 903: /* ! 904: ** Adapter state ! 905: */ ! 906: #define INITIALISED 0 /* After h/w initialised and mem alloc'd */ ! 907: #define CLOSED 1 /* Ready for opening */ ! 908: #define OPEN 2 /* Running */ ! 909: ! 910: /* ! 911: ** Various wait times ! 912: */ ! 913: #define PDET_LINK_WAIT 1200 /* msecs to wait for link detect bits */ ! 914: #define ANS_FINISH_WAIT 1000 /* msecs to wait for link detect bits */ ! 915: ! 916: /* ! 917: ** IEEE OUIs for various PHY vendor/chip combos - Reg 2 values only. Since ! 918: ** the vendors seem split 50-50 on how to calculate the OUI register values ! 919: ** anyway, just reading Reg2 seems reasonable for now [see de4x5_get_oui()]. ! 920: */ ! 921: #define NATIONAL_TX 0x2000 ! 922: #define BROADCOM_T4 0x03e0 ! 923: #define SEEQ_T4 0x0016 ! 924: #define CYPRESS_T4 0x0014 ! 925: ! 926: /* ! 927: ** Speed Selection stuff ! 928: */ ! 929: #define SET_10Mb {\ ! 930: if ((lp->phy[lp->active].id) && (!lp->useSROM || lp->useMII)) {\ ! 931: omr = inl(DE4X5_OMR) & ~(OMR_TTM | OMR_PCS | OMR_SCR | OMR_FDX);\ ! 932: if ((lp->tmp != MII_SR_ASSC) || (lp->autosense != AUTO)) {\ ! 933: mii_wr(MII_CR_10|(lp->fdx?MII_CR_FDM:0), MII_CR, lp->phy[lp->active].addr, DE4X5_MII);\ ! 934: }\ ! 935: omr |= ((lp->fdx ? OMR_FDX : 0) | OMR_TTM);\ ! 936: outl(omr, DE4X5_OMR);\ ! 937: if (!lp->useSROM) lp->cache.gep = 0;\ ! 938: } else if (lp->useSROM && !lp->useMII) {\ ! 939: omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR | OMR_FDX));\ ! 940: omr |= (lp->fdx ? OMR_FDX : 0);\ ! 941: outl(omr | (lp->infoblock_csr6 & ~(OMR_SCR | OMR_HBD)), DE4X5_OMR);\ ! 942: } else {\ ! 943: omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR | OMR_FDX));\ ! 944: omr |= (lp->fdx ? OMR_FDX : 0);\ ! 945: outl(omr | OMR_SDP | OMR_TTM, DE4X5_OMR);\ ! 946: lp->cache.gep = (lp->fdx ? 0 : GEP_FDXD);\ ! 947: gep_wr(lp->cache.gep, dev);\ ! 948: }\ ! 949: } ! 950: ! 951: #define SET_100Mb {\ ! 952: if ((lp->phy[lp->active].id) && (!lp->useSROM || lp->useMII)) {\ ! 953: int fdx=0;\ ! 954: if (lp->phy[lp->active].id == NATIONAL_TX) {\ ! 955: mii_wr(mii_rd(0x18, lp->phy[lp->active].addr, DE4X5_MII) & ~0x2000,\ ! 956: 0x18, lp->phy[lp->active].addr, DE4X5_MII);\ ! 957: }\ ! 958: omr = inl(DE4X5_OMR) & ~(OMR_TTM | OMR_PCS | OMR_SCR | OMR_FDX);\ ! 959: sr = mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);\ ! 960: if (!(sr & MII_ANA_T4AM) && lp->fdx) fdx=1;\ ! 961: if ((lp->tmp != MII_SR_ASSC) || (lp->autosense != AUTO)) {\ ! 962: mii_wr(MII_CR_100|(fdx?MII_CR_FDM:0), MII_CR, lp->phy[lp->active].addr, DE4X5_MII);\ ! 963: }\ ! 964: if (fdx) omr |= OMR_FDX;\ ! 965: outl(omr, DE4X5_OMR);\ ! 966: if (!lp->useSROM) lp->cache.gep = 0;\ ! 967: } else if (lp->useSROM && !lp->useMII) {\ ! 968: omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR | OMR_FDX));\ ! 969: omr |= (lp->fdx ? OMR_FDX : 0);\ ! 970: outl(omr | lp->infoblock_csr6, DE4X5_OMR);\ ! 971: } else {\ ! 972: omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR | OMR_FDX));\ ! 973: omr |= (lp->fdx ? OMR_FDX : 0);\ ! 974: outl(omr | OMR_SDP | OMR_PS | OMR_HBD | OMR_PCS | OMR_SCR, DE4X5_OMR);\ ! 975: lp->cache.gep = (lp->fdx ? 0 : GEP_FDXD) | GEP_MODE;\ ! 976: gep_wr(lp->cache.gep, dev);\ ! 977: }\ ! 978: } ! 979: ! 980: /* FIX ME so I don't jam 10Mb networks */ ! 981: #define SET_100Mb_PDET {\ ! 982: if ((lp->phy[lp->active].id) && (!lp->useSROM || lp->useMII)) {\ ! 983: mii_wr(MII_CR_100|MII_CR_ASSE, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);\ ! 984: omr = (inl(DE4X5_OMR) & ~(OMR_TTM | OMR_PCS | OMR_SCR | OMR_FDX));\ ! 985: outl(omr, DE4X5_OMR);\ ! 986: } else if (lp->useSROM && !lp->useMII) {\ ! 987: omr = (inl(DE4X5_OMR) & ~(OMR_TTM | OMR_PCS | OMR_SCR | OMR_FDX));\ ! 988: outl(omr, DE4X5_OMR);\ ! 989: } else {\ ! 990: omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR | OMR_FDX));\ ! 991: outl(omr | OMR_SDP | OMR_PS | OMR_HBD | OMR_PCS, DE4X5_OMR);\ ! 992: lp->cache.gep = (GEP_FDXD | GEP_MODE);\ ! 993: gep_wr(lp->cache.gep, dev);\ ! 994: }\ ! 995: } ! 996: ! 997: /* ! 998: ** Include the IOCTL stuff ! 999: */ ! 1000: #include <linux/sockios.h> ! 1001: ! 1002: #define DE4X5IOCTL SIOCDEVPRIVATE ! 1003: ! 1004: struct de4x5_ioctl { ! 1005: unsigned short cmd; /* Command to run */ ! 1006: unsigned short len; /* Length of the data buffer */ ! 1007: unsigned char *data; /* Pointer to the data buffer */ ! 1008: }; ! 1009: ! 1010: /* ! 1011: ** Recognised commands for the driver ! 1012: */ ! 1013: #define DE4X5_GET_HWADDR 0x01 /* Get the hardware address */ ! 1014: #define DE4X5_SET_HWADDR 0x02 /* Set the hardware address */ ! 1015: #define DE4X5_SET_PROM 0x03 /* Set Promiscuous Mode */ ! 1016: #define DE4X5_CLR_PROM 0x04 /* Clear Promiscuous Mode */ ! 1017: #define DE4X5_SAY_BOO 0x05 /* Say "Boo!" to the kernel log file */ ! 1018: #define DE4X5_GET_MCA 0x06 /* Get a multicast address */ ! 1019: #define DE4X5_SET_MCA 0x07 /* Set a multicast address */ ! 1020: #define DE4X5_CLR_MCA 0x08 /* Clear a multicast address */ ! 1021: #define DE4X5_MCA_EN 0x09 /* Enable a multicast address group */ ! 1022: #define DE4X5_GET_STATS 0x0a /* Get the driver statistics */ ! 1023: #define DE4X5_CLR_STATS 0x0b /* Zero out the driver statistics */ ! 1024: #define DE4X5_GET_OMR 0x0c /* Get the OMR Register contents */ ! 1025: #define DE4X5_SET_OMR 0x0d /* Set the OMR Register contents */ ! 1026: #define DE4X5_GET_REG 0x0e /* Get the DE4X5 Registers */ ! 1027: ! 1028: #define LinuxVersionCode(v, p, s) (((v)<<16)+((p)<<8)+(s))
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