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1.1 root 1: /* epic100.c: A SMC 83c170 EPIC/100 Fast Ethernet driver for Linux. */
2: /*
3: Written 1997-1998 by Donald Becker.
4:
5: This software may be used and distributed according to the terms
6: of the GNU Public License, incorporated herein by reference.
7: All other rights reserved.
8:
9: This driver is for the SMC83c170/175 "EPIC" series, as used on the
10: SMC EtherPower II 9432 PCI adapter, and several CardBus cards.
11:
12: The author may be reached as [email protected], or C/O
13: Center of Excellence in Space Data and Information Sciences
14: Code 930.5, Goddard Space Flight Center, Greenbelt MD 20771
15:
16: Support and updates available at
17: http://cesdis.gsfc.nasa.gov/linux/drivers/epic100.html
18: */
19:
20: static const char *version =
21: "epic100.c:v1.03 8/7/98 Donald Becker http://cesdis.gsfc.nasa.gov/linux/drivers/epic100.html\n";
22:
23: /* A few user-configurable values. */
24:
25: /* Keep the ring sizes a power of two for efficiency.
26: Making the Tx ring too large decreases the effectiveness of channel
27: bonding and packet priority.
28: There are no ill effects from too-large receive rings. */
29: #define TX_RING_SIZE 16
30: #define RX_RING_SIZE 32
31:
32: /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
33: Setting to > 1518 effectively disables this feature. */
34: static int rx_copybreak = 200;
35:
36: /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
37: static int max_interrupt_work = 10;
38:
39: /* Operational parameters that usually are not changed. */
40: /* Time in jiffies before concluding the transmitter is hung. */
41: #define TX_TIMEOUT ((2000*HZ)/1000)
42:
43: #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
44:
45: /* Bytes transferred to chip before transmission starts. */
46: #define TX_FIFO_THRESH 256 /* Rounded down to 4 byte units. */
47: #define RX_FIFO_THRESH 1 /* 0-3, 0==32, 64,96, or 3==128 bytes */
48:
49: #include <linux/config.h>
50: #include <linux/version.h> /* Evil, but neccessary */
51: #ifdef MODULE
52: #ifdef MODVERSIONS
53: #include <linux/modversions.h>
54: #endif
55: #include <linux/module.h>
56: #else
57: #define MOD_INC_USE_COUNT
58: #define MOD_DEC_USE_COUNT
59: #endif
60:
61: #include <linux/kernel.h>
62: #include <linux/sched.h>
63: #include <linux/string.h>
64: #include <linux/timer.h>
65: #include <linux/ptrace.h>
66: #include <linux/errno.h>
67: #include <linux/ioport.h>
68: #include <linux/malloc.h>
69: #include <linux/interrupt.h>
70: #include <linux/pci.h>
71: #if LINUX_VERSION_CODE >= 0x20155
72: #define PCI_SUPPORT_VER2
73: #else
74: #include <linux/bios32.h>
75: #endif
76: #include <linux/delay.h>
77:
78: #include <asm/processor.h> /* Processor type for cache alignment. */
79: #include <asm/bitops.h>
80: #include <asm/io.h>
81: #include <asm/dma.h>
82:
83: #include <linux/netdevice.h>
84: #include <linux/etherdevice.h>
85: #include <linux/skbuff.h>
86:
87: /* Kernel compatibility defines, common to David Hind's PCMCIA package.
88: This is only in the support-all-kernels source code. */
89:
90: #if ! defined (LINUX_VERSION_CODE) || LINUX_VERSION_CODE < 0x20000
91: #warning This driver version is only for kernel versions 2.0.0 and later.
92: #endif
93:
94: #define RUN_AT(x) (jiffies + (x))
95:
96: #if defined(MODULE) && (LINUX_VERSION_CODE >= 0x20115)
97: MODULE_AUTHOR("Donald Becker <[email protected]>");
98: MODULE_DESCRIPTION("SMC 83c170 EPIC series Ethernet driver");
99: MODULE_PARM(debug, "i");
100: MODULE_PARM(options, "1-" __MODULE_STRING(8) "i");
101: MODULE_PARM(full_duplex, "1-" __MODULE_STRING(8) "i");
102: MODULE_PARM(rx_copybreak, "i");
103: MODULE_PARM(max_interrupt_work, "i");
104: #endif
105: #if LINUX_VERSION_CODE < 0x20123
106: #define test_and_set_bit(val, addr) set_bit(val, addr)
107: #endif
108: #if LINUX_VERSION_CODE <= 0x20139
109: #define net_device_stats enet_statistics
110: #define NETSTATS_VER2
111: #endif
112: #if LINUX_VERSION_CODE < 0x20159
113: #define DEV_FREE_SKB(skb) dev_kfree_skb(skb, FREE_WRITE);
114: #else /* Grrr, unneeded incompatible change. */
115: #define DEV_FREE_SKB(skb) dev_kfree_skb(skb);
116: #endif
117:
118: /* The I/O extent. */
119: #define EPIC_TOTAL_SIZE 0x100
120:
121: static int epic_debug = 1;
122:
123: /*
124: Theory of Operation
125:
126: I. Board Compatibility
127:
128: This device driver is designed for the SMC "EPCI/100", the SMC
129: single-chip Ethernet controllers for PCI. This chip is used on
130: the SMC EtherPower II boards.
131:
132:
133: II. Board-specific settings
134:
135: PCI bus devices are configured by the system at boot time, so no jumpers
136: need to be set on the board. The system BIOS will assign the
137: PCI INTA signal to a (preferably otherwise unused) system IRQ line.
138: Note: Kernel versions earlier than 1.3.73 do not support shared PCI
139: interrupt lines.
140:
141: III. Driver operation
142:
143: IIIa. Ring buffers
144:
145: IVb. References
146:
147: http://www.smc.com/components/catalog/smc83c170.html
148: http://cesdis.gsfc.nasa.gov/linux/misc/NWay.html
149: http://www.national.com/pf/DP/DP83840.html
150:
151: IVc. Errata
152:
153: */
154:
155: /* The rest of these values should never change. */
156:
157: static struct device *epic_probe1(int pci_bus, int pci_devfn,
158: struct device *dev, int card_idx);
159:
160: enum pci_flags_bit {
161: PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
162: PCI_ADDR0=0x10<<0, PCI_ADDR1=0x10<<1, PCI_ADDR2=0x10<<2, PCI_ADDR3=0x10<<3,
163: };
164: struct chip_info {
165: const char *name;
166: u16 vendor_id, device_id, device_id_mask, pci_flags;
167: int io_size, min_latency;
168: struct device *(*probe1)(int pci_bus, int pci_devfn, struct device *dev,
169: int chip_idx);
170: } chip_tbl[] = {
171: {"SMSC EPIC/100", 0x10B8, 0x0005, 0x7fff,
172: PCI_USES_IO|PCI_USES_MASTER|PCI_ADDR0, EPIC_TOTAL_SIZE, 32, epic_probe1},
173: {0,},
174: };
175:
176: /* Offsets to registers, using the (ugh) SMC names. */
177: enum epic_registers {
178: COMMAND=0, INTSTAT=4, INTMASK=8, GENCTL=0x0C, NVCTL=0x10, EECTL=0x14,
179: PCIBurstCnt=0x18,
180: TEST1=0x1C, CRCCNT=0x20, ALICNT=0x24, MPCNT=0x28, /* Rx error counters. */
181: MIICtrl=0x30, MIIData=0x34, MIICfg=0x38,
182: LAN0=64, /* MAC address. */
183: MC0=80, /* Multicast filter table. */
184: RxCtrl=96, TxCtrl=112, TxSTAT=0x74,
185: PRxCDAR=0x84, RxSTAT=0xA4, EarlyRx=0xB0, PTxCDAR=0xC4, TxThresh=0xDC,
186: };
187:
188: /* Interrupt register bits, using my own meaningful names. */
189: enum IntrStatus {
190: TxIdle=0x40000, RxIdle=0x20000, IntrSummary=0x010000,
191: PCIBusErr170=0x7000, PCIBusErr175=0x1000, PhyEvent175=0x8000,
192: RxStarted=0x0800, RxEarlyWarn=0x0400, CntFull=0x0200, TxUnderrun=0x0100,
193: TxEmpty=0x0080, TxDone=0x0020, RxError=0x0010,
194: RxOverflow=0x0008, RxFull=0x0004, RxHeader=0x0002, RxDone=0x0001,
195: };
196:
197: /* The EPIC100 Rx and Tx buffer descriptors. */
198:
199: struct epic_tx_desc {
200: s16 status;
201: u16 txlength;
202: u32 bufaddr;
203: u16 buflength;
204: u16 control;
205: u32 next;
206: };
207:
208: struct epic_rx_desc {
209: s16 status;
210: u16 rxlength;
211: u32 bufaddr;
212: u32 buflength;
213: u32 next;
214: };
215:
216: struct epic_private {
217: char devname[8]; /* Used only for kernel debugging. */
218: const char *product_name;
219: struct device *next_module;
220:
221: /* Rx and Rx rings here so that they remain paragraph aligned. */
222: struct epic_rx_desc rx_ring[RX_RING_SIZE];
223: struct epic_tx_desc tx_ring[TX_RING_SIZE];
224: /* The saved address of a sent-in-place packet/buffer, for skfree(). */
225: struct sk_buff* tx_skbuff[TX_RING_SIZE];
226: /* The addresses of receive-in-place skbuffs. */
227: struct sk_buff* rx_skbuff[RX_RING_SIZE];
228:
229: /* Ring pointers. */
230: unsigned int cur_rx, cur_tx; /* The next free ring entry */
231: unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
232:
233: u8 pci_bus, pci_dev_fn; /* PCI bus location. */
234: u16 chip_id;
235:
236: struct net_device_stats stats;
237: struct timer_list timer; /* Media selection timer. */
238: unsigned char mc_filter[8];
239: signed char phys[4]; /* MII device addresses. */
240: unsigned int tx_full:1; /* The Tx queue is full. */
241: unsigned int full_duplex:1; /* Current duplex setting. */
242: unsigned int force_fd:1; /* Full-duplex operation requested. */
243: unsigned int default_port:4; /* Last dev->if_port value. */
244: unsigned int media2:4; /* Secondary monitored media port. */
245: unsigned int medialock:1; /* Don't sense media type. */
246: unsigned int mediasense:1; /* Media sensing in progress. */
247: int pad0, pad1; /* Used for 8-byte alignment */
248: };
249:
250: /* Used to pass the full-duplex flag, etc. */
251: #define MAX_UNITS 8
252: static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
253: static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
254:
255: static int epic_open(struct device *dev);
256: static int read_eeprom(long ioaddr, int location);
257: static int mdio_read(long ioaddr, int phy_id, int location);
258: static void mdio_write(long ioaddr, int phy_id, int location, int value);
259: static void epic_restart(struct device *dev);
260: static void epic_timer(unsigned long data);
261: static void epic_tx_timeout(struct device *dev);
262: static void epic_init_ring(struct device *dev);
263: static int epic_start_xmit(struct sk_buff *skb, struct device *dev);
264: static int epic_rx(struct device *dev);
265: static void epic_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
266: static int mii_ioctl(struct device *dev, struct ifreq *rq, int cmd);
267: static int epic_close(struct device *dev);
268: static struct net_device_stats *epic_get_stats(struct device *dev);
269: static void set_rx_mode(struct device *dev);
270:
271:
272: /* A list of all installed EPIC devices, for removing the driver module. */
273: static struct device *root_epic_dev = NULL;
274:
275: #ifndef CARDBUS
276: int epic100_probe(struct device *dev)
277: {
278: int cards_found = 0;
279: int chip_idx;
280: u16 pci_command, new_command;
281: unsigned char pci_bus, pci_device_fn;
282:
283: #ifdef PCI_SUPPORT_VER2
284: struct pci_dev *pcidev = NULL;
285: while ((pcidev = pci_find_class(PCI_CLASS_NETWORK_ETHERNET << 8, pcidev))
286: != NULL) {
287: long pci_ioaddr = pcidev->base_address[0] & ~3;
288: int vendor = pcidev->vendor;
289: int device = pcidev->device;
290:
291: for (chip_idx = 0; chip_tbl[chip_idx].vendor_id; chip_idx++)
292: if (vendor == chip_tbl[chip_idx].vendor_id
293: && (device & chip_tbl[chip_idx].device_id_mask) ==
294: chip_tbl[chip_idx].device_id)
295: break;
296: if (chip_tbl[chip_idx].vendor_id == 0 /* Compiled out! */
297: || check_region(pci_ioaddr, chip_tbl[chip_idx].io_size))
298: continue;
299: pci_bus = pcidev->bus->number;
300: pci_device_fn = pcidev->devfn;
301: #else
302: int pci_index;
303:
304: if ( ! pcibios_present())
305: return -ENODEV;
306:
307: for (pci_index = 0; pci_index < 0xff; pci_index++) {
308: u16 vendor, device;
309: u32 pci_ioaddr;
310:
311: if (pcibios_find_class (PCI_CLASS_NETWORK_ETHERNET << 8,
312: pci_index, &pci_bus, &pci_device_fn)
313: != PCIBIOS_SUCCESSFUL)
314: break;
315: pcibios_read_config_word(pci_bus, pci_device_fn,
316: PCI_VENDOR_ID, &vendor);
317: pcibios_read_config_word(pci_bus, pci_device_fn,
318: PCI_DEVICE_ID, &device);
319:
320: for (chip_idx = 0; chip_tbl[chip_idx].vendor_id; chip_idx++)
321: if (vendor == chip_tbl[chip_idx].vendor_id
322: && (device & chip_tbl[chip_idx].device_id_mask) ==
323: chip_tbl[chip_idx].device_id)
324: break;
325: if (chip_tbl[chip_idx].vendor_id == 0) /* Compiled out! */
326: continue;
327:
328: pcibios_read_config_dword(pci_bus, pci_device_fn,
329: PCI_BASE_ADDRESS_0, &pci_ioaddr);
330: /* Remove I/O space marker in bit 0. */
331: pci_ioaddr &= ~3;
332:
333: if (check_region(pci_ioaddr, chip_tbl[chip_idx].io_size))
334: continue;
335: #endif
336:
337: /* EPIC-specific code: Soft-reset the chip ere setting as master. */
338: outl(0x0001, pci_ioaddr + GENCTL);
339:
340: /* Activate the card: fix for brain-damaged Win98 BIOSes. */
341: pcibios_read_config_word(pci_bus, pci_device_fn,
342: PCI_COMMAND, &pci_command);
343: new_command = pci_command | PCI_COMMAND_MASTER|PCI_COMMAND_IO;
344: if (pci_command != new_command) {
345: printk(KERN_INFO " The PCI BIOS has not enabled Ethernet"
346: " device %4.4x-%4.4x."
347: " Updating PCI command %4.4x->%4.4x.\n",
348: vendor, device, pci_command, new_command);
349: pcibios_write_config_word(pci_bus, pci_device_fn,
350: PCI_COMMAND, new_command);
351: }
352:
353: dev = chip_tbl[chip_idx].probe1(pci_bus, pci_device_fn,
354: dev, cards_found);
355:
356: /* Check the latency timer. */
357: if (dev) {
358: u8 pci_latency;
359: pcibios_read_config_byte(pci_bus, pci_device_fn,
360: PCI_LATENCY_TIMER, &pci_latency);
361: if (pci_latency < chip_tbl[chip_idx].min_latency) {
362: printk(KERN_INFO " PCI latency timer (CFLT) value of %d is "
363: "unreasonably low, setting to %d.\n", pci_latency,
364: chip_tbl[chip_idx].min_latency);
365: pcibios_write_config_byte(pci_bus, pci_device_fn,
366: PCI_LATENCY_TIMER,
367: chip_tbl[chip_idx].min_latency);
368: }
369: dev = 0;
370: cards_found++;
371: }
372: }
373:
374: return cards_found ? 0 : -ENODEV;
375: }
376: #endif /* not CARDBUS */
377:
378: static struct device *epic_probe1(int bus, int devfn, struct device *dev,
379: int card_idx)
380: {
381: static int did_version = 0; /* Already printed version info. */
382: struct epic_private *ep;
383: int i, option = 0, duplex = 0;
384: u16 chip_id;
385: u32 ioaddr;
386:
387: if (epic_debug > 0 && did_version++ == 0)
388: printk(KERN_INFO "%s", version);
389:
390: if (dev && dev->mem_start) {
391: option = dev->mem_start;
392: duplex = (dev->mem_start & 16) ? 1 : 0;
393: } else if (card_idx >= 0 && card_idx < MAX_UNITS) {
394: if (options[card_idx] >= 0)
395: option = options[card_idx];
396: if (full_duplex[card_idx] >= 0)
397: duplex = full_duplex[card_idx];
398: }
399:
400: dev = init_etherdev(dev, 0);
401:
402: { /* Grrrr, badly consider interface change. */
403: #if defined(PCI_SUPPORT_VER2)
404: struct pci_dev *pdev = pci_find_slot(bus, devfn);
405: ioaddr = pdev->base_address[0] & ~3;
406: dev->irq = pdev->irq;
407: chip_id = pdev->device;
408: #else
409: u8 irq;
410: u32 ioaddr0;
411: pcibios_read_config_dword(bus, devfn, PCI_BASE_ADDRESS_0, &ioaddr0);
412: pcibios_read_config_byte(bus, devfn, PCI_INTERRUPT_LINE, &irq);
413: pcibios_read_config_word(bus, devfn, PCI_DEVICE_ID, &chip_id);
414: ioaddr = ioaddr0 & ~3;
415: dev->irq = irq;
416: #endif
417: }
418:
419: dev->base_addr = ioaddr;
420: printk(KERN_INFO "%s: SMC EPIC/100 (chip ID %4.4x) at %#3x, IRQ %d, ",
421: dev->name, chip_id, ioaddr, dev->irq);
422:
423: /* Bring the chip out of low-power mode. */
424: outl(0x4200, ioaddr + GENCTL);
425: /* Magic?! If we don't set this bit the MII interface won't work. */
426: outl(0x0008, ioaddr + TEST1);
427:
428: /* Turn on the MII transceiver. */
429: outl(0x12, ioaddr + MIICfg);
430: if (chip_id == 6)
431: outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
432: outl(0x0200, ioaddr + GENCTL);
433:
434: /* This could also be read from the EEPROM. */
435: for (i = 0; i < 3; i++)
436: ((u16 *)dev->dev_addr)[i] = inw(ioaddr + LAN0 + i*4);
437:
438: for (i = 0; i < 5; i++)
439: printk("%2.2x:", dev->dev_addr[i]);
440: printk("%2.2x.\n", dev->dev_addr[i]);
441:
442: if (epic_debug > 1) {
443: printk(KERN_DEBUG "%s: EEPROM contents\n", dev->name);
444: for (i = 0; i < 64; i++)
445: printk(" %4.4x%s", read_eeprom(ioaddr, i),
446: i % 16 == 15 ? "\n" : "");
447: }
448:
449: /* We do a request_region() to register /proc/ioports info. */
450: request_region(ioaddr, EPIC_TOTAL_SIZE, "SMC EPIC/100");
451:
452: /* The data structures must be quadword aligned. */
453: ep = kmalloc(sizeof(*ep), GFP_KERNEL | GFP_DMA);
454: memset(ep, 0, sizeof(*ep));
455: dev->priv = ep;
456:
457: ep->next_module = root_epic_dev;
458: root_epic_dev = dev;
459:
460: ep->pci_bus = bus;
461: ep->pci_dev_fn = devfn;
462: ep->chip_id = chip_id;
463:
464: /* Find the connected MII xcvrs.
465: Doing this in open() would allow detecting external xcvrs later, but
466: takes too much time. */
467: {
468: int phy, phy_idx;
469: for (phy = 1, phy_idx = 0; phy < 32 && phy_idx < sizeof(ep->phys);
470: phy++) {
471: int mii_status = mdio_read(ioaddr, phy, 1);
472: if (mii_status != 0xffff && mii_status != 0x0000) {
473: ep->phys[phy_idx++] = phy;
474: printk(KERN_INFO "%s: MII transceiver #%d control "
475: "%4.4x status %4.4x.\n"
476: KERN_INFO "%s: Autonegotiation advertising %4.4x "
477: "link partner %4.4x.\n",
478: dev->name, phy, mdio_read(ioaddr, phy, 0), mii_status,
479: dev->name, mdio_read(ioaddr, phy, 4),
480: mdio_read(ioaddr, phy, 5));
481: }
482: }
483: if (phy_idx == 0) {
484: printk(KERN_WARNING "%s: ***WARNING***: No MII transceiver found!\n",
485: dev->name);
486: /* Use the known PHY address of the EPII. */
487: ep->phys[0] = 3;
488: }
489: }
490:
491: /* Turn off the MII xcvr (175 only!), leave the chip in low-power mode. */
492: if (ep->chip_id == 6)
493: outl(inl(ioaddr + NVCTL) & ~0x483C, ioaddr + NVCTL);
494: outl(0x0008, ioaddr + GENCTL);
495:
496: /* The lower four bits are the media type. */
497: ep->force_fd = duplex;
498: ep->default_port = option;
499: if (ep->default_port)
500: ep->medialock = 1;
501:
502: /* The Epic-specific entries in the device structure. */
503: dev->open = &epic_open;
504: dev->hard_start_xmit = &epic_start_xmit;
505: dev->stop = &epic_close;
506: dev->get_stats = &epic_get_stats;
507: dev->set_multicast_list = &set_rx_mode;
508: dev->do_ioctl = &mii_ioctl;
509:
510: return dev;
511: }
512:
513: /* Serial EEPROM section. */
514:
515: /* EEPROM_Ctrl bits. */
516: #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
517: #define EE_CS 0x02 /* EEPROM chip select. */
518: #define EE_DATA_WRITE 0x08 /* EEPROM chip data in. */
519: #define EE_WRITE_0 0x01
520: #define EE_WRITE_1 0x09
521: #define EE_DATA_READ 0x10 /* EEPROM chip data out. */
522: #define EE_ENB (0x0001 | EE_CS)
523:
524: /* Delay between EEPROM clock transitions.
525: No extra delay is needed with 33Mhz PCI, but 66Mhz is untested.
526: */
527:
528: #ifdef _LINUX_DELAY_H
529: #define eeprom_delay(nanosec) udelay(1)
530: #else
531: #define eeprom_delay(nanosec) do { ; } while (0)
532: #endif
533:
534: /* The EEPROM commands include the alway-set leading bit. */
535: #define EE_WRITE_CMD (5 << 6)
536: #define EE_READ64_CMD (6 << 6)
537: #define EE_READ256_CMD (6 << 8)
538: #define EE_ERASE_CMD (7 << 6)
539:
540: static int read_eeprom(long ioaddr, int location)
541: {
542: int i;
543: int retval = 0;
544: long ee_addr = ioaddr + EECTL;
545: int read_cmd = location |
546: (inl(ee_addr) & 0x40) ? EE_READ64_CMD : EE_READ256_CMD;
547:
548: printk("EEctrl is %x.\n", inl(ee_addr));
549: outl(EE_ENB & ~EE_CS, ee_addr);
550: outl(EE_ENB, ee_addr);
551:
552: /* Shift the read command bits out. */
553: for (i = 12; i >= 0; i--) {
554: short dataval = (read_cmd & (1 << i)) ? EE_WRITE_1 : EE_WRITE_0;
555: outl(EE_ENB | dataval, ee_addr);
556: eeprom_delay(100);
557: outl(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
558: eeprom_delay(150);
559: }
560: outl(EE_ENB, ee_addr);
561:
562: for (i = 16; i > 0; i--) {
563: outl(EE_ENB | EE_SHIFT_CLK, ee_addr);
564: eeprom_delay(100);
565: retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0);
566: outl(EE_ENB, ee_addr);
567: eeprom_delay(100);
568: }
569:
570: /* Terminate the EEPROM access. */
571: outl(EE_ENB & ~EE_CS, ee_addr);
572: return retval;
573: }
574:
575: #define MII_READOP 1
576: #define MII_WRITEOP 2
577: static int mdio_read(long ioaddr, int phy_id, int location)
578: {
579: int i;
580:
581: outl((phy_id << 9) | (location << 4) | MII_READOP, ioaddr + MIICtrl);
582: /* Typical operation takes < 50 ticks. */
583: for (i = 4000; i > 0; i--)
584: if ((inl(ioaddr + MIICtrl) & MII_READOP) == 0)
585: return inw(ioaddr + MIIData);
586: return 0xffff;
587: }
588:
589: static void mdio_write(long ioaddr, int phy_id, int location, int value)
590: {
591: int i;
592:
593: outw(value, ioaddr + MIIData);
594: outl((phy_id << 9) | (location << 4) | MII_WRITEOP, ioaddr + MIICtrl);
595: for (i = 10000; i > 0; i--) {
596: if ((inl(ioaddr + MIICtrl) & MII_WRITEOP) == 0)
597: break;
598: }
599: return;
600: }
601:
602:
603: static int
604: epic_open(struct device *dev)
605: {
606: struct epic_private *ep = (struct epic_private *)dev->priv;
607: long ioaddr = dev->base_addr;
608: int i;
609: int mii_reg5;
610: ep->full_duplex = ep->force_fd;
611:
612: /* Soft reset the chip. */
613: outl(0x4001, ioaddr + GENCTL);
614:
615: if (request_irq(dev->irq, &epic_interrupt, SA_SHIRQ, "SMC EPIC/100", dev))
616: return -EAGAIN;
617:
618: MOD_INC_USE_COUNT;
619:
620: epic_init_ring(dev);
621:
622: outl(0x4000, ioaddr + GENCTL);
623: /* This next magic! line by Ken Yamaguchi.. ?? */
624: outl(0x0008, ioaddr + TEST1);
625:
626: /* Pull the chip out of low-power mode, enable interrupts, and set for
627: PCI read multiple. The MIIcfg setting and strange write order are
628: required by the details of which bits are reset and the transceiver
629: wiring on the Ositech CardBus card.
630: */
631: outl(0x12, ioaddr + MIICfg);
632: if (ep->chip_id == 6)
633: outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
634:
635: #if defined(__powerpc__) || defined(__sparc__) /* Big endian */
636: outl(0x0432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
637: #else
638: outl(0x0412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
639: #endif
640:
641: for (i = 0; i < 3; i++)
642: outl(((u16*)dev->dev_addr)[i], ioaddr + LAN0 + i*4);
643:
644: outl(TX_FIFO_THRESH, ioaddr + TxThresh);
645:
646: mii_reg5 = mdio_read(ioaddr, ep->phys[0], 5);
647: if (mii_reg5 != 0xffff) {
648: if ((mii_reg5 & 0x0100) || (mii_reg5 & 0x01C0) == 0x0040)
649: ep->full_duplex = 1;
650: else if (! (mii_reg5 & 0x4000))
651: mdio_write(ioaddr, ep->phys[0], 0, 0x1200);
652: if (epic_debug > 1)
653: printk(KERN_INFO "%s: Setting %s-duplex based on MII xcvr %d"
654: " register read of %4.4x.\n", dev->name,
655: ep->full_duplex ? "full" : "half", ep->phys[0], mii_reg5);
656: }
657:
658: outl(ep->full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
659: outl(virt_to_bus(ep->rx_ring), ioaddr + PRxCDAR);
660: outl(virt_to_bus(ep->tx_ring), ioaddr + PTxCDAR);
661:
662: /* Start the chip's Rx process. */
663: set_rx_mode(dev);
664: outl(0x000A, ioaddr + COMMAND);
665:
666: dev->tbusy = 0;
667: dev->interrupt = 0;
668: dev->start = 1;
669:
670: /* Enable interrupts by setting the interrupt mask. */
671: outl((ep->chip_id == 6 ? PCIBusErr175 : PCIBusErr170)
672: | CntFull | TxUnderrun | TxDone
673: | RxError | RxOverflow | RxFull | RxHeader | RxDone,
674: ioaddr + INTMASK);
675:
676: if (epic_debug > 1)
677: printk(KERN_DEBUG "%s: epic_open() ioaddr %lx IRQ %d status %4.4x "
678: "%s-duplex.\n",
679: dev->name, ioaddr, dev->irq, inl(ioaddr + GENCTL),
680: ep->full_duplex ? "full" : "half");
681:
682: /* Set the timer to switch to check for link beat and perhaps switch
683: to an alternate media type. */
684: init_timer(&ep->timer);
685: ep->timer.expires = RUN_AT((24*HZ)/10); /* 2.4 sec. */
686: ep->timer.data = (unsigned long)dev;
687: ep->timer.function = &epic_timer; /* timer handler */
688: add_timer(&ep->timer);
689:
690: return 0;
691: }
692:
693: /* Reset the chip to recover from a PCI transaction error.
694: This may occur at interrupt time. */
695: static void epic_pause(struct device *dev)
696: {
697: long ioaddr = dev->base_addr;
698: struct epic_private *ep = (struct epic_private *)dev->priv;
699:
700: /* Disable interrupts by clearing the interrupt mask. */
701: outl(0x00000000, ioaddr + INTMASK);
702: /* Stop the chip's Tx and Rx DMA processes. */
703: outw(0x0061, ioaddr + COMMAND);
704:
705: /* Update the error counts. */
706: if (inw(ioaddr + COMMAND) != 0xffff) {
707: ep->stats.rx_missed_errors += inb(ioaddr + MPCNT);
708: ep->stats.rx_frame_errors += inb(ioaddr + ALICNT);
709: ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
710: }
711:
712: /* Remove the packets on the Rx queue. */
713: epic_rx(dev);
714: }
715:
716: static void epic_restart(struct device *dev)
717: {
718: long ioaddr = dev->base_addr;
719: struct epic_private *ep = (struct epic_private *)dev->priv;
720: int i;
721:
722: printk(KERN_DEBUG "%s: Restarting the EPIC chip, Rx %d/%d Tx %d/%d.\n",
723: dev->name, ep->cur_rx, ep->dirty_rx, ep->dirty_tx, ep->cur_tx);
724: /* Soft reset the chip. */
725: outl(0x0001, ioaddr + GENCTL);
726:
727: udelay(1);
728: /* Duplicate code from epic_open(). */
729: outl(0x0008, ioaddr + TEST1);
730:
731: #if defined(__powerpc__) /* Big endian */
732: outl(0x0432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
733: #else
734: outl(0x0412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
735: #endif
736: outl(0x12, ioaddr + MIICfg);
737: if (ep->chip_id == 6)
738: outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
739:
740: for (i = 0; i < 3; i++)
741: outl(((u16*)dev->dev_addr)[i], ioaddr + LAN0 + i*4);
742:
743: outl(TX_FIFO_THRESH, ioaddr + TxThresh);
744: outl(ep->full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
745: outl(virt_to_bus(&ep->rx_ring[ep->cur_rx%RX_RING_SIZE]), ioaddr + PRxCDAR);
746: outl(virt_to_bus(&ep->tx_ring[ep->dirty_tx%TX_RING_SIZE]),
747: ioaddr + PTxCDAR);
748:
749: /* Start the chip's Rx process. */
750: set_rx_mode(dev);
751: outl(0x000A, ioaddr + COMMAND);
752:
753: /* Enable interrupts by setting the interrupt mask. */
754: outl((ep->chip_id == 6 ? PCIBusErr175 : PCIBusErr170)
755: | CntFull | TxUnderrun | TxDone
756: | RxError | RxOverflow | RxFull | RxHeader | RxDone,
757: ioaddr + INTMASK);
758: printk(KERN_DEBUG "%s: epic_restart() done, cmd status %4.4x, ctl %4.4x"
759: " interrupt %4.4x.\n",
760: dev->name, inl(ioaddr + COMMAND), inl(ioaddr + GENCTL),
761: inl(ioaddr + INTSTAT));
762: return;
763: }
764:
765: static void epic_timer(unsigned long data)
766: {
767: struct device *dev = (struct device *)data;
768: struct epic_private *ep = (struct epic_private *)dev->priv;
769: long ioaddr = dev->base_addr;
770: int next_tick = 0;
771: int mii_reg5 = mdio_read(ioaddr, ep->phys[0], 5);
772:
773: if (epic_debug > 3) {
774: printk(KERN_DEBUG "%s: Media selection tick, Tx status %8.8x.\n",
775: dev->name, inl(ioaddr + TxSTAT));
776: printk(KERN_DEBUG "%s: Other registers are IntMask %4.4x "
777: "IntStatus %4.4x RxStatus %4.4x.\n",
778: dev->name, inl(ioaddr + INTMASK), inl(ioaddr + INTSTAT),
779: inl(ioaddr + RxSTAT));
780: }
781: if (! ep->force_fd && mii_reg5 != 0xffff) {
782: int duplex = (mii_reg5&0x0100) || (mii_reg5 & 0x01C0) == 0x0040;
783: if (ep->full_duplex != duplex) {
784: ep->full_duplex = duplex;
785: printk(KERN_INFO "%s: Setting %s-duplex based on MII #%d link"
786: " partner capability of %4.4x.\n", dev->name,
787: ep->full_duplex ? "full" : "half", ep->phys[0], mii_reg5);
788: outl(ep->full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
789: }
790: next_tick = 60*HZ;
791: }
792:
793: if (next_tick) {
794: ep->timer.expires = RUN_AT(next_tick);
795: add_timer(&ep->timer);
796: }
797: }
798:
799: static void epic_tx_timeout(struct device *dev)
800: {
801: struct epic_private *ep = (struct epic_private *)dev->priv;
802: long ioaddr = dev->base_addr;
803:
804: if (epic_debug > 0) {
805: printk(KERN_WARNING "%s: Transmit timeout using MII device, "
806: "Tx status %4.4x.\n",
807: dev->name, inw(ioaddr + TxSTAT));
808: if (epic_debug > 1) {
809: printk(KERN_DEBUG "%s: Tx indices: dirty_tx %d, cur_tx %d.\n",
810: dev->name, ep->dirty_tx, ep->cur_tx);
811: }
812: }
813: if (inw(ioaddr + TxSTAT) & 0x10) { /* Tx FIFO underflow. */
814: ep->stats.tx_fifo_errors++;
815: /* Restart the transmit process. */
816: outl(0x0080, ioaddr + COMMAND);
817: }
818:
819: /* Perhaps stop and restart the chip's Tx processes . */
820: /* Trigger a transmit demand. */
821: outl(0x0004, dev->base_addr + COMMAND);
822:
823: dev->trans_start = jiffies;
824: ep->stats.tx_errors++;
825: return;
826: }
827:
828: /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
829: static void
830: epic_init_ring(struct device *dev)
831: {
832: struct epic_private *ep = (struct epic_private *)dev->priv;
833: int i;
834:
835: ep->tx_full = 0;
836: ep->cur_rx = ep->cur_tx = 0;
837: ep->dirty_rx = ep->dirty_tx = 0;
838:
839: for (i = 0; i < RX_RING_SIZE; i++) {
840: ep->rx_ring[i].status = 0x8000; /* Owned by Epic chip */
841: ep->rx_ring[i].buflength = PKT_BUF_SZ;
842: {
843: /* Note the receive buffer must be longword aligned.
844: dev_alloc_skb() provides 16 byte alignment. But do *not*
845: use skb_reserve() to align the IP header! */
846: struct sk_buff *skb;
847: skb = dev_alloc_skb(PKT_BUF_SZ);
848: ep->rx_skbuff[i] = skb;
849: if (skb == NULL)
850: break; /* Bad news! */
851: skb->dev = dev; /* Mark as being used by this device. */
852: skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
853: ep->rx_ring[i].bufaddr = virt_to_bus(skb->tail);
854: }
855: ep->rx_ring[i].next = virt_to_bus(&ep->rx_ring[i+1]);
856: }
857: /* Mark the last entry as wrapping the ring. */
858: ep->rx_ring[i-1].next = virt_to_bus(&ep->rx_ring[0]);
859:
860: /* The Tx buffer descriptor is filled in as needed, but we
861: do need to clear the ownership bit. */
862: for (i = 0; i < TX_RING_SIZE; i++) {
863: ep->tx_skbuff[i] = 0;
864: ep->tx_ring[i].status = 0x0000;
865: ep->tx_ring[i].next = virt_to_bus(&ep->tx_ring[i+1]);
866: }
867: ep->tx_ring[i-1].next = virt_to_bus(&ep->tx_ring[0]);
868: }
869:
870: static int
871: epic_start_xmit(struct sk_buff *skb, struct device *dev)
872: {
873: struct epic_private *ep = (struct epic_private *)dev->priv;
874: int entry;
875: u32 flag;
876:
877: /* Block a timer-based transmit from overlapping. This could better be
878: done with atomic_swap(1, dev->tbusy), but set_bit() works as well. */
879: if (test_and_set_bit(0, (void*)&dev->tbusy) != 0) {
880: if (jiffies - dev->trans_start < TX_TIMEOUT)
881: return 1;
882: epic_tx_timeout(dev);
883: return 1;
884: }
885:
886: /* Caution: the write order is important here, set the base address
887: with the "ownership" bits last. */
888:
889: /* Calculate the next Tx descriptor entry. */
890: entry = ep->cur_tx % TX_RING_SIZE;
891:
892: ep->tx_skbuff[entry] = skb;
893: ep->tx_ring[entry].txlength = (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN);
894: ep->tx_ring[entry].bufaddr = virt_to_bus(skb->data);
895: ep->tx_ring[entry].buflength = skb->len;
896:
897: if (ep->cur_tx - ep->dirty_tx < TX_RING_SIZE/2) {/* Typical path */
898: flag = 0x10; /* No interrupt */
899: clear_bit(0, (void*)&dev->tbusy);
900: } else if (ep->cur_tx - ep->dirty_tx == TX_RING_SIZE/2) {
901: flag = 0x14; /* Tx-done intr. */
902: clear_bit(0, (void*)&dev->tbusy);
903: } else if (ep->cur_tx - ep->dirty_tx < TX_RING_SIZE - 2) {
904: flag = 0x10; /* No Tx-done intr. */
905: clear_bit(0, (void*)&dev->tbusy);
906: } else {
907: /* Leave room for two additional entries. */
908: flag = 0x14; /* Tx-done intr. */
909: ep->tx_full = 1;
910: }
911:
912: ep->tx_ring[entry].control = flag;
913: ep->tx_ring[entry].status = 0x8000; /* Pass ownership to the chip. */
914: ep->cur_tx++;
915: /* Trigger an immediate transmit demand. */
916: outl(0x0004, dev->base_addr + COMMAND);
917:
918: dev->trans_start = jiffies;
919: if (epic_debug > 4)
920: printk(KERN_DEBUG "%s: Queued Tx packet size %d to slot %d, "
921: "flag %2.2x Tx status %8.8x.\n",
922: dev->name, (int)skb->len, entry, flag,
923: inl(dev->base_addr + TxSTAT));
924:
925: return 0;
926: }
927:
928: /* The interrupt handler does all of the Rx thread work and cleans up
929: after the Tx thread. */
930: static void epic_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
931: {
932: struct device *dev = (struct device *)dev_instance;
933: struct epic_private *ep;
934: int status, ioaddr, boguscnt = max_interrupt_work;
935:
936: ioaddr = dev->base_addr;
937: ep = (struct epic_private *)dev->priv;
938:
939: #if defined(__i386__)
940: /* A lock to prevent simultaneous entry bug on Intel SMP machines. */
941: if (test_and_set_bit(0, (void*)&dev->interrupt)) {
942: printk(KERN_ERR"%s: SMP simultaneous entry of an interrupt handler.\n",
943: dev->name);
944: dev->interrupt = 0; /* Avoid halting machine. */
945: return;
946: }
947: #else
948: if (dev->interrupt) {
949: printk(KERN_ERR "%s: Re-entering the interrupt handler.\n", dev->name);
950: return;
951: }
952: dev->interrupt = 1;
953: #endif
954:
955: do {
956: status = inl(ioaddr + INTSTAT);
957: /* Acknowledge all of the current interrupt sources ASAP. */
958: outl(status & 0x00007fff, ioaddr + INTSTAT);
959:
960: if (epic_debug > 4)
961: printk("%s: interrupt interrupt=%#8.8x new intstat=%#8.8x.\n",
962: dev->name, status, inl(ioaddr + INTSTAT));
963:
964: if ((status & IntrSummary) == 0)
965: break;
966:
967: if (status & (RxDone | RxStarted | RxEarlyWarn))
968: epic_rx(dev);
969:
970: if (status & (TxEmpty | TxDone)) {
971: int dirty_tx;
972:
973: for (dirty_tx = ep->dirty_tx; dirty_tx < ep->cur_tx; dirty_tx++) {
974: int entry = dirty_tx % TX_RING_SIZE;
975: int txstatus = ep->tx_ring[entry].status;
976:
977: if (txstatus < 0)
978: break; /* It still hasn't been Txed */
979:
980: if ( ! (txstatus & 0x0001)) {
981: /* There was an major error, log it. */
982: #ifndef final_version
983: if (epic_debug > 1)
984: printk("%s: Transmit error, Tx status %8.8x.\n",
985: dev->name, txstatus);
986: #endif
987: ep->stats.tx_errors++;
988: if (txstatus & 0x1050) ep->stats.tx_aborted_errors++;
989: if (txstatus & 0x0008) ep->stats.tx_carrier_errors++;
990: if (txstatus & 0x0040) ep->stats.tx_window_errors++;
991: if (txstatus & 0x0010) ep->stats.tx_fifo_errors++;
992: #ifdef ETHER_STATS
993: if (txstatus & 0x1000) ep->stats.collisions16++;
994: #endif
995: } else {
996: #ifdef ETHER_STATS
997: if ((txstatus & 0x0002) != 0) ep->stats.tx_deferred++;
998: #endif
999: ep->stats.collisions += (txstatus >> 8) & 15;
1000: ep->stats.tx_packets++;
1001: }
1002:
1003: /* Free the original skb. */
1004: DEV_FREE_SKB(ep->tx_skbuff[entry]);
1005: ep->tx_skbuff[entry] = 0;
1006: }
1007:
1008: #ifndef final_version
1009: if (ep->cur_tx - dirty_tx > TX_RING_SIZE) {
1010: printk("%s: Out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1011: dev->name, dirty_tx, ep->cur_tx, ep->tx_full);
1012: dirty_tx += TX_RING_SIZE;
1013: }
1014: #endif
1015:
1016: if (ep->tx_full && dev->tbusy
1017: && dirty_tx > ep->cur_tx - TX_RING_SIZE + 2) {
1018: /* The ring is no longer full, clear tbusy. */
1019: ep->tx_full = 0;
1020: clear_bit(0, (void*)&dev->tbusy);
1021: mark_bh(NET_BH);
1022: }
1023:
1024: ep->dirty_tx = dirty_tx;
1025: }
1026:
1027: /* Check uncommon events all at once. */
1028: if (status & (CntFull | TxUnderrun | RxOverflow |
1029: PCIBusErr170 | PCIBusErr175)) {
1030: if (status == 0xffffffff) /* Chip failed or removed (CardBus). */
1031: break;
1032: /* Always update the error counts to avoid overhead later. */
1033: ep->stats.rx_missed_errors += inb(ioaddr + MPCNT);
1034: ep->stats.rx_frame_errors += inb(ioaddr + ALICNT);
1035: ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
1036:
1037: if (status & TxUnderrun) { /* Tx FIFO underflow. */
1038: ep->stats.tx_fifo_errors++;
1039: outl(1536, ioaddr + TxThresh);
1040: /* Restart the transmit process. */
1041: outl(0x0080, ioaddr + COMMAND);
1042: }
1043: if (status & RxOverflow) { /* Missed a Rx frame. */
1044: ep->stats.rx_errors++;
1045: }
1046: if (status & PCIBusErr170) {
1047: printk(KERN_ERR "%s: PCI Bus Error! EPIC status %4.4x.\n",
1048: dev->name, status);
1049: epic_pause(dev);
1050: epic_restart(dev);
1051: }
1052: /* Clear all error sources. */
1053: outl(status & 0x7f18, ioaddr + INTSTAT);
1054: }
1055: if (--boguscnt < 0) {
1056: printk(KERN_ERR "%s: Too much work at interrupt, "
1057: "IntrStatus=0x%8.8x.\n",
1058: dev->name, status);
1059: /* Clear all interrupt sources. */
1060: outl(0x0001ffff, ioaddr + INTSTAT);
1061: break;
1062: }
1063: } while (1);
1064:
1065: if (epic_debug > 3)
1066: printk(KERN_DEBUG "%s: exiting interrupt, intr_status=%#4.4x.\n",
1067: dev->name, inl(ioaddr + INTSTAT));
1068:
1069: #if defined(__i386__)
1070: clear_bit(0, (void*)&dev->interrupt);
1071: #else
1072: dev->interrupt = 0;
1073: #endif
1074: return;
1075: }
1076:
1077: static int epic_rx(struct device *dev)
1078: {
1079: struct epic_private *ep = (struct epic_private *)dev->priv;
1080: int entry = ep->cur_rx % RX_RING_SIZE;
1081: int work_done = 0;
1082:
1083: if (epic_debug > 4)
1084: printk(KERN_DEBUG " In epic_rx(), entry %d %8.8x.\n", entry,
1085: ep->rx_ring[entry].status);
1086: /* If we own the next entry, it's a new packet. Send it up. */
1087: while (ep->rx_ring[entry].status >= 0 && ep->rx_skbuff[entry]) {
1088: int status = ep->rx_ring[entry].status;
1089:
1090: if (epic_debug > 4)
1091: printk(KERN_DEBUG " epic_rx() status was %8.8x.\n", status);
1092: if (status & 0x2006) {
1093: if (status & 0x2000) {
1094: printk(KERN_WARNING "%s: Oversized Ethernet frame spanned "
1095: "multiple buffers, status %4.4x!\n", dev->name, status);
1096: ep->stats.rx_length_errors++;
1097: } else if (status & 0x0006)
1098: /* Rx Frame errors are counted in hardware. */
1099: ep->stats.rx_errors++;
1100: } else {
1101: /* Malloc up new buffer, compatible with net-2e. */
1102: /* Omit the four octet CRC from the length. */
1103: short pkt_len = ep->rx_ring[entry].rxlength - 4;
1104: struct sk_buff *skb;
1105:
1106: /* Check if the packet is long enough to accept without copying
1107: to a minimally-sized skbuff. */
1108: if (pkt_len < rx_copybreak
1109: && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1110: skb->dev = dev;
1111: skb_reserve(skb, 2); /* 16 byte align the IP header */
1112: #if 1 /* USE_IP_COPYSUM */
1113: eth_copy_and_sum(skb, bus_to_virt(ep->rx_ring[entry].bufaddr),
1114: pkt_len, 0);
1115: skb_put(skb, pkt_len);
1116: #else
1117: memcpy(skb_put(skb, pkt_len),
1118: bus_to_virt(ep->rx_ring[entry].bufaddr), pkt_len);
1119: #endif
1120: } else {
1121: skb_put(skb = ep->rx_skbuff[entry], pkt_len);
1122: ep->rx_skbuff[entry] = NULL;
1123: }
1124: skb->protocol = eth_type_trans(skb, dev);
1125: netif_rx(skb);
1126: ep->stats.rx_packets++;
1127: }
1128: work_done++;
1129: entry = (++ep->cur_rx) % RX_RING_SIZE;
1130: }
1131:
1132: /* Refill the Rx ring buffers. */
1133: for (; ep->cur_rx - ep->dirty_rx > 0; ep->dirty_rx++) {
1134: entry = ep->dirty_rx % RX_RING_SIZE;
1135: if (ep->rx_skbuff[entry] == NULL) {
1136: struct sk_buff *skb;
1137: skb = ep->rx_skbuff[entry] = dev_alloc_skb(PKT_BUF_SZ);
1138: if (skb == NULL)
1139: break;
1140: skb->dev = dev; /* Mark as being used by this device. */
1141: skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1142: ep->rx_ring[entry].bufaddr = virt_to_bus(skb->tail);
1143: work_done++;
1144: }
1145: ep->rx_ring[entry].status = 0x8000;
1146: }
1147: return work_done;
1148: }
1149:
1150: static int epic_close(struct device *dev)
1151: {
1152: long ioaddr = dev->base_addr;
1153: struct epic_private *ep = (struct epic_private *)dev->priv;
1154: int i;
1155:
1156: dev->start = 0;
1157: dev->tbusy = 1;
1158:
1159: if (epic_debug > 1)
1160: printk(KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n",
1161: dev->name, inl(ioaddr + INTSTAT));
1162:
1163: /* Disable interrupts by clearing the interrupt mask. */
1164: outl(0x00000000, ioaddr + INTMASK);
1165: /* Stop the chip's Tx and Rx DMA processes. */
1166: outw(0x0061, ioaddr + COMMAND);
1167:
1168: /* Update the error counts. */
1169: ep->stats.rx_missed_errors += inb(ioaddr + MPCNT);
1170: ep->stats.rx_frame_errors += inb(ioaddr + ALICNT);
1171: ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
1172:
1173: del_timer(&ep->timer);
1174:
1175: free_irq(dev->irq, dev);
1176:
1177: /* Free all the skbuffs in the Rx queue. */
1178: for (i = 0; i < RX_RING_SIZE; i++) {
1179: struct sk_buff *skb = ep->rx_skbuff[i];
1180: ep->rx_skbuff[i] = 0;
1181: ep->rx_ring[i].status = 0; /* Not owned by Epic chip. */
1182: ep->rx_ring[i].buflength = 0;
1183: ep->rx_ring[i].bufaddr = 0xBADF00D0; /* An invalid address. */
1184: if (skb) {
1185: #if LINUX_VERSION_CODE < 0x20100
1186: skb->free = 1;
1187: #endif
1188: DEV_FREE_SKB(skb);
1189: }
1190: }
1191: for (i = 0; i < TX_RING_SIZE; i++) {
1192: if (ep->tx_skbuff[i])
1193: DEV_FREE_SKB(ep->tx_skbuff[i]);
1194: ep->tx_skbuff[i] = 0;
1195: }
1196:
1197:
1198: /* Green! Leave the chip in low-power mode. */
1199: outl(0x0008, ioaddr + GENCTL);
1200:
1201: MOD_DEC_USE_COUNT;
1202:
1203: return 0;
1204: }
1205:
1206: static struct net_device_stats *epic_get_stats(struct device *dev)
1207: {
1208: struct epic_private *ep = (struct epic_private *)dev->priv;
1209: long ioaddr = dev->base_addr;
1210:
1211: if (dev->start) {
1212: /* Update the error counts. */
1213: ep->stats.rx_missed_errors += inb(ioaddr + MPCNT);
1214: ep->stats.rx_frame_errors += inb(ioaddr + ALICNT);
1215: ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
1216: }
1217:
1218: return &ep->stats;
1219: }
1220:
1221: /* Set or clear the multicast filter for this adaptor.
1222: Note that we only use exclusion around actually queueing the
1223: new frame, not around filling ep->setup_frame. This is non-deterministic
1224: when re-entered but still correct. */
1225:
1226: /* The little-endian AUTODIN II ethernet CRC calculation.
1227: N.B. Do not use for bulk data, use a table-based routine instead.
1228: This is common code and should be moved to net/core/crc.c */
1229: static unsigned const ethernet_polynomial_le = 0xedb88320U;
1230: static inline unsigned ether_crc_le(int length, unsigned char *data)
1231: {
1232: unsigned int crc = 0xffffffff; /* Initial value. */
1233: while(--length >= 0) {
1234: unsigned char current_octet = *data++;
1235: int bit;
1236: for (bit = 8; --bit >= 0; current_octet >>= 1) {
1237: if ((crc ^ current_octet) & 1) {
1238: crc >>= 1;
1239: crc ^= ethernet_polynomial_le;
1240: } else
1241: crc >>= 1;
1242: }
1243: }
1244: return crc;
1245: }
1246:
1247:
1248: static void set_rx_mode(struct device *dev)
1249: {
1250: long ioaddr = dev->base_addr;
1251: struct epic_private *ep = (struct epic_private *)dev->priv;
1252: unsigned char mc_filter[8]; /* Multicast hash filter */
1253: int i;
1254:
1255: if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1256: outl(0x002C, ioaddr + RxCtrl);
1257: /* Unconditionally log net taps. */
1258: printk(KERN_INFO "%s: Promiscuous mode enabled.\n", dev->name);
1259: memset(mc_filter, 0xff, sizeof(mc_filter));
1260: } else if ((dev->mc_count > 0) || (dev->flags & IFF_ALLMULTI)) {
1261: /* There is apparently a chip bug, so the multicast filter
1262: is never enabled. */
1263: /* Too many to filter perfectly -- accept all multicasts. */
1264: memset(mc_filter, 0xff, sizeof(mc_filter));
1265: outl(0x000C, ioaddr + RxCtrl);
1266: } else if (dev->mc_count == 0) {
1267: outl(0x0004, ioaddr + RxCtrl);
1268: return;
1269: } else { /* Never executed, for now. */
1270: struct dev_mc_list *mclist;
1271:
1272: memset(mc_filter, 0, sizeof(mc_filter));
1273: for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1274: i++, mclist = mclist->next)
1275: set_bit(ether_crc_le(ETH_ALEN, mclist->dmi_addr) & 0x3f,
1276: mc_filter);
1277: }
1278: /* ToDo: perhaps we need to stop the Tx and Rx process here? */
1279: if (memcmp(mc_filter, ep->mc_filter, sizeof(mc_filter))) {
1280: for (i = 0; i < 4; i++)
1281: outw(((u16 *)mc_filter)[i], ioaddr + MC0 + i*4);
1282: memcpy(ep->mc_filter, mc_filter, sizeof(mc_filter));
1283: }
1284: return;
1285: }
1286:
1287: static int mii_ioctl(struct device *dev, struct ifreq *rq, int cmd)
1288: {
1289: long ioaddr = dev->base_addr;
1290: u16 *data = (u16 *)&rq->ifr_data;
1291:
1292: switch(cmd) {
1293: case SIOCDEVPRIVATE: /* Get the address of the PHY in use. */
1294: data[0] = ((struct epic_private *)dev->priv)->phys[0] & 0x1f;
1295: /* Fall Through */
1296: case SIOCDEVPRIVATE+1: /* Read the specified MII register. */
1297: if (! dev->start) {
1298: outl(0x0200, ioaddr + GENCTL);
1299: outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
1300: }
1301: data[3] = mdio_read(ioaddr, data[0] & 0x1f, data[1] & 0x1f);
1302: if (! dev->start) {
1303: #ifdef notdef
1304: outl(0x0008, ioaddr + GENCTL);
1305: outl((inl(ioaddr + NVCTL) & ~0x483C) | 0x0000, ioaddr + NVCTL);
1306: #endif
1307: }
1308: return 0;
1309: case SIOCDEVPRIVATE+2: /* Write the specified MII register */
1310: if (!suser())
1311: return -EPERM;
1312: if (! dev->start) {
1313: outl(0x0200, ioaddr + GENCTL);
1314: outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
1315: }
1316: mdio_write(ioaddr, data[0] & 0x1f, data[1] & 0x1f, data[2]);
1317: if (! dev->start) {
1318: #ifdef notdef
1319: outl(0x0008, ioaddr + GENCTL);
1320: outl((inl(ioaddr + NVCTL) & ~0x483C) | 0x0000, ioaddr + NVCTL);
1321: #endif
1322: }
1323: return 0;
1324: default:
1325: return -EOPNOTSUPP;
1326: }
1327: }
1328:
1329:
1330: #ifdef CARDBUS
1331:
1332: #include <pcmcia/driver_ops.h>
1333:
1334: static dev_node_t *epic_attach(dev_locator_t *loc)
1335: {
1336: struct device *dev;
1337: u16 dev_id;
1338: u32 io;
1339: u8 bus, devfn, irq;
1340:
1341: if (loc->bus != LOC_PCI) return NULL;
1342: bus = loc->b.pci.bus; devfn = loc->b.pci.devfn;
1343: printk(KERN_INFO "epic_attach(bus %d, function %d)\n", bus, devfn);
1344: pcibios_read_config_dword(bus, devfn, PCI_BASE_ADDRESS_0, &io);
1345: pcibios_read_config_byte(bus, devfn, PCI_INTERRUPT_LINE, &irq);
1346: pcibios_read_config_word(bus, devfn, PCI_DEVICE_ID, &dev_id);
1347: io &= ~3;
1348: dev = epic_probe1(bus, devfn, NULL, -1);
1349: if (dev) {
1350: dev_node_t *node = kmalloc(sizeof(dev_node_t), GFP_KERNEL);
1351: strcpy(node->dev_name, dev->name);
1352: node->major = node->minor = 0;
1353: node->next = NULL;
1354: MOD_INC_USE_COUNT;
1355: return node;
1356: }
1357: return NULL;
1358: }
1359:
1360: static void epic_suspend(dev_node_t *node)
1361: {
1362: struct device **devp, **next;
1363: printk(KERN_INFO "epic_suspend(%s)\n", node->dev_name);
1364: for (devp = &root_epic_dev; *devp; devp = next) {
1365: next = &((struct epic_private *)(*devp)->priv)->next_module;
1366: if (strcmp((*devp)->name, node->dev_name) == 0) break;
1367: }
1368: if (*devp) {
1369: long ioaddr = (*devp)->base_addr;
1370: epic_pause(*devp);
1371: /* Put the chip into low-power mode. */
1372: outl(0x0008, ioaddr + GENCTL);
1373: }
1374: }
1375: static void epic_resume(dev_node_t *node)
1376: {
1377: struct device **devp, **next;
1378: printk(KERN_INFO "epic_resume(%s)\n", node->dev_name);
1379: for (devp = &root_epic_dev; *devp; devp = next) {
1380: next = &((struct epic_private *)(*devp)->priv)->next_module;
1381: if (strcmp((*devp)->name, node->dev_name) == 0) break;
1382: }
1383: if (*devp) {
1384: epic_restart(*devp);
1385: }
1386: }
1387: static void epic_detach(dev_node_t *node)
1388: {
1389: struct device **devp, **next;
1390: printk(KERN_INFO "epic_detach(%s)\n", node->dev_name);
1391: for (devp = &root_epic_dev; *devp; devp = next) {
1392: next = &((struct epic_private *)(*devp)->priv)->next_module;
1393: if (strcmp((*devp)->name, node->dev_name) == 0) break;
1394: }
1395: if (*devp) {
1396: unregister_netdev(*devp);
1397: kfree(*devp);
1398: *devp = *next;
1399: kfree(node);
1400: MOD_DEC_USE_COUNT;
1401: }
1402: }
1403:
1404: struct driver_operations epic_ops = {
1405: "epic_cb", epic_attach, epic_suspend, epic_resume, epic_detach
1406: };
1407:
1408: #endif /* Cardbus support */
1409:
1410:
1411: #ifdef MODULE
1412:
1413: /* An additional parameter that may be passed in... */
1414: static int debug = -1;
1415:
1416: int
1417: init_module(void)
1418: {
1419: if (debug >= 0)
1420: epic_debug = debug;
1421:
1422: #ifdef CARDBUS
1423: register_driver(&epic_ops);
1424: return 0;
1425: #else
1426: return epic100_probe(0);
1427: #endif
1428: }
1429:
1430: void
1431: cleanup_module(void)
1432: {
1433: struct device *next_dev;
1434:
1435: #ifdef CARDBUS
1436: unregister_driver(&epic_ops);
1437: #endif
1438:
1439: /* No need to check MOD_IN_USE, as sys_delete_module() checks. */
1440: while (root_epic_dev) {
1441: next_dev = ((struct epic_private *)root_epic_dev->priv)->next_module;
1442: unregister_netdev(root_epic_dev);
1443: release_region(root_epic_dev->base_addr, EPIC_TOTAL_SIZE);
1444: kfree(root_epic_dev);
1445: root_epic_dev = next_dev;
1446: }
1447: }
1448:
1449: #endif /* MODULE */
1450:
1451: /*
1452: * Local variables:
1453: * compile-command: "gcc -DMODULE -D__KERNEL__ -Wall -Wstrict-prototypes -O6 -c epic100.c `[ -f /usr/include/linux/modversions.h ] && echo -DMODVERSIONS`"
1454: * cardbus-compile-command: "gcc -DCARDBUS -DMODULE -D__KERNEL__ -Wall -Wstrict-prototypes -O6 -c epic100.c -o epic_cb.o -I/usr/src/pcmcia-cs-3.0.5/include/"
1455: * c-indent-level: 4
1456: * c-basic-offset: 4
1457: * tab-width: 4
1458: * End:
1459: */
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