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1.1 root 1: /*
2: * eth82586.h: Intel EtherExpress defines
3: *
4: * Written 1995 by John Sullivan
5: * See eexpress.c for further details
6: * documentation and usage to do.
7: */
8:
9: /*
10: * EtherExpress card register addresses
11: * as offsets from the base IO region (dev->base_addr)
12: */
13:
14: #define DATAPORT 0x0000
15: #define WRITE_PTR 0x0002
16: #define READ_PTR 0x0004
17: #define SIGNAL_CA 0x0006
18: #define SET_IRQ 0x0007
19: #define SM_PTR 0x0008
20: #define MEM_Ctrl 0x000b
21: #define MEM_Page_Ctrl 0x000c
22: #define Config 0x000d
23: #define EEPROM_Ctrl 0x000e
24: #define ID_PORT 0x000f
25:
26: /*
27: * offset to shadowed memory, 0 <= x <= 31. We don't use this yet,
28: * but may in the future. Is shadow memory access any faster than
29: * dataport access?
30: */
31: #define SM_ADDR(x) (0x4000+((x&0x10)<<10)+(x&0xf))
32:
33: /* Always mirrors eexp-memory at 0x0008-0x000f */
34: #define SCB_STATUS 0xc008
35: #define SCB_CMD 0xc00a
36: #define SCB_CBL 0xc00c
37: #define SCB_RFA 0xc00e
38:
39:
40:
41: /*
42: * card register defines
43: */
44:
45: /* SET_IRQ */
46: #define SIRQ_en 0x08
47: #define SIRQ_dis 0x00
48:
49: /* Config */
50: #define set_loopback outb(inb(ioaddr+Config)|0x02,ioaddr+Config)
51: #define clear_loopback outb(inb(ioaddr+Config)&0xfd,ioaddr+Config)
52:
53: /* EEPROM_Ctrl */
54: #define EC_Clk 0x01
55: #define EC_CS 0x02
56: #define EC_Wr 0x04
57: #define EC_Rd 0x08
58: #define ASIC_RST 0x40
59: #define i586_RST 0x80
60:
61: #define eeprom_delay() { int _i = 40; while (--_i>0) { __SLOW_DOWN_IO; }}
62:
63: /*
64: * i82586 Memory Configuration
65: */
66:
67: /* (System Configuration Pointer) System start up block, read after 586_RST */
68: #define SCP_START 0xfff6
69:
70:
71: /* Intermediate System Configuration Pointer */
72: #define ISCP_START 0x0000
73: /* System Command Block */
74: #define SCB_START 0x0008
75:
76: /*
77: * Start of buffer region. If we have 64k memory, eexp_hw_probe() may raise
78: * NUM_TX_BUFS. RX_BUF_END is set to the end of memory, and all space between
79: * the transmit buffer region and end of memory used for as many receive buffers
80: * as we can fit. See eexp_hw_[(rx)(tx)]init().
81: */
82: #define TX_BUF_START 0x0100
83: #define TX_BUF_SIZE ((24+ETH_FRAME_LEN+31)&~0x1f)
84: #define RX_BUF_SIZE ((32+ETH_FRAME_LEN+31)&~0x1f)
85:
86:
87:
88: /*
89: * SCB defines
90: */
91:
92: /* these functions take the SCB status word and test the relevant status bit */
93: #define SCB_complete(s) ((s&0x8000)!=0)
94: #define SCB_rxdframe(s) ((s&0x4000)!=0)
95: #define SCB_CUdead(s) ((s&0x2000)!=0)
96: #define SCB_RUdead(s) ((s&0x1000)!=0)
97: #define SCB_ack(s) (s & 0xf000)
98:
99: /* Command unit status: 0=idle, 1=suspended, 2=active */
100: #define SCB_CUstat(s) ((s&0x0300)>>8)
101:
102: /* Receive unit status: 0=idle, 1=suspended, 2=out of resources, 4=ready */
103: #define SCB_RUstat(s) ((s&0x0070)>>4)
104:
105: /* SCB commands */
106: #define SCB_CUnop 0x0000
107: #define SCB_CUstart 0x0100
108: #define SCB_CUresume 0x0200
109: #define SCB_CUsuspend 0x0300
110: #define SCB_CUabort 0x0400
111:
112: /* ? */
113: #define SCB_resetchip 0x0080
114:
115: #define SCB_RUnop 0x0000
116: #define SCB_RUstart 0x0010
117: #define SCB_RUresume 0x0020
118: #define SCB_RUsuspend 0x0030
119: #define SCB_RUabort 0x0040
120:
121:
122: /*
123: * Command block defines
124: */
125:
126: #define Stat_Done(s) ((s&0x8000)!=0)
127: #define Stat_Busy(s) ((s&0x4000)!=0)
128: #define Stat_OK(s) ((s&0x2000)!=0)
129: #define Stat_Abort(s) ((s&0x1000)!=0)
130: #define Stat_STFail ((s&0x0800)!=0)
131: #define Stat_TNoCar(s) ((s&0x0400)!=0)
132: #define Stat_TNoCTS(s) ((s&0x0200)!=0)
133: #define Stat_TNoDMA(s) ((s&0x0100)!=0)
134: #define Stat_TDefer(s) ((s&0x0080)!=0)
135: #define Stat_TColl(s) ((s&0x0040)!=0)
136: #define Stat_TXColl(s) ((s&0x0020)!=0)
137: #define Stat_NoColl(s) (s&0x000f)
138:
139: /* Cmd_END will end AFTER the command if this is the first
140: * command block after an SCB_CUstart, but BEFORE the command
141: * for all subsequent commands. Best strategy is to place
142: * Cmd_INT on the last command in the sequence, followed by a
143: * dummy Cmd_Nop with Cmd_END after this.
144: */
145: #define Cmd_END 0x8000
146: #define Cmd_SUS 0x4000
147: #define Cmd_INT 0x2000
148:
149: #define Cmd_Nop 0x0000
150: #define Cmd_SetAddr 0x0001
151: #define Cmd_Config 0x0002
152: #define Cmd_MCast 0x0003
153: #define Cmd_Xmit 0x0004
154: #define Cmd_TDR 0x0005
155: #define Cmd_Dump 0x0006
156: #define Cmd_Diag 0x0007
157:
158:
159: /*
160: * Frame Descriptor (Receive block) defines
161: */
162:
163: #define FD_Done(s) ((s&0x8000)!=0)
164: #define FD_Busy(s) ((s&0x4000)!=0)
165: #define FD_OK(s) ((s&0x2000)!=0)
166:
167: #define FD_CRC(s) ((s&0x0800)!=0)
168: #define FD_Align(s) ((s&0x0400)!=0)
169: #define FD_Resrc(s) ((s&0x0200)!=0)
170: #define FD_DMA(s) ((s&0x0100)!=0)
171: #define FD_Short(s) ((s&0x0080)!=0)
172: #define FD_NoEOF(s) ((s&0x0040)!=0)
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